CN105118867A - 4H-SiC metal semiconductor field effect transistor having partial sinking channel - Google Patents
4H-SiC metal semiconductor field effect transistor having partial sinking channel Download PDFInfo
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- CN105118867A CN105118867A CN201510532352.6A CN201510532352A CN105118867A CN 105118867 A CN105118867 A CN 105118867A CN 201510532352 A CN201510532352 A CN 201510532352A CN 105118867 A CN105118867 A CN 105118867A
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- grid leak
- cap layers
- resilient coating
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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Abstract
The invention discloses a 4H-SiC metal semiconductor field effect transistor having a partial sinking channel. The 4H-SiC metal semiconductor field effect transistor having a partial sinking channel, from the bottom to the top, comprises a 4H-SiC half insulation substrate, a P type buffer layer, and an N type channel layer; the N type channel layer surface is provided with a source electrode cap layer and a drain electrode cap layer; the surfaces of the source electrode cap layer and the drain electrode cap layer are provided with a source electrode and a drain electrode; a grating electrode is formed above the N type channel layer and close to one side of the source electrode cap layer; part of the grating electrode close to the source electrode cap layer concaves downwardly to form a concave grating structure; a concave grating drain drifting area is formed between the grating electrode and the drain electrode cap layer; a concave grating drain buffer layer is formed on the upper end surface of a P buffer layer and close to the portion between the drain electrode cap layer and the concave grating drain side; and the concave depth of the concave grating drain drifting area is identical to that of the concave grating drain buffer layer. The 4H-SIC metal semiconductor field effect transistor having a partial sinking channel has advantages that the drain electrode is big in output current, the breakdown voltage is high and frequency characteristic is good.
Description
Technical field
The present invention relates to field-effect transistor technical field, particularly a kind of 4H-SiC metal-semiconductor field effect transistor with part sinking raceway groove.
Background technology
SiC material has superior electric property, comprises broad stopband [(2.3 ~ 3.3) eV], high breakdown electric field [(0.8 ~ 3.0) × 10
6v/cm], high saturation drift velocity (2 × 10
7and high heat conductance (4.9Wcm V/cm)
-1k
-1), these characteristics can make SiC device be operated in high temperature, high power and high frequency specific condition.A distinguishing feature of SiC material is exactly that homogeneity is many types of, and in all SiC polytypes, the 4H-SiC of the closely packed wurtzite structure of hexagonal obtains high attention rate, because the electron mobility of 4H-SiC structure is approximately more than 2 times of 6H-SiC.Therefore, 4H-SiC material, at high frequency high power device, especially occupies main status in metal-semiconductor field effect transistor (MESFET) application.
At present, most of document is devoted to the research of dual recess 4H-SiCMESFET structure and is improved on the basis of this structure.Dual recess 4H-SiCMESFET structure is from top to bottom: 4H-SiC SI-substrate, P type resilient coating, N-type channel layer and N+ cap layers, form the N-type channel layer of depression after etching N+cap layers, the source half length of grid forms recessed grid structure to N-type channel layer sunken inside.
Compared to traditional structure, although the drain saturation current of dual recess 4H-SiCMESFET structure is improved because of the increase of gate electrode both sides channel thickness, the puncture voltage of device receives very large suppression, declines to some extent on the contrary.This is because device is subject to the restriction of drain saturation current and puncture voltage equilibrium, is ensureing under the condition that device current is larger, then must sacrifice the breakdown characteristics that device is correlated with and exchange larger saturated drain current for.
Summary of the invention
The object of the invention is to provide a kind of 4H-SiC metal-semiconductor field effect transistor and the manufacture method with part sinking raceway groove, not only further increase the drain saturation current of device, and breakdown point drifts near drain electrode from grid, drastically increase the breakdown characteristics of device, the output power density of device improves nearly more than one times than dual recess 4H-SiC structure, the frequency characteristic of device is also greatly improved.
For achieving the above object, the present invention implements according to following technical scheme:
A kind of 4H-SiC metal-semiconductor field effect transistor with part sinking raceway groove, comprise 4H-SiC SI-substrate from bottom to top, P type resilient coating, N-type channel layer, N-type channel layer surface is provided with source electrode cap layers and drain electrode cap layers, source electrode cap layers and drain electrode cap layers surface are respectively equipped with source electrode and drain electrode, above N-type channel layer and near source class cap layers side formed gate electrode, part gate electrode near source class cap layers side is to lower recess, form recessed grid structure, grid leak drift region of caving in is formed between gate electrode and drain electrode cap layers, P resilient coating upper surface forms near between drain electrode cap layers place and recessed grid leak side the grid leak resilient coating that caves in, the cup depth of depression grid leak drift region is identical with the cup depth of depression grid leak resilient coating, channel thickness between grid leak and the channel thickness between grid source are consistent, raceway groove sinks, the grid leak channel region of depression is overall relative to channel region, grid source parallelly to be moved down.
As present invention further optimization scheme, the cup depth of described depression grid leak drift region and the cup depth of depression grid leak resilient coating are 0.1 μm.
There is a preparation method for the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove, comprise the following steps:
1) 4H-SiC SI-substrate is cleaned, to remove surface contaminants;
2) in the SiC layer that 4H-SiC SI-substrate Epitaxial growth 0.5 μm is thick, and through B
2h
6in-situ doped, formed concentration be 1.4 × 10
15cm
-3p type resilient coating;
3) in the SiC layer that P type resilient coating Epitaxial growth 0.25 μm is thick, and through N
2in-situ doped, formed concentration be 3 × 10
17cm
-3n-type channel layer;
4) in the SiC layer that N-type channel layer Epitaxial growth 0.2 μm is thick, and through N
2in-situ doped, formed concentration be 1.0 × 10
20cm
-3n+ type cap layers;
5) in N+ type cap layers, carry out photoetching and isolation injection successively, form isolated area and active area;
6) successively source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out to active area, form source electrode and the drain electrode of 0.5 μm long;
7) carry out photoetching, etching to the N+ type cap layers between source electrode and drain electrode, formation etching depth and length are respectively the chase road of 0.2 μm and 2.2 μm;
8) carry out photoetching and ion implantation to P type resilient coating, formed and have 1.35 μm long, the degree of depth is the depression grid leak resilient coating of 0.1 μm, and the leakage lateral edges of depression grid leak resilient coating is positioned at immediately below drain electrode;
9) carry out electron beam exposure, etching to chase road, form one 1 μm long, the degree of depth is the depression grid leak drift region of 0.1 μm, and the leakage lateral edges of depression grid leak drift region is positioned at immediately below drain electrode;
10) carry out electron beam exposure, etching to chase road, form one 0.35 μm long, distance sources electrode side is 0.5 μm long, and the degree of depth is the groove of 0.05 μm;
11) between the source electrode side of groove and depression grid leak drift region, carry out photoetching, magnetron sputtering and metal-stripping, form the gate electrode of 0.7 μm long, the part gate electrode near source class cap layers side is recessed to form recessed grid structure to N-type channel layer;
12) formed 4H-SiC metal-semiconductor field effect transistor surface is carried out passivation, anti-carved, form electrode pad, complete the making of device.
Compared with prior art, beneficial effect of the present invention:
1. drain saturation current improves
For 4H-SiC metal-semiconductor field effect transistor structure, channel thickness is larger, and drain saturation current is larger.Depression grid leak resilient coating is the same with the cup depth of depression grid leak drift region, and the channel thickness between grid source and the thickness between grid leak are generally consistent.But because the length of sunk area is different, make the channel thickness under non-recessed gate electrode more originally compare and increase, impedance reduces, and drain saturation current is improved.
2. puncture voltage improves
There is the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove compared to dual recess 4H-SiC metal-semiconductor field effect transistor, due to the existence of grid leak drift region of caving in, effectively improve the electric field concentration effect that gate electrode leaks lateral edges, by the modulation of effects on surface Electric Field Distribution, under breakdown conditions, exist except peak value electric field, near drain electrode except gate electrode leaks lateral edges, also there is a peak value electric field, and the peak electric field of drain side is higher than the peak electric field near grid.The breakdown point of device changes, and drift to drain electrode side from original grid side, puncture voltage obviously promotes.So the puncture voltage of new construction is greatly improved.
3. frequency characteristic is improved
For the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove, the existence of depression grid leak drift region, to inhibit under grid depletion region to the extension of grid leak channel region.Simultaneously due to the increase of the channel thickness under non-recessed gate electrode region, the distance of gate electrode and depletion layer lower limb is increased, therefore there is very little grid source electric capacity.Although the mutual conductance of the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove comparatively dual recess structure has and slightly declines, but the fall of grid source electric capacity is greater than the fall of mutual conductance, so it improves by frequency, the maximum oscillation frequency and the maximum available gain that also have device that improve thereupon.
Accompanying drawing explanation
Fig. 1 is cross-sectional view of the present invention;
Fig. 2 is Making programme figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the invention will be further described, is used for explaining the present invention in illustrative examples of this invention and explanation, but not as a limitation of the invention.
Shown in Fig. 1,4H-SiC metal-semiconductor field effect transistor of the present invention, comprising: the 4H-SiC SI-substrate Isosorbide-5-Nitrae H-SiC SI-substrate 1 mixing foreign matter of vanadium is respectively 1.4 × 10 for doping content and thickness
15cm
-33 × 10 are respectively for doping content and thickness with on P type resilient coating 2, the P type resilient coating 2 of 0.5 μm
17cm
-3with the N-type channel layer 3 of 0.25 μm, the both sides of N-type channel layer 3 are respectively the N of 0.5 μm long
+type source electrode cap layers 5 and drain electrode cap layers 6, both doping contents and thickness are 1.0 × 10
20cm
-3with 0.2 μm, source electrode cap layers 5 and drain electrode cap layers 6 surface are source electrode 9 and drain electrode 10 respectively, it is the gate electrode 4 of 0.7 μm long above N-type channel layer 3 and near 0.5 μm of place of source electrode cap layers 5, half gate electrode 4 wherein near source class cap layers 5 side caves in 0.05 μm to N-type channel layer 3, form recessed grid structure, P type resilient coating 2 upper surface immediately below between non-recessed grid and drain electrode cap layers 6, form 1.35 μm long, 0.1 μm of dark depression grid leak resilient coating 7, between gate electrode 4 and drain electrode cap layers 6, form 1 μm long, 0.1 μm of dark depression grid leak drift region 8, channel layer thickness between grid leak and the channel layer thickness between grid source are consistent, raceway groove sinks, the grid leak channel region of depression is overall relative to channel region, grid source parallelly to be moved down.
With reference to the method for Fig. 2, this making 4H-SiC metal-semiconductor field effect transistor, provide following three kinds of embodiments.
Embodiment 1
Making depression grid leak buffer layer thickness and recessed gate drain-gate leak the 4H-SiC metal-semiconductor field effect transistor that drift region thickness is 0.1 μm.
The making step of the present embodiment is as follows:
Step 1: cleaning 4H-SiC SI-substrate 1, to remove surface contaminant.
(1.1) with the cotton balls being moistened with methyl alcohol, substrate is carefully cleaned twice, to remove the SiC particle of surperficial various sizes;
(1.2) by substrate at H
2sO
4: HNO
3in=1:1 ultrasonic 5 minutes;
(1.3) by substrate at 1# cleaning fluid (NaOH:H
2o
2: H
2o=1:2:5) boil 5 minutes in, deionized water rinsing puts into 2# cleaning fluid (HCl:H again after 5 minutes
2o
2: H
2o=1:2:7) 5 minutes are boiled in.Finally clean with deionized water rinsing and use N
2dry up for subsequent use.
Step 2: in 4H-SiC SI-substrate 1 epitaxial growth SiC layer on the surface, through diborane B
2h
6in-situ doped formation P type resilient coating 2.
4H-SiC SI-substrate 1 is put into growth room, in growth room, passes into silane, the propane of 10ml/min, the high-purity hydrogen of 80l/min that flow is 20ml/min, pass into the B of 2ml/min simultaneously
2h
6(H
2in be diluted to 5%), growth temperature is 1550 DEG C, and pressure is 10
5pa, continues 6min, and making doping content and thickness are respectively 1.4 × 10
15cm
-3with the P type resilient coating 2 of 0.5 μm;
Step 3: in P type resilient coating 2 Epitaxial growth SiC layer, through N
2in-situ doped formation N-type channel layer 3.
4H-SiC sample is put into growth room, in growth room, passes into the N of silane, the propane of 10ml/min, the high-purity hydrogen of 80l/min and the 2ml/min that flow is 20ml/min
2, growth temperature is 1550 DEG C, and pressure is 10
5pa, continues 3min, and making doping content and thickness are respectively 3 × 10
17cm
-3with the N-type channel layer 3 of 0.25 μm;
Step 4: in N-type channel layer 3 Epitaxial growth SiC layer, through N
2in-situ doped formation N
+cap layers.
4H-SiC sample is put into growth room, in growth room, passes into the N of silane, the propane of 10ml/min, the high-purity hydrogen of 80l/min and the 20ml/min that flow is 20ml/min
2, growth temperature is 1550 DEG C, and pressure is 10
5pa, continues 2min, makes 0.5 μm long, doping content 1.0 × 10
20cm
-3, thickness is the N of 0.2 μm
+cap layers;
Step 5: utilize table top photoetching to protect N
+the active area of cap layers, carries out isolation to the region beyond active area and injects.
(5.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm is to ensure can play good barrier effect when follow-up isolation is injected;
(5.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, adopt isolation to inject photolithography plate and carry out after about 35 seconds uv-exposures at special developer solution ((CH
3)
4nOH:H
2o=1:3) in, development 60 seconds, exposes 4H-SiC, dries 3 minutes after then in 100 DEG C of baking ovens;
(5.3) carry out twice boron ion implantation, injection condition is 130keV/6 × 10
12cm
-2, 50keV/2 × 10
12cm
-2.With acetone and ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes, the isolation completed beyond active area is injected.
(5.4) above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min.
Step 6: at N
+cap layers is formed source electrode 9 and drain electrode 10.
(6.1) masking glue adopts PMMA+AZ1400 double-layer glue, requires the thick > of glue 1.2 μm.First be coated with PMMA glue after sample treatment is clean, speed is 4000R/min, thick about 0.5 μm of glue, and then front baking 120 seconds in 200 DEG C of baking ovens, is coated with about 0.8 μm, AZ1400 glue again after taking-up;
(6.2) front baking 90 seconds in 90 DEG C of baking ovens, adopts source and drain photolithography plate to carry out after exposure in 15 seconds with special developer solution ((CH
3)
4nOH:H
2o=1:4) development removes AZ1400 glue in 50 seconds, then carries out uv-exposure to PMMA glue, then develops 3 minutes with toluene, dries 3 minutes after then in 100 DEG C of baking ovens, completes source-drain area metallization window;
(6.3) adopt multi-target magnetic control sputtering platform, room temperature sputters Ni (150nm)/Ti (150nm)/Au (300nm) multiple layer metal as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10
-3pa, Ar flow 40sccm;
(6.4) after having sputtered, sample is put into 150 DEG C of special strippers of Buty, move in 130 DEG C of Buty strippers after metal comes off again, when equitemperature drops to below 80 DEG C, then sample is moved in acetone, finally take out sample and dry up with nitrogen.
(6.5) sample is put into rapid alloying stove, at nitrogen nitrogen atmosphere (N
2: H
2=9:1) be rapidly heated (970/1min) to alloy temperature under protection, carry out 10 minutes, form source electrode 9 and drain electrode 10.
Step 7: at N
+in cap layers, etching forms chase road.
(7.1) adopt application rate: 3000R/min, the positive photoresist of the thick > of glue 2 μm carries out photoetching to sample, plays etching masking action during to ensure subsequent etching;
(7.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, adopt mask blank to carry out after about 35 seconds uv-exposures at special developer solution ((CH
3)
4nOH:H
2o=1:3) in, development 60 seconds, dries 3 minutes after then in 100 DEG C of baking ovens;
(7.3) adopt ICP sense coupling system to carry out N+ etching, etching condition is etching power 250W, bias power 60W, operating pressure 9Pa, and etching gas selects CF
4(32sccm)+Ar (8sccm), forming length after etching is 2.2 μm, and the degree of depth is the chase road of 0.2 μm, etches rear acetone+ultrasonic removal etching and shelters glue.
Step 8: to resilient coating 2 photoetching of P type and ion implantation, forms depression grid leak resilient coating 7.
(8.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
(8.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting ladder disign layer photoetching plate to carry out about 35 seconds uv-exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(8.3) carry out N~+ implantation, injection condition is 260keV/2 × 10
12cm
-2, temperature is 400 DEG C.With acetone+ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes, forming depression thickness is 0.1 μm, and depression length is the depression grid leak resilient coating 7 of 1.35 μm, and the leakage lateral edges of the grid leak resilient coating 7 that wherein caves in is positioned at immediately below drain electrode 10;
(8.4) above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of depression grid leak resilient coating 7.
Step 9: to N-type channel layer 3 photoetching, etching, forms depression grid leak drift region 8.
(9.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
(9.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting recessed gate source grid leak photolithography plate to carry out about 35 seconds electron beam exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(9.3) etching adopts ICP sense coupling system, and etching condition is etching power 250W, bias power 60W, operating pressure 9Pa, and etching gas selects CF
4(32sccm)+Ar (8sccm), forming length after etching is 1 μm, the degree of depth is the depression grid leak drift region of 0.1 μm, wherein the leakage lateral edges of depression grid leak drift region 8 is positioned at immediately below drain electrode 10, shelter glue with by acetone+ultrasonic removal etching, complete the making of depression grid leak drift region 8 after etching.
Step 10: photoetching, etching, forms recessed gate electrode region.
(10.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
(10.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting recessed gate electrode region photolithography plate to carry out about 35 seconds electron beam exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(10.3) etching adopts ICP sense coupling system, and etching condition is etching power 250W, bias power 60W, operating pressure 9Pa, and etching gas selects CF
4(32sccm)+Ar (8sccm), forming distance sources electrode 9 side after etching is 0.5 μm, and length is 0.35 μm, and the degree of depth is the recessed gate electrode region of 0.05 μm, shelters glue after etching with by acetone+ultrasonic removal etching.
Step 11: photoetching, magnetron sputtering and metal-stripping, forms the gate electrode 4 of 0.7 μm long.
(11.1) masking glue adopts PMMA+AZ1400 double-layer glue, requires the thick > of glue 1.2 μm.First be coated with PMMA glue after slice, thin piece process is clean, speed is 4000R/min, thick about 0.5 μm of glue, and then front baking 120 seconds in 200 DEG C of baking ovens, is coated with about 0.8 μm, AZ1400 glue again after taking-up;
(11.2) front baking 90 seconds in 90 DEG C of baking ovens, develop with special developer solution (tetramethyl aqua ammonia: water=1:4) after adopting grid photolithography plate to carry out 15 seconds uv-exposures and remove AZ1400 glue in 50 seconds, then general exposure is carried out to PMMA glue, develop 3 minutes with toluene again, dry 3 minutes after then in 100 DEG C of baking ovens;
(11.3) adopt multi-target magnetic control sputtering platform, room temperature sputters Ni (150nm)/Ti (150nm)/Au (300nm) multiple layer metal as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10
-3pa, Ar flow 40sccm, is heated to 150 DEG C by slice, thin piece in sputter procedure;
(11.4) after having sputtered, slice, thin piece is put into 150 DEG C of special strippers of Buty, move in 130 DEG C of Buty strippers after metal comes off again, when equitemperature drops to below 80 DEG C, again slice, thin piece is moved in acetone, finally take out slice, thin piece and slowly dry up (preventing metal gate to be touched down) with low discharge nitrogen.Finally use the removing of photoresist by plasma 3 minutes, complete the making of gate electrode 4.
Step 12: the 4H-SiC metal-semiconductor field effect transistor surface of above-mentioned formation is carried out to passivation, anti-carved, forms electrode pad.
(12.1) at 300 DEG C, in reative cell, pass into the SiH that flow is 300sccm simultaneously
4, 323sccm NH
3with the N of 330sccm
2, by plasma enhanced CVD technique, at the Si that surface deposition 0.5 μm is thick
3n
4layer is as passivation dielectric layer;
(12.2) passivation photoetching adopts positive photoresist, application rate 3000R/mins, require the thick > of glue 2 μm, after gluing completes in 90 DEG C of baking ovens front baking 90 seconds, then adopt and anti-carve photolithography plate and carry out 35 seconds uv-exposures, develop 60 seconds with special developer solution (tetramethyl aqua ammonia: water=1:3), dry 3 minutes after finally in 100 DEG C of baking ovens;
(12.3) Si
3n
4etching adopts RIE technique, and etching gas selects CHF
3(50sccm)+Ar (5sccm), carries out 3 minutes removing of photoresist by plasmas after completing again.Expose metal, form source, leakage and gate electrode pressure welding point, complete the making of whole device.
Embodiment 2
Making depression grid leak buffer layer thickness and recessed gate drain-gate leak the 4H-SiC metal-semiconductor field effect transistor that drift region thickness is 0.08 μm.
Step 8: to resilient coating 2 photoetching of P type and ion implantation, forms depression grid leak resilient coating 7.
(8.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
(8.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting ladder disign layer photoetching plate to carry out about 35 seconds uv-exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(8.3) carry out N~+ implantation, injection condition is 240keV/2 × 10
12cm
-2, temperature is 400 DEG C.With acetone+ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes, forming depression thickness is 0.08 μm, and depression length is the depression grid leak resilient coating 7 of 1.35 μm, and the leakage lateral edges of the grid leak resilient coating 7 that wherein caves in is positioned at immediately below drain electrode 10;
(8.4) above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of depression grid leak resilient coating 7.
Step 9: to N-type channel layer 3 photoetching, etching, forms depression grid leak drift region 8.
(9.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
(9.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting recessed gate source grid leak photolithography plate to carry out about 35 seconds electron beam exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(9.3) etching adopts ICP sense coupling system, and etching condition is etching power 250W, bias power 60W, operating pressure 9Pa, and etching gas selects CF
4(32sccm)+Ar (8sccm), forming length after etching is 1 μm, the degree of depth is the depression grid leak drift region of 0.08 μm, wherein the leakage lateral edges of depression grid leak drift region 8 is positioned at immediately below drain electrode 10, shelter glue with by acetone+ultrasonic removal etching, complete the making of depression grid leak drift region 8 after etching.
All the other steps are with embodiment 1.
Embodiment 3
Making depression grid leak buffer layer thickness and recessed gate drain-gate leak the 4H-SiC metal-semiconductor field effect transistor that drift region thickness is 0.11 μm.
Step 8: to resilient coating 2 photoetching of P type and ion implantation, forms depression grid leak resilient coating 7.
(8.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures can play good barrier effect when follow-up isolation is injected;
(8.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting ladder disign layer photoetching plate to carry out about 35 seconds uv-exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(8.3) carry out N~+ implantation, injection condition is 270keV/2 × 10
12cm
-2, temperature is 400 DEG C.With acetone+ultrasonic depolymerization after injection completes, then use the removing of photoresist by plasma 3 minutes, forming depression thickness is 0.11 μm, and depression length is the depression grid leak resilient coating 7 of 1.35 μm, and the leakage lateral edges of the grid leak resilient coating 7 that wherein caves in is positioned at immediately below drain electrode 10;
(8.4) above-mentioned 4H-SiC epitaxial wafer is placed in 1600 DEG C of induction heating furnace annealings, 10 minutes activator impurities, Ar throughput is 20ml/min, completes the making of depression grid leak resilient coating 7.
Step 9: to N-type channel layer 3 photoetching, etching, forms depression grid leak drift region 8.
(9.1) adopt positive photoresist, application rate: 3000R/min, the thick > of glue 2 μm ensures the etching masking action of the glue when subsequent etching;
(9.2) gluing complete after in 90 DEG C of baking ovens front baking 90 seconds, develop 60 seconds in special developer solution (tetramethyl aqua ammonia: water=1:3) after adopting recessed gate source grid leak photolithography plate to carry out about 35 seconds electron beam exposures, dry 3 minutes after then in 100 DEG C of baking ovens;
(9.3) etching adopts ICP sense coupling system, and etching condition is etching power 250W, bias power 60W, operating pressure 9Pa, and etching gas selects CF
4(32sccm)+Ar (8sccm), forming length after etching is 1 μm, the degree of depth is the depression grid leak drift region of 0.11 μm, wherein the leakage lateral edges of depression grid leak drift region 8 is positioned at immediately below drain electrode 10, shelter glue with by acetone+ultrasonic removal etching, complete the making of depression grid leak drift region 8 after etching.
All the other steps are with embodiment 1.
Summary, the 4H-SiC metal-semiconductor field effect transistor tool that the present invention makes has the following advantages:
1. drain saturation current improves
For 4H-SiC metal-semiconductor field effect transistor structure, channel thickness is larger, and drain saturation current is larger.Depression grid leak resilient coating is the same with the cup depth of depression grid leak drift region, and the channel thickness between grid source and the thickness between grid leak are generally consistent.But because the length of sunk area is different, make the channel thickness under non-recessed gate electrode more originally compare and increase, impedance reduces, and drain saturation current is improved.
2. puncture voltage improves
There is the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove compared to dual recess 4H-SiC metal-semiconductor field effect transistor, due to the existence of grid leak drift region of caving in, effectively improve the electric field concentration effect that gate electrode leaks lateral edges, by the modulation of effects on surface Electric Field Distribution, under breakdown conditions, exist except peak value electric field, near drain electrode except gate electrode leaks lateral edges, also there is a peak value electric field, and the peak electric field of drain side is higher than the peak electric field near grid.The breakdown point of device changes, and drift to drain electrode side from original grid side, puncture voltage obviously promotes.So the puncture voltage of new construction is greatly improved.
3. frequency characteristic is improved
For the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove, the existence of depression grid leak drift region, to inhibit under grid depletion region to the extension of grid leak channel region.Simultaneously due to the increase of the channel thickness under non-recessed gate electrode region, the distance of gate electrode and depletion layer lower limb is increased, therefore there is very little grid source electric capacity.Although the mutual conductance of the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove comparatively dual recess structure has and slightly declines, but the fall of grid source electric capacity is greater than the fall of mutual conductance, so it improves by frequency, the maximum oscillation frequency and the maximum available gain that also have device that improve thereupon.
Claims (3)
1. one kind has the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove, comprise 4H-SiC SI-substrate (1) from bottom to top, P type resilient coating (2), N-type channel layer (3), N-type channel layer (3) surperficial both sides are respectively equipped with source electrode cap layers (5) and drain electrode cap layers (6), source electrode cap layers (5) and drain electrode cap layers (6) surface are respectively equipped with source electrode (9) and drain electrode (10), above N-type channel layer (3) and side formation gate electrode (4) of close source electrode cap layers (5), it is characterized in that: the part gate electrode (4) near source class cap layers (5) side is recessed to form recessed grid structure to N-type channel layer (3), grid leak drift region (8) of caving in is formed between gate electrode (4) and drain electrode cap layers (6), P resilient coating (2) upper surface forms near between drain electrode cap layers (6) place and the recessed grid leak side of gate electrode (4) the grid leak resilient coating (7) that caves in, the cup depth of described depression grid leak drift region (8) is identical with the cup depth of depression grid leak resilient coating (7).
2. the 4H-SiC metal-semiconductor field effect transistor with part sinking raceway groove according to claim 1, is characterized in that: the cup depth of depression grid leak drift region (8) is 0.1 μm with the cup depth of depression grid leak resilient coating (7).
3. there is a preparation method for the 4H-SiC metal-semiconductor field effect transistor of part sinking raceway groove as claimed in claim 1, comprise the following steps:
1) 4H-SiC SI-substrate (1) is cleaned, to remove surface contaminants;
2) in the SiC layer that 4H-SiC SI-substrate (1) Epitaxial growth 0.5 μm is thick, and through B
2h
6in-situ doped, formed concentration be 1.4 × 10
15cm
-3p type resilient coating (2);
3) in the SiC layer that P type resilient coating (2) Epitaxial growth 0.25 μm is thick, and through N
2in-situ doped, formed concentration be 3 × 10
17cm
-3n-type channel layer (3);
4) in the SiC layer that N-type channel layer (3) Epitaxial growth 0.2 μm is thick, and through N
2in-situ doped, formed concentration be 1.0 × 10
20cm
-3n+ type cap layers;
5) at N
+type cap layers is carried out successively photoetching and isolation injection, form isolated area and active area;
6) successively source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out to active area, form source electrode (9) and the drain electrode (10) of 0.5 μm long;
7) carry out photoetching, etching to the N+ type cap layers between source electrode (9) and drain electrode (10), formation etching depth and length are respectively the chase road of 0.2 μm and 2.2 μm;
8) photoetching and ion implantation are carried out to P type resilient coating (2), formed and there are 1.35 μm long, the degree of depth is the depression grid leak resilient coating (7) of 0.1 μm, and the edge, side of depression grid leak resilient coating (7) is positioned at immediately below drain electrode (10);
9) electron beam exposure, etching are carried out to chase road, form one 1 μm long, the degree of depth is the depression grid leak drift region (8) of 0.1 μm, and the edge, side of depression grid leak drift region (8) is positioned at immediately below drain electrode (10);
10) carry out electron beam exposure, etching to chase road, form one 0.35 μm long, distance sources electrode (9) side is 0.5 μm long, and the degree of depth is the groove of 0.05 μm;
11) between source electrode (9) side of groove and depression grid leak drift region (8), photoetching, magnetron sputtering and metal-stripping is carried out, form the gate electrode (4) of 0.7 μm long, the part gate electrode (4) near source class cap layers (5) side is recessed to form recessed grid structure to N-type channel layer (3);
12) formed 4H-SiC metal-semiconductor field effect transistor surface is carried out passivation, anti-carved, form electrode pad, complete the making of device.
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| CN112436051A (en) * | 2020-11-03 | 2021-03-02 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with symmetrical stepped oxygen buried layer |
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| JP2001068481A (en) * | 1999-08-25 | 2001-03-16 | Sanken Electric Co Ltd | Field-effect semiconductor device |
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| JP2001068481A (en) * | 1999-08-25 | 2001-03-16 | Sanken Electric Co Ltd | Field-effect semiconductor device |
| US20040164374A1 (en) * | 2003-02-20 | 2004-08-26 | Nec Compound Semiconductor Devices, Ltd. | Field effect transistor and method of manufacturing the same |
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| CN112436051A (en) * | 2020-11-03 | 2021-03-02 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with symmetrical stepped oxygen buried layer |
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