CN104282764B - 4H SiC metal-semiconductor field effect transistors and preparation method with domatic grid - Google Patents
4H SiC metal-semiconductor field effect transistors and preparation method with domatic grid Download PDFInfo
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- CN104282764B CN104282764B CN201410587502.9A CN201410587502A CN104282764B CN 104282764 B CN104282764 B CN 104282764B CN 201410587502 A CN201410587502 A CN 201410587502A CN 104282764 B CN104282764 B CN 104282764B
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- 230000005669 field effect Effects 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims description 6
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims abstract description 21
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims description 29
- 238000001259 photo etching Methods 0.000 claims description 14
- 238000010894 electron beam technology Methods 0.000 claims description 12
- 108091006146 Channels Proteins 0.000 claims description 7
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000356 contaminant Substances 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 30
- 239000002184 metal Substances 0.000 description 30
- 239000003292 glue Substances 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 14
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 12
- 229910001868 water Inorganic materials 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 239000000243 solution Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 6
- 238000004026 adhesive bonding Methods 0.000 description 6
- 210000002381 plasma Anatomy 0.000 description 6
- 239000010931 gold Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 229910052774 Proactinium Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 3
- 239000004926 polymethyl methacrylate Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000001294 propane Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000002604 ultrasonography Methods 0.000 description 2
- 235000009161 Espostoa lanata Nutrition 0.000 description 1
- 240000001624 Espostoa lanata Species 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- XKMRRTOUMJRJIA-UHFFFAOYSA-N ammonia nh3 Chemical compound N.N XKMRRTOUMJRJIA-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a kind of 4H SiC metal-semiconductor field effect transistors with domatic grid, it includes 4H SiC SI-substrates from bottom to top, p-type cushion, N-type channel layer, N-type channel layer surface is provided with source electrode cap layers and drain electrode cap layers, source electrode cap layers and drain electrode cap layers surface are respectively equipped with source electrode and drain electrode, the upper surface of the N-type channel layer is set to the inclined domatic groove in source electrode cap layers side, domatic grid is provided with domatic groove, the lower surface of domatic grid is engaged with domatic groove, the upper surface of domatic grid is parallel with the upper surface of N-type channel layer, distance is less than domatic grid and the distance between the cap layers that drain between the domatic grid and source electrode cap layers.The field-effect transistor of the present invention has the characteristics of drain electrode output current is big, frequency characteristic is excellent.
Description
Technical field
The present invention relates to field-effect transistor, particularly a kind of 4H-SiC metal-semiconductor field effects with domatic grid
Transistor and preparation method.
Background technology
Material and electrology characteristic that SiC is protruded due to it, e.g., big energy gap, high saturated electrons migration velocity, height
Breakdown electric field, high heat conductance etc., make it in high frequency high power device application, especially high temperature, high pressure, space flight, satellite etc. are tight
There are very big potentiality in high frequency high power device application under severe environment.SiC is partly led in microwave power device, especially metal
Occupy main status in the application of body field-effect transistor (MESFET).
Traditional 4H-SiC MESFET structure is from top to bottom：4H-SiC SI-substrates, p-type cushion, N-type ditch
The N-type channel layer of depression is formed after channel layer and N+ cap layers, etching N+ cap layers.Breakdown voltage is to weigh 4H-SiC MESFET devices
The important indicator of performance.At present, the improvement that the breakdown voltage for 4H-SiC MESFET devices is carried out is mainly in traditional 4H-
SiC MESFET geometrically, structure improvement are carried out to grid, raceway groove, drift region etc..However, to traditional 4H-SiC
Lifting of the improvement of MESFET geometries to device electric breakdown strength is limited, and this is due to ensure that device current is larger
Under the conditions of, the lifting of 4H-SiC MESEFT breakdown voltages is limited in a balanced way by drain saturation current and breakdown voltage：Big saturation
Current density requires that raceway groove is thicker, and doping concentration is bigger, but the raising of doping concentration and thickness can reduce the breakdown potential of device
Pressure.
The content of the invention
The invention aims to provide a kind of 4H-SiC metal-semiconductor field effect transistors with domatic grid and
Preparation method, can improve the frequency characteristic of effect transistor, so as to improve effect transistor performance.
To reach above-mentioned purpose, the present invention is implemented according to following technical scheme：
A kind of 4H-SiC metal-semiconductor field effect transistors with domatic grid, it is exhausted including 4H-SiC half from bottom to top
Edge substrate, p-type cushion, N-type channel layer, N-type channel layer surface is provided with source electrode cap layers and drain cap layers, source electrode cap layers and drain electrode
Cap layers surface is respectively equipped with source electrode and drain electrode, and the upper surface of the N-type channel layer sets inclined to source electrode cap layers side
Domatic groove, domatic grid is provided with domatic groove, and the lower surface of domatic grid is engaged with domatic groove, the upper surface of domatic grid and
N-type channel layer upper surface it is parallel, between the domatic grid and source electrode cap layers distance be less than domatic grid with drain electrode cap layers it
Between distance.
As present invention further optimization scheme, the length of the domatic grid is 0.7 μm,
As present invention further optimization scheme, the beeline between the domatic grid and source electrode cap layers is 0.5 μ
m。
A kind of preparation method of the 4H-SiC metal-semiconductor field effect transistors with domatic grid, including following step
Suddenly：
1) 4H-SiC SI-substrates are cleaned, to remove surface contaminants；
2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates Epitaxial growth 0.5, and through B2H6Doping in situ, formed dense
Spend for 1.4 × 1015cm-3P-type cushion；
3) in the SiC layer of the μ m-thick of p-type cushion Epitaxial growth 0.25, and through N2Doping in situ, is formed concentration be 3 ×
1017cm-3N-type channel layer；
4) in the SiC layer of the N-type channel layer μ m-thick of Epitaxial growth 0.2, and through N2Doping in situ, it is 1.0 to form concentration
×1020cm-3N+Type cap layers；
5) in N+Photoetching is carried out in type cap layers successively and isolation is injected, isolated area and active area is formed；
6) source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out successively to active area, forms 0.5 μm long
Source electrode and drain electrode；
7) to the N between source electrode and drain electrode+Type cap layers carry out photoetching, etching again, form etching depth and length point
Chase road that Wei be 0.2 μm and 2.2 μm；
8) electron beam exposure, etching are carried out to chase road, forms one 0.7 μm long, is 0.5 μm, depth away from source electrode side
For 0.01 μm of groove, and it is 0.6 μm, 0.5 μm ... according to length successively and is successively decreased, 7 electron beam exposures, quarters is carried out altogether
Erosion, forms a domatic groove；
9) photoetching, magnetron sputtering and metal-stripping are carried out successively to domatic groove, domatic grid 0.7 μm long is formed；
10) the 4H-SiC metal-semiconductor field effect transistors surface formed is passivated, anti-carved, form electrode pressure
Solder joint, completes the making of device.
Compared with prior art, beneficial effects of the present invention：
1. drain current is improved
For 4H-SiC metal-semiconductor field effect transistor structures, the size for the depletion region that its metallic perimeter is produced
It is relevant with the size of the area of semiconductor contact with metal.Metal and the area of semiconductor contact be bigger, and metallic perimeter exhausts
Area's area can also increase therewith.For common 4H-SiC metal-semiconductor field effect transistors, its metal contact area is only limitted to
Contact area below grid.And the 4H-SiC metal-semiconductor field effect transistors with domatic grid, metal contact is on slope
Shape grid part, smaller close to leakage side gate area, depletion region is moved to the direction close to grid, so that depletion region area is more
Small, channel resistance reduces so that drain current is improved.
2. frequency characteristic improves
Relative to the 4H-SiC metal-semiconductor field effect transistors of traditional structure, the 4H-SiC metals with domatic grid
Semiconductor field effect transistor is smaller due to the distance of its metal and depletion region, therefore the 4H-SiC metals with domatic grid half
Conductor field-effect transistor has higher gate-source capacitance, but the 4H-SiC metal-semiconductor field effects with domatic grid are brilliant
The lifting amplitude of the mutual conductance of body pipe is but significantly larger than the 4H-SiC metal-semiconductor field effect transistors of traditional structure.So its section
Only frequency is improved, and that improves therewith also has the maximum oscillation frequency and maximum available gain of device.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the present invention；
Fig. 2 is the Making programme figure of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment the invention will be further described, the illustrative examples invented herein
And explanation is used for explaining the present invention, but it is not as a limitation of the invention.
As shown in figure 1, the 4H-SiC metal-semiconductor field effect transistors of the present invention, including：Mix the 4H-SiC of foreign matter of vanadium
For doping concentration and thickness it is respectively 1.4 × 10 on SI-substrate Isosorbide-5-Nitrae H-SiC SI-substrates 115cm-3With 0.5 μm of p-type
For doping concentration and thickness it is respectively 3 × 10 on cushion 2, p-type cushion 217cm-3With 0.25 μm of N-type channel layer 3, N-type
The both sides of channel layer 3 are respectively 0.5 μm of long N+Type source electrode cap layers 5 and drain electrode cap layers 6, both doping concentrations and thickness are
1.0×1020cm-3With 0.2 μm, source electrode cap layers 5 and drain electrode cap layers 6 surface are source electrode 7 and drain electrode 8, N-type channel layer 3 respectively
Upper surface set to the inclined domatic groove 9 in the side of source electrode cap layers 5, be provided with domatic groove 9 under domatic grid 4, domatic grid 4
End face is engaged with domatic groove 9, and the upper surface of domatic grid 4 is parallel with the upper surface of N-type channel layer 3, N-type channel layer 3 it is upper
It is 0.7 μm long at 0.5 μm of side and distance sources polar caps layer 5 and there is the domatic grid 4 that thickness is 0.07 μm close to source.
Reference picture 2, the method for this making 4H-SiC metal-semiconductor field effect transistors provides following three kinds of embodiments.
Embodiment 1
Making has 0.07 μm of depth, 4H-SiC metal-semiconductor field effect transistors of domatic grid 0.7 μm long.
The making step of the present embodiment is as follows：
Step 1：4H-SiC SI-substrates 1 are cleaned, to remove surface contaminant.
(1.1) substrate is carefully cleaned twice with the cotton balls for being moistened with methanol, to remove the SiC particulate of surface various sizes；
(1.2) by substrate in H2SO4:HNO3=1:Ultrasound 5 minutes in 1；
(1.3) by substrate in 1# cleaning fluids (NaOH:H2O2:H2O=1:2:5) boiled in 5 minutes, 5 points of deionized water rinsing
2# cleaning fluids (HCl is placed into after clock:H2O2:H2O=1:2:7) boiled in 5 minutes.Finally rinsed well and be used in combination with deionized water
N2Drying is standby.
Step 2：In the surface Epitaxial growth SiC layer of 4H-SiC SI-substrates 1, through diborane B2H6Original position doping forms P
Type cushion 2.
4H-SiC SI-substrates 1 are put into growth room, be passed through into growth room flow be 20ml/min silane,
10ml/min propane, 80l/min high-purity hydrogen, while being passed through 2ml/min B2H6(H2In be diluted to 5%), growth temperature
For 1550 DEG C, pressure is 105Pa, continues 6min, and it is respectively 1.4 × 10 to make doping concentration and thickness15cm-3With 0.5 μm of p-type
Cushion 2；
Step 3：In the Epitaxial growth SiC layer of p-type cushion 2, through N2Original position doping forms N-type channel layer 3.
4H-SiC samples are put into growth room, it is 20ml/min silane, 10ml/min that flow is passed through into growth room
The N of propane, 80l/min high-purity hydrogen and 2ml/min2, growth temperature is 1550 DEG C, and pressure is 105Pa, continues 3min, makes
Doping concentration and thickness are respectively 3.0 × 1017cm-3With 0.25 μm of N-type channel layer 3；
Step 4：In N-type channel 3 Epitaxial growth SiC layer of layer, through N2Original position doping forms N+Cap layers.
4H-SiC samples are put into growth room, it is 20ml/min silane, 10ml/min that flow is passed through into growth room
The N of propane, 80l/min high-purity hydrogen and 20ml/min2, growth temperature is 1550 DEG C, and pressure is 105Pa, continues 2min, system
Make 0.5 μm long, doping concentration 1.0 × 1020cm-3, thickness be 0.2 μm of N+Cap layers；
Step 5：N is protected using table top photoetching+The active area of cap layers, isolation injection is carried out to the region beyond active area.
(5.1) positive photoresist, application rate are used：2 μm of 3000R/min, glue thickness ＞ are to ensure to inject in follow-up isolation
When can play good barrier effect；
(5.2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using isolation injection photolithography plate carry out about 35 seconds it is ultraviolet
In special developer solution ((CH after exposure3)4NOH:H2O=1:3) development 60 seconds, expose 4H-SiC, then in 100 DEG C of baking ovens in
Dry 3 minutes afterwards；
(5.3) carry out boron ion twice to inject, injection condition is 130keV/6 × 1012cm-2, 50keV/2 × 1012cm-2。
Acetone and ultrasonic depolymerization are used after the completion of injection, then with the removing of photoresist by plasma 3 minutes, completes the isolation injection beyond active area.
(5.4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar air-flows
Measure as 20ml/min.
Step 6：In N+Source electrode 7 and drain electrode 8 are formed in cap layers.
(6.1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to 1.2 μm of glue thickness ＞.After sample treatment is clean first
PMMA glue is applied, speed is 4000R/min, and glue is thick about 0.5 μm, and then front baking 120 seconds in 200 DEG C of baking ovens, are applied again after taking-up
About 0.8 μm of AZ1400 glue；
(6.2) front baking 90 seconds in 90 DEG C of baking ovens, special developer solution is used after carrying out exposure in 15 seconds using source and drain photolithography plate
((CH3)4NOH:H2O=1:4) development removes AZ1400 glue in 50 seconds, and uv-exposure, again with toluene development are then carried out to PMMA glue
It is 3 minutes, then rear in 100 DEG C of baking ovens to dry 3 minutes, complete source-drain area metallization window；
(6.3) multi-target magnetic control sputtering platform, room temperature sputtering Ni (150nm)/Ti (150nm)/Au (300nm) multiple layer metal are used
It is used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Pa, Ar flow 40sccm；
(6.4) sample is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 are moved into again after metal comes off
In DEG C Buty strippers, when equitemperature drops to less than 80 DEG C, then sample moved into acetone, finally take out sample and blown with nitrogen
It is dry.
(6.5) sample is put into rapid alloying stove, in nitrogen nitrogen atmosphere (N2:H2=9:1) (970/ is rapidly heated under protecting
Alloy temperature 1min) is arrived, is carried out 10 minutes, source electrode 7 and drain electrode 8 is formed.
Step 7：In N+Chase road is formed in cap layers.
(7.1) application rate is used：3000R/min, 2 μm of glue thickness ＞ positive photoresist carry out photoetching to sample, to protect
Etching masking action is played during card subsequent etching；
(7.2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using mask blank carry out about 35 seconds uv-exposures
Afterwards in special developer solution ((CH3)4NOH:H2O=1:3) development 60 seconds in, it is then rear in 100 DEG C of baking ovens to dry 3 minutes；
(7.3) N+ etchings are carried out using ICP sense couplings system, etching condition is etching power
250W, bias power 60W, operating pressure 9Pa, etching gas selection CF4Length is formed after (32sccm)+Ar (8sccm), etching
For 2.2 μm, depth is to shelter glue with acetone+ultrasound removal etching after 0.2 μm of chase road, etching.
Step 8：Domatic groove 9 is formed on chase road between source electrode 7 and drain electrode 8.
(8.1) in application rate：Under conditions of 3000R/min, 2 μm of glue thickness ＞, photoetching is carried out using positive photoresist, pressed
Reticle is made according to the position of domatic grid, electron beam exposure is used；
(8.2) in special developer solution ((CH3)4NOH:H2O=1:4) in, raceway groove is developed, by figure in reticle
On the chase road for being transferred to source electrode 7 and drain electrode 8, gate figure window is formed, recycles reactive ion etching process etching recessed
Raceway groove, at the same obtain 0.7 μm of length, 0.5 μm away from source, depth is 0.01 μm of groove, and according to length be successively 0.6 μm,
0.5 μm ... is successively decreased, and each etching depth is 0.01mm, and 7 electron beam exposures, etchings are carried out altogether, a domatic is formed
Groove 9.
Step 9：Domatic grid 4 is formed on chase road.
(9.1) photoresist is coated on chase road, reticle is made according to the position in grid region；
(9.2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out about 35 seconds electron beam exposures after in special development
Liquid ((CH3)4NOH:H2O=1:4) in, grid region is developed, it is then rear in 100 DEG C of baking ovens to dry 3 minutes, by reticle
Pattern transfer on the chase road between source region and drain region, form grid region graphical window；
(9.3) multi-target magnetic control sputtering platform, room temperature sputtering Ni (150nm)/Ti (150nm)/Au (300nm) multiple layer metal are used
It is used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Slice, thin piece is heated in Pa, Ar flow 40sccm, sputter procedure
To 150 DEG C；
(9.4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 are moved into again after metal comes off
In DEG C Buty strippers, when equitemperature drops to less than 80 DEG C, then slice, thin piece moved into acetone, finally take out slice, thin piece and use low discharge
Nitrogen slowly dries up and (prevents metal gate to be touched down).Finally use the removing of photoresist by plasma 3 minutes, form the domatic grid that length is 0.7 μm
Pole 4.
Step 10：The 4H-SiC metal-semiconductor field effect transistors surface of above-mentioned formation is passivated, anti-carved, is formed
Electrode pad.
(10.1) at 300 DEG C, it is passed through the SiH that flow is 300sccm simultaneously into reative cell4, 323sccm NH3With
330sccm N2, by plasma (enhancing) chemical vapor deposition method, in the Si of the μ m-thick of surface deposition 0.53N4Layer conduct
Passivation dielectric layer；
(10.2) passivation photoetching uses positive photoresist, application rate 3000R/mins, it is desirable to which 2 μm of glue thickness ＞, gluing is complete
After in 90 DEG C of baking ovens front baking 90 seconds, then using mask blank carry out 35 seconds uv-exposures, use special developer solution
((CH3)4NOH:H2O=1:3) develop 60 seconds, finally post bake 3 minutes in 100 DEG C of baking ovens；
(10.3)Si3N4Etching uses RIE techniques, etching gas selection CHF3(50sccm)+Ar (5sccm), after the completion of again
Carry out 3 minutes removing of photoresist by plasmas.Expose metal, form source, leakage and gate electrode pressure welding point, complete the making of whole device.
Embodiment 2
Making has 0.06 μm of depth, 4H-SiC metal-semiconductor field effect transistors of domatic grid 0.7 μm long.
In the making step of the present embodiment：
Step 8：Domatic groove 9 is formed on chase road between source electrode 7 and drain electrode 8.
1) in application rate：Under conditions of 3000R/min, 2 μm of glue thickness ＞, carried out using positive photoresist on chase road
Photoetching, is made reticle according to the position of domatic grid, uses electron beam exposure；
2) in special developer solution ((CH3)4NOH:H2O=1:4) in, raceway groove is developed, by pattern transfer in reticle
Onto the chase road between source region and drain region, gate figure window is formed, reactive ion etching process etching chase road is recycled, together
When obtain 0.7 μm of length, 0.5 μm away from source, depth is 0.01 μm of groove.And be successively 0.6 μm, 0.5 μm ... according to length
Successively decreased, each etching depth is 0.01mm, 6 electron beam exposures, etchings are carried out altogether, a domatic groove 9 is formed.
Step 9：Domatic grid 4 is formed on chase road.
1) photoresist is coated on chase road, reticle is made according to the position in grid region；
2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out about 35 seconds electron beam exposures after in special developer solution
((CH3)4NOH:H2O=1:4) in, grid region is developed, it is then rear in 100 DEG C of baking ovens to dry 3 minutes, by reticle
Pattern transfer forms grid region graphical window on the chase road between source region and drain region；
3) multi-target magnetic control sputtering platform is used, room temperature sputtering Ni (150nm)/Ti (150nm)/Au (300nm) multiple layer metal is made
For source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Slice, thin piece is heated in Pa, Ar flow 40sccm, sputter procedure
150℃；
4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C are moved into again after metal comes off
In Buty strippers, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, finally take out slice, thin piece and use low discharge nitrogen
Gas slowly dries up and (prevents metal gate to be touched down).Finally use the removing of photoresist by plasma 3 minutes, form the domatic grid that length is 0.7 μm
4。
Remaining step be the same as Example 1.
Embodiment 3：Make the 4H-SiC metal-semiconductor field effects with 0.08 μm of depth, domatic grid 0.7 μm long brilliant
Body pipe.
In the making step of the present embodiment：
Step 8：Domatic groove 9 is formed on chase road between source electrode 7 and drain electrode 8.
1) in application rate：Under conditions of 3000R/min, 2 μm of glue thickness ＞, carried out using positive photoresist on chase road
Photoetching, is made reticle according to the position of domatic grid, uses electron beam exposure；
2) in special developer solution ((CH3)4NOH:H2O=1:4) in, raceway groove is developed, by pattern transfer in reticle
Onto the chase road between source region and drain region, gate figure window is formed, reactive ion etching process etching chase road is recycled, together
When obtain 0.7 μm of length, 0.5 μm away from source, depth is 0.01 μm of groove.And be successively 0.6 μm, 0.5 μm ... according to length
Successively decreased, 7 electron beam exposures, etchings are carried out altogether, etching depth is 0.01mm every time for the first six time, the 7th etching depth
For 0.02mm, a domatic groove 9 is formed.
Step 9：Domatic grid 4 is formed on chase road.
1) photoresist is coated on chase road, reticle is made according to the position in grid region；
2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out about 35 seconds electron beam exposures after in special developer solution
((CH3)4NOH:H2O=1:4) in, grid region is developed, it is then rear in 100 DEG C of baking ovens to dry 3 minutes, by reticle
Pattern transfer forms grid region graphical window on the chase road between source region and drain region；
3) multi-target magnetic control sputtering platform is used, room temperature sputtering Ni (150nm)/Ti (150nm)/Au (300nm) multiple layer metal is made
For source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Slice, thin piece is heated in Pa, Ar flow 40sccm, sputter procedure
150℃；
4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C are moved into again after metal comes off
In Buty strippers, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, finally take out slice, thin piece and use low discharge nitrogen
Gas slowly dries up and (prevents metal gate to be touched down).Finally use the removing of photoresist by plasma 3 minutes, form the domatic grid that length is 0.7 μm
4。
Remaining step be the same as Example 1.
Summary, the 4H-SiC metal-semiconductor field effect transistors that the present invention makes have the following advantages that：
1. drain current is improved
For 4H-SiC metal-semiconductor field effect transistor structures, the size for the depletion region that its metallic perimeter is produced
It is relevant with the size of the area of semiconductor contact with metal.Metal and the area of semiconductor contact be bigger, and metallic perimeter exhausts
Area's area can also increase therewith.For common 4H-SiC metal-semiconductor field effect transistors, its metal contact area is only limitted to
Contact area below grid.And the 4H-SiC metal-semiconductor field effect transistors with domatic grid, metal contact is on slope
Shape grid part, smaller close to leakage side gate area, depletion region is moved to the direction close to grid, so that depletion region area is more
Small, channel resistance reduces so that drain current is improved.
2. frequency characteristic improves
Relative to the 4H-SiC metal-semiconductor field effect transistors of traditional structure, the 4H-SiC gold with domatic grid structure
Belong to semiconductor field effect transistor because the distance of its metal and depletion region is smaller, therefore the 4H-SiC metals with domatic grid
Semiconductor field effect transistor has higher gate-source capacitance, but has the 4H-SiC metal-semiconductor field effects of domatic grid
The lifting amplitude of the mutual conductance of transistor is but significantly larger than the 4H-SiC metal-semiconductor field effect transistors of traditional structure.So its
Cut-off frequency is improved, and that improves therewith also has the maximum oscillation frequency and maximum available gain of device.
Technical scheme is not limited to the limitation of above-mentioned specific embodiment, and every technique according to the invention scheme is done
The technology deformation gone out, each falls within protection scope of the present invention.
Claims (2)
1. a kind of 4H-SiC metal-semiconductor field effect transistors with domatic grid, semi-insulating including 4H-SiC from bottom to top
Substrate (1), p-type cushion (2), N-type channel layer (3), N-type channel layer (3) surface is provided with source electrode cap layers (5) and drain electrode cap layers
(6), source electrode cap layers (5) and drain electrode cap layers (6) surface are respectively equipped with source electrode (7) and drain electrode (8), it is characterised in that：The N
The upper surface of type channel layer (3) is set to the inclined domatic groove (9) in source electrode cap layers (5) side, and domatic groove (9) is interior to be provided with domatic grid
Pole (4), the lower surface of domatic grid (4) is engaged with domatic groove (9), upper surface and the N-type channel layer (3) of domatic grid (4)
Upper surface it is parallel, between the domatic grid (4) and source electrode cap layers (5) distance be less than domatic grid (4) with drain electrode cap layers (6)
The distance between,
The length of the domatic grid (4) is 0.7 μm,
Beeline between the domatic grid (4) and source electrode cap layers (5) is 0.5 μm.
2. a kind of preparation method of the 4H-SiC metal-semiconductor field effect transistors with domatic grid, it is characterised in that bag
Include following steps：
1) 4H-SiC SI-substrates (1) are cleaned, to remove surface contaminants；
2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates (1) Epitaxial growth 0.5, and through B2H6Doping in situ, formed dense
Spend for 1.4 × 1015cm-3P-type cushion (2)；
3) in the SiC layer of the μ m-thick of p-type cushion (2) Epitaxial growth 0.25, and through N2Doping in situ, is formed concentration be 3 ×
1017cm-3N-type channel layer (3)；
4) in the SiC layer of the N-type channel layer μ m-thick of (3) Epitaxial growth 0.2, and through N2Doping in situ, is formed concentration be 1.0 ×
1020cm-3N+Type cap layers；
5) in N+Photoetching is carried out in type cap layers successively and isolation is injected, isolated area and active area is formed；
6) source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy are carried out successively to active area, source electricity 0.5 μm long is formed
Pole (7) and drain electrode (8)；
7) to the N between source electrode (7) and drain electrode (8)+Type cap layers carry out photoetching, etching again, form etching depth and length point
Chase road that Wei be 0.2 μm and 2.2 μm；
8) electron beam exposure, etching are carried out to chase road, forms one 0.7 μm long, is 0.5 μm away from source electrode (7) side, depth is
0.01 μm of groove, and successively decreased successively according to length for 0.6 μm, 0.5 μm ... from source to leakage side, 7 electronics are carried out altogether
Beam exposure, etching, form a domatic groove (9)；
9) photoetching, magnetron sputtering and metal-stripping are carried out successively to domatic groove (9), domatic grid (4) 0.7 μm long is formed；
10) the 4H-SiC metal-semiconductor field effect transistors surface formed is passivated, anti-carved, form electrode pressure welding
Point, completes the making of device.
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| CN110808211A (en) * | 2019-11-08 | 2020-02-18 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor with inclined gate structure and preparation method thereof |
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| CN105870190B (en) * | 2016-04-22 | 2019-04-12 | 西安电子科技大学 | A kind of preparation method of the 4H-SiC metal-semiconductor field effect transistor with double high grid |
| CN110808212B (en) * | 2019-11-08 | 2022-08-30 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor and preparation method thereof |
| CN112951919B (en) * | 2021-01-29 | 2022-09-13 | 中国电子科技集团公司第十三研究所 | Inclined grid type gallium oxide field effect transistor and preparation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686737A (en) * | 1994-09-16 | 1997-11-11 | Cree Research, Inc. | Self-aligned field-effect transistor for high frequency applications |
| CN101964363A (en) * | 2010-08-06 | 2011-02-02 | 电子科技大学 | Metal-semiconductor field effect transistor with stepped buffer layer structure |
| CN103928529A (en) * | 2014-04-30 | 2014-07-16 | 西安电子科技大学 | 4H-SiC metal semiconductor field-effect transistor |
Family Cites Families (2)
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| US6906350B2 (en) * | 2001-10-24 | 2005-06-14 | Cree, Inc. | Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure |
| WO2005114746A1 (en) * | 2004-05-21 | 2005-12-01 | Nanyang Technological University | Novel structures of silicon carbide metal semiconductor field effect transistors for high voltage and high power applications |
-
2014
- 2014-10-28 CN CN201410587502.9A patent/CN104282764B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686737A (en) * | 1994-09-16 | 1997-11-11 | Cree Research, Inc. | Self-aligned field-effect transistor for high frequency applications |
| CN101964363A (en) * | 2010-08-06 | 2011-02-02 | 电子科技大学 | Metal-semiconductor field effect transistor with stepped buffer layer structure |
| CN103928529A (en) * | 2014-04-30 | 2014-07-16 | 西安电子科技大学 | 4H-SiC metal semiconductor field-effect transistor |
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|---|---|---|---|---|
| CN110808211A (en) * | 2019-11-08 | 2020-02-18 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor with inclined gate structure and preparation method thereof |
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