CN105097908A - Ultra high-speed pulse thyristor and manufacturing method thereof - Google Patents
Ultra high-speed pulse thyristor and manufacturing method thereof Download PDFInfo
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- CN105097908A CN105097908A CN201410213047.6A CN201410213047A CN105097908A CN 105097908 A CN105097908 A CN 105097908A CN 201410213047 A CN201410213047 A CN 201410213047A CN 105097908 A CN105097908 A CN 105097908A
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Abstract
The invention discloses an ultra high-speed pulse thyristor and a manufacturing method thereof. The ultra high-speed pulse thyristor belongs to the power semiconductor device technology field, and can be used to solve the problem of the conventional fast switching thyristor that the two-stage amplifying gate level structure cannot satisfy the requirements of strong trigger and ultra high surge current. The ultra high-speed pulse thyristor is formed by packaging a lower packaging member, a lower molybdenum plate, a silicon wafer, an upper molybdenum plate, and a gate level assembly together. N buffer layer zones are additionally arranged between a positive pole zone and a long group region, and therefore the silicon wafer can be provided with a P+NN-PN+ five-layer three-end structure. The positive pole zone is the transparent positive pole zone. The negative pole is provided with the polycell parallel connection negative pole structure, and the surface of the short group region between the cells is provided with the passivation layer. The gate level is provided with the deep groove structure. The VKG of the negative pole interface is in a range from 18 to 23V, and the VKG difference value of the same cell is smaller than 1 V. The ultra high-speed pulse thyristor has advantages of high di/dt tolerance, high frequency repeatability, high voltage, large current, low voltage drop, a certain turn-off capability, and applicability in high-power pulse power supply and high-power laser.
Description
Technical field
The invention belongs to power semiconductor device technology field.Be specifically related to a kind of ultrahigh speed pulse thyristor and manufacture method thereof, be mainly used in the device such as great power pulse power source, high power laser.
Background technology
Traditional opens thyristor device soon, many employings secondary amplifies gate leve structure, by amplifying gate leve, main thyristor device is triggered by force, but along with more and more higher to surge current requirements, the triode thyristor device that secondary amplifies gate leve structure cannot meet the demands.
Impulse power thyristor existingly opens trigger architecture by improving, original secondary is amplified gate leve structure and makes the direct triggering and conducting of cathode isolation mode into, not only have and large open line length, and decrease turn on time delay large in secondary amplification gate leve structure, further increase by high surface concentration the speed of opening.
Ultrahigh speed impulse power thyristor (PPT) is a kind of high di/dt, and there is the power semiconductor device of certain turn-off capacity, feature is that device surge capacity has higher di/dt tolerance, di/di can reach 10kA/ more than μ S, is mainly used in the common replacement scheme opening thyristor soon had higher requirements to di/dt tolerance.The diffusion of electric semiconductor and encapsulation technology are the important method in element manufacturing.
Summary of the invention
When the present invention is intended to for current triode thyristor application, require higher to di/dt tolerance in some application, triode thyristor amplifies gate leve structure and gradually cannot meet the need of market, there is provided a kind of high di/dt tolerance, high frequency repeatability, high voltage, big current, low pressure drop and there is ultrahigh speed pulse thyristor and the manufacture method thereof of certain turn-off capacity.
The technical solution of ultrahigh speed pulse thyristor of the present invention is: a kind of ultrahigh speed pulse thyristor, is formed by lower closure, lower molybdenum sheet, silicon chip, upper molybdenum sheet, upper closure, gate pole component package; This silicon chip comprises anode region, growing base area, short base and cathodic region four-layer structure and anode, negative electrode and gate pole three terminals; It is characterized in that: between described anode region and growing base area, increase N resilient coating district, make silicon chip be P
+nN-PN
+five layer of three end structure; Described anode region is transparent anode district; Described negative electrode is multi cell cathode construction in parallel, and the short base region surface of first intercellular is provided with passivation layer; Described gate pole is deep groove structure.
Multi cell described in the technical solution cathode construction in parallel of ultrahigh speed pulse thyristor of the present invention adopts multi-layer annular evenly to arrange, and cellular length-width ratio is 10 ~ 30:1.
The doping content in the N resilient coating district described in technical solution of ultrahigh speed pulse thyristor of the present invention is 1 × 10
16/ cm
3~ 1 × 10
18/ cm
3between, junction depth is 18 ~ 40 μm.
The transparent anode district concentration described in technical solution of ultrahigh speed pulse thyristor of the present invention is 1 × 10
18/ cm
3~ 1 × 10
20/ cm
3between, junction depth is 8 ~ 30 μm.
The cathodic region surface concentration described in technical solution of ultrahigh speed pulse thyristor of the present invention is 1 × 10
19/ cm
3~ 1 × 10
21/ cm
3between, junction depth 18 ~ 30 μm.
The groove depth of the gate pole described in technical solution of ultrahigh speed pulse thyristor of the present invention is 18 ∽ 35 μm, and the oxide layer that the PN junction surface between cathodic region and short base has 200 ~ 300nm thick is or/and polyimide passivation layer.
The surface impurity concentration of the short base described in the technical solution of ultrahigh speed pulse thyristor of the present invention is 1 × 10
17/ cm
3~ 8 × 10
19/ cm
3, junction depth 80 ~ 140 μm.
The technical solution of the manufacture method of ultrahigh speed pulse thyristor of the present invention is: a kind of manufacture method of ultrahigh speed pulse thyristor, comprises the following steps:
1. select that thickness is 500-950 μm, resistivity is 250 ∽ 500 Ω cm, crystal orientation <111> or <100>, N-type NTD monocrystalline silicon piece, the process of silicon chip two-sided employing phosphorus absorption technique;
2. P district diffusion: silicon chip is two-sided diffuses to form short base by the two Impurity Distribution of Al, Ga, and the junction depth of short base is 80 ∽ 140 μm, and short base region surface impurity concentration is 1 × 10
17∽ 8 × 10
19/ cm
3;
3. resilient coating diffusion: adopt resilient coating phosphonium ion to inject to the silicon chip anode surface of reduction processing or phosphorus perfect diffusion method formation N resilient coating;
4. N+ diffusion: carry out complete surperficial phosphorus and diffuse to form cathodic region on the short base of silicon chip, cathodic region surface concentration is 1 × 10
19/ cm
3∽ 1 × 10
21/ cm
3, cathodic region junction depth is 18 ∽ 30 μm;
5. P+ diffusion: carry out transparent anode diffusion at N buffer-layer surface, junction depth is 8 ∽ 30 μm, anode region surface impurity concentration 1 × 10
18∽ 1 × 10
20/ cm
3;
6. negative electrode grooving: target district carries out selectivity and deep-cuts groove process, the grooving degree of depth is 18 ∽ 35 μm; To short base, surface, cathodic region carry out surface and PN junction oxide layer or and adopt polyimides protection;
7. the two-sided evaporated metal layer of silicon chip, target face selective etch, forms gate pole, negative electrode; Silicon chip edge carries out oblique angle table top moulding, negative bevel angle θ
2size is: 1.5o≤θ
2≤ 5o, table top orthogonal rake θ
1angular dimension is: 20o≤θ
1≤ 60o;
8. carry out low temperature crimping to silicon chip and molybdenum sheet, upper molybdenum sheet is as the negative electrode of chip, and lower molybdenum sheet is as the anode of chip, and gate pole is picked out by gate leve lead-in wire;
9. last by closure, upper closure, gate pole component package under semiconductor chip and shell.
The present invention manufacture the method for ultrahigh speed pulse thyristor the resilient coating phosphonium ion described in technical solution inject or phosphorus perfect diffusion method be:
Resilient coating phosphonium ion injects+diffusion:
1. phosphonium ion injects and prepares (equipment, frock, process);
2. phosphonium ion injects;
3. high-temperature oxydation advances;
Process conditions and formula are:
1. dosage: 1 ~ 8 × 10
16, energy: 40 ~ 100Kev, implant angle: 5 ~ 9 degree;
2. propulsioning condition: temperature: 1200 ∽ 1250 DEG C, advances the time: 20-30h, N2=2.5L/min, O2=2L/min;
Resilient coating phosphorus perfect diffusion process conditions:
1. phosphorus pre-deposition condition: 1120 ∽ 1220 DEG C, LN2=50 ~ 200ml/min, pre-deposition time: 3 ~ 30 minutes, constant temperature time 15 minutes;
2. phosphorus propulsioning condition: temperature 1200 ~ 1240 DEG C, N2=6L/min, O2=2L/min.
The transparent anode district diffusion technology described in technical solution that the present invention manufactures the method for ultrahigh speed pulse thyristor is:
1. boron source adopts alcohol source or latex source, is alcohol or the latex source saturated solution of boron oxide, adopts constant surface source method of diffusion;
2. propulsioning condition: 1180 ∽ 1250 DEG C, N2=6L/min, O2=0.5L/min, time 120 ~ 300min.
The present invention, owing to increasing N resilient coating district between existing anode region and growing base area, makes silicon chip be P
+nN-PN
+five layer of three end structure; anode region adopts transparent anode district; gate pole adopts deep groove structure; negative electrode adopts multi cell cathode construction in parallel, and the surface between cellular adopts polyimide passivation layer protection, gate leve centered by cathode plane center; thus cathode plane passes through the identical structure cell of gate leve turn-off thyristor; deep trouth is dug, PN junction protect oxide layer, the V of PN junction by negative electrode
kGcontrol at 18 ~ 23V, V in sheet
kGuniformity 1V.
The feature technology that the present invention has is as follows:
1, blocking voltage 4500 ∽ 5000V, high di/dt tolerance, can reach 5000A/ more than μ s;
2, deep etching, isolates single devices in parallel cellular;
3, grooving PN junction thermal oxidation SiO
2protection and the protection of photoetching polyimide passivation layer;
4, anode surface adopts resilient coating and transparent anode design;
5, resilient coating ion implantation and high-temperature oxydation advance;
6, low stress total head connects encapsulation.
The present invention has high di/dt tolerance, high frequency repeatability, high voltage, big current, low pressure drop and have the feature of certain turn-off capacity.The present invention is mainly used in ultrahigh speed pulse thyristor.
Accompanying drawing explanation
Fig. 1 is product structure schematic diagram of the present invention.
Fig. 2 is silicon chip structural representation of the present invention.
Fig. 3 is silicon chip Impurity Distribution schematic diagram of the present invention.
Fig. 4 is silicon wafer fabrication process flow chart of the present invention.
Fig. 5 is a kind of cathode junction composition of silicon chip of the present invention.
Fig. 6 is the another kind of cathode junction composition of silicon chip of the present invention.
In figure: A-anode, K-negative electrode, G-gate pole, closure under 1-, molybdenum sheet under 2-, 3-silicon chip, the upper molybdenum sheet of 4-, the upper closure of 5-, 6-gate pole assembly, 41-P
+anode region, 42-N resilient coating district, 43-N-growing base area, the short base of 44-P2,45-N
+cathodic region, 46-cathode metal layer, 47-gate metal layer, 48-anode metal layer.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
As shown in Figure 1 to Figure 3.Ultrahigh speed impulse power thyristor of the present invention is encapsulated formed by lower closure 1, lower molybdenum sheet 2, silicon chip 3, upper molybdenum sheet 4, upper closure 5, gate pole assembly 6.Lower molybdenum sheet 2, silicon chip 3, upper molybdenum sheet 4 once crimp semiconductor chip integrally.Silicon chip 3 comprises P
+anode region 41, N resilient coating district 42, N-growing base area 43, the short base 44 of P2, N
+cathodic region 45 and anode A, negative electrode K and gate pole G tri-terminals.N resilient coating district 42 is P
+increase between anode region 41 and N-growing base area 43, the doping content of N resilient coating is 1 × 10
16/ cm
3~ 1 × 10
18/ cm
3between, make silicon chip form P
+nN-PN
+five layer of three end structure.P
+anode region 41 is transparent anode, transparent anode district P
+concentration is 1 × 10
18/ cm
3~ 1 × 10
20/ cm
3between.Gate pole G is deep groove structure, and negative electrode K is multi cell cathode construction in parallel, and adopt multi-layer annular evenly to arrange, cellular length-width ratio is 10 ~ 30:1, and the surface between cellular adopts polyimide passivation layer protection.The cathode plane Impurity Distribution degree of depth is 18 ~ 30um, and concentration is 1 × 10
19/ cm
3~ 1 × 10
21/ cm
3between, it is 18 ~ 23V that PN junction voltage design requires, in sheet, uniformity is less than 1V, and PN junction place has thickness to be the oxide layer of 200 ~ 300nm, beyond the gate leve of cathode plane center, gate leve has polyimide surface passivation layer.P
+anode region 41, the short base 44 of P2 adopt the two matter diffusion of Ga, Al, and the Ga impurity concentration of the short base 44 of P2 is 1 × 10
17/ cm
3~ 5 × 10
19/ cm
3between, P2 short base 44 skin is high concentration N
+type impurity layer, N
+type impurity layer concentration is 1 × 10
19/ cm
3~ 1 × 10
21/ cm
3between.The doping content of N-growing base area 43 substrate is 1 × 10
12/ cm
3~ 1 × 10
14/ cm
3between.Silicon chip 3 thickness is 500-950 μm, silicon chip 3 table top orthogonal rake angle θ
1size is: 20o≤θ
1≤ 60o, negative bevel angle θ
2size is: 1.5o≤θ
2≤ 5o.Ultrahigh speed impulse power thyristor P
+nN-PN
+five-layer structure chip Impurity Distribution curve as shown in Figure 3.
As shown in Figure 4.The manufacture method of a kind of ultrahigh speed pulse thyristor of the present invention, comprises the following steps:
1. select that thickness is 500-950 μm, resistivity is 250 ∽ 500 Ω cm, crystal orientation <111> or <100>, N-type substrate NTD monocrystalline silicon piece, silicon chip doping content is 1 × 10
12/ cm
3~ 1 × 10
14/ cm
3between, the process of silicon chip two-sided employing phosphorus absorption technique;
2. P district diffusion: silicon chip is two-sided diffuses to form the short base of P2 by the two Impurity Distribution of Al, Ga, and the junction depth of the short base of P2 is the short base region surface impurity concentration of 80 ∽ 140 μm, P2 is 1 × 10
17∽ 8 × 10
19/ cm
3;
3. resilient coating diffusion: adopt resilient coating phosphonium ion to inject to the silicon chip anode surface of reduction processing or phosphorus perfect diffusion method formation N resilient coating;
4. N+ diffusion: carry out complete surperficial phosphorus and diffuse to form N on the short base of silicon chip P2
+cathodic region, N
+cathodic region surface concentration is 1 × 10
19/ cm
3∽ 1 × 10
21/ cm
3, N
+cathodic region junction depth is 18 ∽ 30 μm;
5. P+ diffusion: carry out transparent anode P+ diffusion at N buffer-layer surface, junction depth is 8 ∽ 30 μm, anode region P+ surface impurity concentration 1 × 10
18∽ 1 × 10
20/ cm
3;
6. negative electrode grooving: to N
+cathodic region is carried out selectivity and is deep-cut groove process, and the grooving degree of depth is 18 ∽ 35 μm; To the short base of P2, N
+surface, cathodic region is carried out surface and PN junction oxide layer or is protected with employing polyimides;
7. the two-sided evaporated metal layer of silicon chip, forms anode metal layer 48, target face selective etch, forms gate metal layer 47, cathode metal layer 46; Silicon chip edge carries out table top moulding, negative bevel angle θ
2size is: 1.5o≤θ
2≤ 5o, table top orthogonal rake θ
1angular dimension is: 20o≤θ
1≤ 60o;
8. carry out low temperature crimping to silicon chip and molybdenum sheet, upper molybdenum sheet is as the negative electrode K of chip, and lower molybdenum sheet is as the anode A of chip, and gate pole is picked out by gate leve lead-in wire;
9. last closure 1, upper closure 5, gate pole assembly 6 under semiconductor chip and shell to be encapsulated.
The resilient coating diffusion of ultrahigh speed pulse thyristor of the present invention adopts phosphonium ion to inject or phosphorus perfect diffusion method:
Resilient coating phosphonium ion injects+diffusion:
1. phosphonium ion injects and prepares (equipment, frock, process);
2. phosphonium ion injects;
3. high-temperature oxydation advances.
Process conditions are:
1. dosage: 1 ~ 8 × 10
16, energy: 40 ~ 100Kev, implant angle: 5 ~ 9 degree;
2. propulsioning condition: temperature: 1200 ∽ 1250 DEG C, advances the time: 20-30h, N2=2.5L/min, O2=2L/min;
Resilient coating phosphorus perfect diffusion process conditions:
1. phosphorus pre-deposition condition, 1120 ∽ 1220 DEG C, LN2=50 ~ 200ml/min, pre-deposition time: 3 ~ 30 minutes, constant temperature time 15 minutes;
2. phosphorus propulsioning condition: temperature 1200 ~ 1240 DEG C, N2=6L/min, O2=2L/min.
The transparent anode (p+) that the present invention manufactures ultrahigh speed pulse thyristor adopts diffusion technology to be:
1. boron source adopts alcohol source or latex source, is alcohol or the latex source saturated solution of boron oxide, adopts constant surface source method of diffusion;
2. propulsioning condition, 1180 ∽ 1250 DEG C, N2=6L/min, O2=0.5L/min, time 120 ~ 300min.
Beyond the gate pole of cathode plane center, gate pole adopts polyimides to form passivation layer protection, aluminium lamination can be protected from erosion, increase creepage distance.
It is 10 ∽ 30 μ s that chip adopts the method for electron irradiation to control minority carrier life time, can be 10 ∽ 80 μ s the adjusting means turn-off time.
A kind of embodiment chip negative electrode schematic diagram of the present invention as shown in Figure 5.
Another kind of embodiment chip negative electrode schematic diagram of the present invention as shown in Figure 6.
Make Φ 50mm ultrahigh speed pulse thyristor scheme product according to technique scheme, contrasted as follows with triode thyristor test parameter:
Data show, according to this programme make ultrahigh speed pulse thyristor its dynamically open parameter, on-state voltage drop, di/dt test performance all considerably beyond triode thyristor.
Have a fling at some Φ 100mm ultrahigh speed pulse thyristor devices, through test and test, when applying less trigger current between gate pole G of the present invention and negative electrode K (usual 1 ∽ 1.5A), ultrahigh speed pulse thyristor is open-minded, blocking voltage reaches 4500 ∽ 5000V, mean on state current I
t (AV)reach 1600A ∽ 1800A, current-rising-rate di
t/ dt can reach 10KA/ μ s.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Therefore everyly do not depart from content of the present invention, according to technical spirit of the present invention to any amendment made for any of the above embodiments, equivalently to replace, equivalence change and modifying, all still belong to the scope of technical solution of the present invention protection.
Claims (10)
1. a ultrahigh speed pulse thyristor, is encapsulated formed by lower closure (1), lower molybdenum sheet (2), silicon chip (3), upper molybdenum sheet (4), upper closure (5), gate pole assembly (6); This silicon chip (3) comprises anode region (41), growing base area (43), short base (44) and cathodic region (45) four-layer structure, and anode (A), negative electrode (K) and gate pole (G) three terminals; It is characterized in that: between described anode region (41) and growing base area (43), increase N resilient coating district (42), make silicon chip be P
+nN-PN
+five layer of three end structure; Described anode region (41) is transparent anode district; Described negative electrode (K) is multi cell cathode construction in parallel, and short base (44) surface of first intercellular is provided with passivation layer; Described gate pole (G) is deep groove structure.
2. a kind of ultrahigh speed pulse thyristor according to claim 1, is characterized in that: described multi cell cathode construction in parallel adopts multi-layer annular evenly to arrange, and cellular length-width ratio is 10 ~ 30:1.
3. a kind of ultrahigh speed pulse thyristor according to claim 1 and 2, is characterized in that: the doping content in described N resilient coating district (42) is 1 × 10
16/ cm
3~ 1 × 10
18/ cm
3between, junction depth is 18 ~ 40 μm.
4. a kind of ultrahigh speed pulse thyristor according to claim 1 and 2, is characterized in that: described transparent anode district concentration is 1 × 10
18/ cm
3~ 1 × 10
20/ cm
3between, junction depth is 8 ~ 30 μm.
5. a kind of ultrahigh speed pulse thyristor according to claim 1 and 2, is characterized in that: described cathodic region (45) surface concentration is 1 × 10
19/ cm
3~ 1 × 10
21/ cm
3between, junction depth 18 ~ 30 μm.
6. a kind of ultrahigh speed pulse thyristor according to claim 1 and 2, it is characterized in that: the groove depth of described gate pole (G) is 18 ∽ 35 μm, and the oxide layer that the PN junction surface between cathodic region (45) and short base (44) has 200 ~ 300nm thick is or/and polyimide passivation layer.
7. a kind of ultrahigh speed pulse thyristor according to claim 1 and 2, is characterized in that: the surface impurity concentration of described short base (44) is 1 × 10
17/ cm
3~ 8 × 10
19/ cm
3, junction depth 80 ~ 140 μm.
8. a method for the ultrahigh speed pulse thyristor described in manufacturing claims 1 or 2, is characterized in that comprising the following steps:
1. select that thickness is 500-950 μm, resistivity is 250 ∽ 500 Ω cm, crystal orientation <111> or <100>, N-type NTD monocrystalline silicon piece, the process of silicon chip two-sided employing phosphorus absorption technique;
2. P district diffusion: silicon chip is two-sided diffuses to form short base (44) by the two Impurity Distribution of Al, Ga, and the junction depth of short base (44) is 80 ∽ 140 μm, and short base (44) surface impurity concentration is 1 × 10
17∽ 8 × 10
18(10
19)/cm
3;
3. resilient coating diffusion: adopt resilient coating phosphonium ion to inject to the silicon chip anode surface of reduction processing or phosphorus perfect diffusion method formation N resilient coating;
4. N+ diffusion: carry out complete surperficial phosphorus and diffuse to form cathodic region (45) on the short base of silicon chip (44), cathodic region (45) surface concentration is 1 × 10
19/ cm
3∽ 1 × 10
21/ cm
3, cathodic region (45) junction depth is 18 ∽ 30 μm;
5. P+ diffusion: carry out the diffusion of transparent anode district at N buffer-layer surface, junction depth is 8 ∽ 30 μm, anode region (41) surface impurity concentration 1 × 10
18∽ 1 × 10
20/ cm
3;
6. negative electrode grooving: target district (45) are carried out selectivity and deep-cut groove process, the grooving degree of depth is 18 ∽ 35 μm; Short base (44), cathodic region (45) surface are carried out surface and PN junction oxide layer or protected with employing polyimides;
7. the two-sided evaporated metal layer of silicon chip, target face selective etch, forms gate pole (G), negative electrode (K); Silicon chip edge carries out oblique angle table top moulding, negative bevel angle θ
2size is: 1.5o≤θ
2≤ 5o, table top orthogonal rake θ
1angular dimension is: 20o≤θ
1≤ 60o;
8. carry out low temperature crimping to silicon chip and molybdenum sheet, upper molybdenum sheet is as the negative electrode (K) of chip, and lower molybdenum sheet is as the anode (A) of chip, and gate pole (G) is picked out by gate leve lead-in wire;
9. last closure (1), upper closure (5), gate pole assembly (6) under semiconductor chip and shell to be encapsulated.
9. the method for manufacture ultrahigh speed pulse thyristor according to claim 8, is characterized in that described resilient coating phosphonium ion injects or phosphorus perfect diffusion method is:
Resilient coating phosphonium ion injects+diffusion:
1. phosphonium ion implantation dosage: 1 ~ 8 × 10
16, energy: 40 ~ 100Kev, implant angle: 5 ~ 9 degree;
2. high-temperature oxydation propulsioning condition: temperature: 1200 ∽ 1250 DEG C, advances the time: 20-30h, N2=2.5L/min, O2=2L/min;
Resilient coating phosphorus perfect diffusion process conditions:
1. phosphorus pre-deposition condition: 1120 ∽ 1220 DEG C, LN2=50 ~ 200ml/min, pre-deposition time: 3 ~ 30 minutes, constant temperature time 15 minutes;
2. phosphorus propulsioning condition: temperature 1200 ~ 1240 DEG C, N2=6L/min, O2=2L/min.
10. the method for manufacture ultrahigh speed pulse thyristor according to claim 8 or claim 9, is characterized in that described transparent anode diffusion technology is:
1. boron source adopts alcohol source or latex source, is alcohol or the latex source saturated solution of boron oxide, adopts constant surface source method of diffusion;
2. propulsioning condition: 1180 ∽ 1250 DEG C, N2=6L/min, O2=0.5L/min, time 120 ~ 300min.
Priority Applications (1)
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|---|---|---|---|
| CN201410213047.6A CN105097908A (en) | 2014-05-20 | 2014-05-20 | Ultra high-speed pulse thyristor and manufacturing method thereof |
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|---|---|---|---|
| CN201410213047.6A CN105097908A (en) | 2014-05-20 | 2014-05-20 | Ultra high-speed pulse thyristor and manufacturing method thereof |
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|---|---|
| CN105097908A true CN105097908A (en) | 2015-11-25 |
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ID=54577949
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|---|---|---|---|
| CN201410213047.6A Pending CN105097908A (en) | 2014-05-20 | 2014-05-20 | Ultra high-speed pulse thyristor and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493243A (en) * | 2018-03-23 | 2018-09-04 | 西安理工大学 | A kind of silicon carbide light triggered thyristor with the short base area of varying doping |
| CN110164980A (en) * | 2019-05-24 | 2019-08-23 | 湖北台基半导体股份有限公司 | A kind of fast soft-recovery diode of high pressure |
| CN114005743A (en) * | 2021-10-13 | 2022-02-01 | 华中科技大学 | Square semiconductor pulse power switch and preparation method thereof |
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2014
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| CN1035024A (en) * | 1988-01-27 | 1989-08-23 | 亚瑞亚·勃朗·勃威力有限公司 | The turn-off semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493243A (en) * | 2018-03-23 | 2018-09-04 | 西安理工大学 | A kind of silicon carbide light triggered thyristor with the short base area of varying doping |
| CN108493243B (en) * | 2018-03-23 | 2021-04-06 | 西安理工大学 | Silicon carbide light-triggered thyristor with variable doping short base region |
| CN110164980A (en) * | 2019-05-24 | 2019-08-23 | 湖北台基半导体股份有限公司 | A kind of fast soft-recovery diode of high pressure |
| CN114005743A (en) * | 2021-10-13 | 2022-02-01 | 华中科技大学 | Square semiconductor pulse power switch and preparation method thereof |
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Application publication date: 20151125 |