CN105097758A - 衬底、其半导体封装及其制造方法 - Google Patents

衬底、其半导体封装及其制造方法 Download PDF

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CN105097758A
CN105097758A CN201410186379.XA CN201410186379A CN105097758A CN 105097758 A CN105097758 A CN 105097758A CN 201410186379 A CN201410186379 A CN 201410186379A CN 105097758 A CN105097758 A CN 105097758A
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conductive trace
layer
upper wiring
wiring layer
line layer
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CN105097758B (zh
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陈天赐
王圣民
陈光雄
李育颖
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种衬底、其半导体封装及其制造方法。所述衬底包括上线路层及下线路层，所述上线路层包括至少一个导电迹线及至少一个接垫，所述下线路层包括至少一个导电迹线及至少一个接垫，其中所述上线路层的所述至少一个导电迹线与所述下线路层的所述至少一个导电迹线的最小距离并非零。

Description

衬底、其半导体封装及其制造方法
技术领域
本发明涉及一种用于半导体封装的衬底及其制造方法。
背景技术
由于价格低廉及可靠性高，引线框架封装在集成电路封装领域应用了很长一段时间，然而，随着集成电路产品缩小化以及对于输入/输出(input/output，I/O)数目增加的需求，慢慢地，部分集成电路产品便随着规格的要求提高，由引线框架(leadframe)封装转移至四方扁平无引线(quadflatnolead,QFN)封装及球格阵列(ballgridarray,BGA)封装。因此，目前常看到QFN应用于包括高频传输(例如，经由RF频宽进行的高频传输)的芯片封装，BGA被广泛应用在具有高I/O数以及需要较佳电性及热性能的芯片(例如，中央处理器及绘图芯片)；而引线框架(leadframe)封装因其能提供具有成本效益的解决方案，常应用于低I/O数的芯片。
发明内容
本发明的实施例涉及一种衬底，其包含上线路层及下线路层，所述上线路层包括至少一导电迹线及至少一接垫，所述下线路层包括至少一导电迹线及至少一接垫，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线的最小距离并非零。
本发明的另一实施例涉及一种半导体封装，其包含：衬底，所述衬底包含上线路层及下线路层，所述上线路层包括至少一导电迹线及至少一接垫，所述下线路层包括至少一导电迹线及至少一接垫，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线的最小距离并非零；以及裸片，其电性连接于所述上线路层。
本发明的另一实施例涉及一种制造衬底的方法，其包含：提供导电箔，所述导电箔包括第一表面及第二表面；图案化所述第一表面以形成至少一第一导电迹线及第一接垫；以及图案化所述第二表面以形成至少一第二导电迹线及第二接垫。
附图说明
图1为图6所示的本发明衬底的实施例的沿着C-C'剖面线的剖面图。
图2为图6所示的本发明衬底的实施例的沿着D-D'剖面线的剖面图。
图3为本发明衬底的实施例的剖面图。
图4显示上线路层的实施例的俯视图。
图5显示下线路层的实施例的俯视图。
图6显示下线路层与上线路层组合而成的完整电路图样的实施例的俯视图。
图7A显示本发明衬底的相邻两导电迹线的相对位置的实施例的俯视示意图；图7B显示本发明衬底的上导电迹线12及其接垫24相对于图7A方向的前视示意图；图7C显示本发明衬底的下导电迹线10及其接垫18相对于图7A方向的前视示意图；以及图7D显示本发明衬底的相邻两导电迹线10及12相对于图7A方向的侧视示意图。
图8A显示未分拆成两层前单一层电路图样的相关配置位置的实施例的示意图；以及图8B显示图8A的单一层电路图样分拆成两层时的相关配置位置示意图。
图9显示本发明半导体封装的实施例的示意图。
图10显示本发明半导体封装的另一实施例的示意图。
图11显示本发明半导体封装的另一实施例的示意图。
图12A至12R显示本发明衬底的制造方法的一实施例的示意图。
具体实施方式
请参看图1，其为图6所示的本发明衬底的实施例的沿着C-C'剖面线的剖面图。衬底8包含具有多个下导电迹线10及接垫24的下线路层1，多个下导电迹线10彼此电性绝缘；以及位于下线路层1上方的具有多个上导电迹线12及接垫(图未显示)的上线路层2，多个上导电迹线12彼此电性绝缘，其中上线路层的至少一导电迹线与下线路层的至少一导电迹线的最小距离并非零。上线路层2的至少一导电迹线12具有上表面12a及下表面12b，所述下线路层1的至少一导电迹线10具有上表面10a及下表面10b，所述上线路层的至少一导电迹线12的下表面12b与下线路层的至少一导电迹线10的下表面10b实质上位于同一平面。
上线路层2的部分上导电迹线12与下线路层1的部分下导电迹线10可间隔排列。在实施例中，当两条上导电迹线12或下导电迹线10间另有两条导电迹线通过时，此两条导电迹线可利用分成上下两层电路层1及2方式完成。在另一实施例中，当下线路层的两邻近接垫24间有两条导电迹线经过时，此两条导电迹线也可利用分成上下两层电路层1及2方式完成。其中，是否拆分成上下两层电路层方式完成可依据导电迹线的线宽与线距的值而定，线宽及线距的值例如依工艺能力而决定。例如，当两邻近接垫或位同一层的两条导电迹线的间距设计为固定值(例如，为310μm)，且有另两条导电迹线通过其间，当以蚀刻工艺形成此另两条导电迹线的线宽且线距的能力值分别为50μm及70μm时，此两条导电迹线即会以上下两层电路方式完成布线。根据形成导电迹线的蚀刻技术不同，导电迹线的侧壁轮廓可形成不同的形状。在一实施例中，上线路层2的上导电迹线的侧壁轮廓可呈现往内的弧形且下线路层2的下导电迹线的侧壁轮廓可呈现往内的弧形。在实施例中，上线路层2的上导电迹线12与下线路层1的接垫(球垫)24(也可参看图6的B区)可重叠。
衬底可包含保护层，围绕上线路层2的多个上导电迹线12及下线路层1的多个下导电迹线10。保护层可分为围绕且覆盖多个上导电迹线的上保护层31，及围绕且覆盖多个下导电迹线的下保护层21。下保护层21可具有开口以露出接垫24(例如，球垫)，可供球栅阵列焊球形成于其上。
请参看图2，其为图6所示的本发明衬底的实施例的沿着D-D'剖面线的剖面图。衬底8包含具有多个下导电迹线10及接垫(图未显示)的下线路层1，多个下导电迹线10彼此电性绝缘；及位于下线路层1上方的具有多个上导电迹线12及接垫18的上线路层2，多个上导电迹线12彼此电性绝缘。接垫18上可具有表面处理层35(例如，镍/金层)，以作为打线端点，以打线(wirebond)连接至芯片。在一实施例中，上线路层2的接垫(指部)18与下线路层1的下导电迹线10可重叠(也可参看图6的A区)。
请参看图3，其为本发明衬底的另一实施例的剖面图。衬底8'与图2的衬底8的差别在于至少一上线路层2的接垫18下方具有加强层20，用以提供接垫18额外的支撑力。在实施例中，所述加强层20可为与下导电迹线10同样材料的金属层，且在同一工艺中形成，其中加强层的形状及大小视设计需求而有所不同。举例而言，加强层20的宽度及长度可较下导电迹线10小。
根据本发明的实施例，下保护层21及上保护层31的材质可为感光型非导电高分子，例如，可选自但不限于：聚苯并二恶唑(polyparaphenylenebenzobisoxazole,PBO)、聚酰亚胺、苯基环丁烯或其组合等，由此，下保护层21能利用微影工艺形成显露出下线路层1(接垫)的开口及上保护层31能利用微影工艺形成显露出上线路层2(接垫)的开口。在另一实施例中，所述下保护层21及上保护层31也可皆为防焊膜(soldermask)。防焊膜的材料可为感光型非导电高分子。
根据本发明的实施例，下线路层1及上线路层2的材质只要可作为电路者即可，例如但不限于铜。参看图4至6，其中图4显示所述上线路层2的实施例的俯视图；图5显示所述下线路层1的实施例的俯视图；以及图6显示下线路层1与上线路层2组合而成的电路图样的实施例的俯视图。所属领域的技术人员可根据不同用途的电路图样，决定可分拆至所述上线路层2的导电迹线及接垫及可分拆至所述下线路层1的导电迹线及接垫。举例而言，如图4所示，在某些实施例中，接垫(圆形亮点)可皆分在同一层，且在某些实施例中，如果电路图样中两接垫间有两条以上导电迹线的话，那么所述两接垫间的导电迹线可间隔分成上下两层，因同层导电迹线间的间距变宽，其对于蚀刻的容忍度增加，故可改进蚀刻的良率。除此之外，上下两层相邻导电迹线的间距也可缩短。如图4所示，两接垫间的线路X1及X2配置在同一层；且如图5所示，两接垫间的线路Y1及Y2配置在同一层。
为利于说明，请参看图7A至7D，图7A显示本发明衬底的相邻两导电迹线的相对位置的实施例的俯视示意图；图7B显示本发明衬底的上导电迹线12及其接垫24相对于图7A方向的前视示意图；图7C显示本发明衬底的下导电迹线10及其接垫18相对于图7A方向的前视示意图；以及图7D显示本发明衬底的相邻两导电迹线10相对于图7A方向的侧视示意图。如图7B所示，部分下导电迹线的接垫24可与上导电迹线12重叠。如图7C所示，部分上导电迹线的接垫18可与下导电迹线10重叠。如图7D所示，相邻的导电迹线10及12可分成上下两层。
参看图8A及8B，其显示同一电路层分拆前与分拆后两者线路相关位置的比较。图8A显示未分拆成两层前单一层电路图样37相关配置位置的一实施例的示意图。图8B显示图8A的单一层电路图样分拆成两层37a及37b时的相关配置位置示意图。在实施例中，两层37a及37b相加的厚度相当于单一层电路图样37的厚度。如图8A及8B所示，当同一层电路分拆成两层37a及37b时，很明显，同一层且相邻的两线路间的间距W2相较于分拆前的间距W1会变宽(W2>W1)，因此，其对于蚀刻的容忍度增加，可改进蚀刻的良率。此外，根据本发明的实施例，上下两层相邻线路间距在设计上，W3可不等于W1，因此，在本发明的一实施例中，上下两层相邻线路间距可设计为较短(W3<W1)，故总体而言，本实施例将单一层线路分拆成两层，因此可提高衬底的布线能力且提高线路密度，也可提高衬底工艺的良率。
参看图9，其显示本发明半导体封装的实施例的示意图。所述半导体封装14包括衬底8、裸片3、底胶9、接垫18、多个焊线7及封装材料5。裸片3通过底胶9附着至衬底8，及接垫18形成于上保护层31的开口中，以供焊线7连接。封装材料5位于所述上保护层31上，包覆裸片3及底胶9。此外，在实施例中，多个焊球11形成于显露于下保护层21的开口的下线路层1(接垫)上以作为外部连接。在另一实施例中，也可以形成电镀锡于显露于下保护层21的开口的下线路层1(接垫)上以作为外部连接。
参看图10，其显示本发明半导体封装的另一实施例的示意图。其与图9所示的半导体封装不同之处在于图10的裸片3利用倒装芯片形式，透过焊球36与衬底8的上线路层2电性连接。此外，在实施例中，多个焊球11可形成于显露于下保护层21的开口的下线路层1(接垫)上以作为外部连接。
参看图11，其显示本发明半导体封装的另一实施例的示意图。其与图9所示的半导体封装不同之处在于图11的半导体封装可包含两层衬底，两层衬底通过例如导电胶22来电性连接这两层衬底，其中两层衬底可利用同样的方式形成，且各衬底皆包含上线路层及下线路层，上线路层所包括的至少一上导电迹线与下线路层所包括的至少一下导电迹线的最小距离并非零。在实施例中，多个焊球可形成于显露于其中的衬底的下保护层21的开口的下线路层1(接垫)上以作为外部连接。
参看图12A至12R，其显示本发明衬底的制造方法的实施例的示意图。
参看图12A，提供导电箔13。参看图12B，形成第一干膜15于导电箔13上。参看图12C，图案化第一干膜15，以显露部分导电箔13，界定下线路层的导电迹线及接垫位置，其中部分导电迹线位置对应于上层线路的指部。图案化过程可通过微影方法达成。
参看图12D，去除部分导电箔13，以形成下线路层1的导电迹线及接垫19。导电箔13可通过蚀刻或其它方式去除。参看图12E，去除图案化的第一干膜17，露出下线路层1的导电迹线及接垫19。在某些实施例中，导电箔13通过蚀刻去除，而如图12E所示，通过蚀刻去除导电箔13所产生的下线路层1的导电迹线的侧壁轮廓非平面，例如，其会由上往下呈现往内的弧形(或如图12M的上线路层2所示，下线路层1的导电迹线两侧因反过来会由下往上呈现往内的弧形)。
参看图12F，形成下保护层21于下线路层1的导电迹线及接垫上。下保护层21围绕且覆盖导电迹线及接垫。在某些实施例中，下保护层21可利用旋转涂布、喷射涂布或层压方式形成。参看图12G，图案化下保护层21，以形成开口23，界定下线路层1中欲形成接垫的位置，其中部分接垫位置对应于上层线路的导电迹线。图案化过程可通过微影方法达成。
参看图12H，形成第二干膜25于导电箔13形成下线路层1的相对表面上。参看图12I，图案化第二干膜25，以显露部分导电箔13，以在形成下线路层1的相对表面上界定上层线路的导电迹线及接垫位置。图案化过程可通过微影方法达成。参看图12J，自导电箔13去除未被图案化第二干膜27所覆盖的部分，以形成具有多个上导电迹线及接垫29的上线路层2。导电箔13可通过蚀刻或其它方式去除。如图所示，通过蚀刻去除所述导电箔13所产生的上线路层2的上导电迹线12侧壁相对于下保护层21露出的表面会由上往下呈现往内的弧形(如图12M所示，图12M为图12L中特定区域的局部放大图)。
参看图12K，其去除了图案化的第二干膜27。参看图12L，形成上保护层31，上保护层31围绕上线路层2的导电迹线及接垫29并覆盖其上。在某些实施例中，上保护层31可利用旋转涂布、喷射涂布或层压方式形成。参看图12N，图案化上保护层31，以形成开口33，界定上线路层2中欲形成接垫或指部的位置，其中部分指部位置对应于下线路层的导电迹线。图案化过程可通过微影方法达成。参看图12O，更可形成导电层35(例如，镍/金)于接垫上，以利后续打线。导电层可通过浸渍、电镀、化学镀、印刷或其它方式形成于上保护层31的开口。
参看图12P，裸片3可通过底胶9附着于上线路层2上，并可通过焊线7与上线路层2的导电层35电性连接。参看图12Q，利用封装材料5包覆裸片3。参看图12R，焊球11可形成于半导体封装14的下线路层1的开口(接垫)处，以供外部连接。
上述实施例仅为说明本发明的原理及功效，而非用以限制本发明。因此，所属领域的技术人员对上述实施例进行修改及变化仍不脱本发明的精神。
根据以上本发明的说明可知，本发明将一层电路拆成两层实施方案，由此可改进线路蚀刻的良率，且也可缩小相邻线路间的间距。
此外，因本发明的衬底具备上下布线的能力，其具有更多线路设计上的弹性。

Claims (26)

1.一种衬底，其包括上线路层及下线路层，所述上线路层包括至少一导电迹线及至少一接垫，所述下线路层包括至少一导电迹线及至少一接垫，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线的最小距离并非零。
2.根据权利要求1所述的衬底，所述上线路层的所述至少一导电迹线具有上表面及下表面，所述下线路层的所述至少一导电迹线具有上表面及下表面，所述上线路层的所述至少一导电迹线的所述下表面与所述下线路层的所述至少一导电迹线的所述下表面实质上位于同一平面。
3.根据权利要求1所述的衬底，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线间隔排列。
4.根据权利要求1所述的衬底，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线位于所述下线路层的两个相邻接垫之间。
5.根据权利要求1所述的衬底，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线位于所述上线路层或所述下线路层的两个导电迹线之间。
6.根据权利要求1所述的衬底，其中所述上线路层的所述接垫为指部，所述指部与所述下线路层的导电迹线重叠。
7.根据权利要求1所述的衬底，其中所述下线路层的所述接垫为球垫，所述上线路层的导电迹线与所述球垫重叠。
8.根据权利要求1所述的衬底，其中所述上线路层的导电迹线的侧壁轮廓呈现往内的弧形，且所述下线路层的导电迹线的侧壁轮廓呈现往内的弧形。
9.根据权利要求1所述的衬底，其进一步包括保护层，其围绕且覆盖所述上线路层及所述下线路层的导电迹线。
10.根据权利要求1所述的衬底，其进一步包括加强层，其位于所述上线路层的所述接垫下方。
11.一种半导体封装，其包括：
衬底，所述衬底包括上线路层及下线路层，所述上线路层包括至少一导电迹线及至少一接垫，所述下线路层包括至少一导电迹线及至少一接垫，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线的最小距离并非零；以及
裸片，其电性连接于所述上线路层。
12.根据权利要求11所述的半导体封装，所述上线路层的所述至少一导电迹线具有上表面及下表面，所述下线路层的所述至少一导电迹线具有上表面及下表面，所述上线路层的所述至少一导电迹线的所述下表面与所述下线路层的所述至少一导电迹线的所述下表面实质上位于同一平面。
13.根据权利要求11所述的半导体封装，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线间隔排列。
14.根据权利要求11所述的半导体封装，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线位于所述下线路层的两个相邻接垫之间。
15.根据权利要求11所述的半导体封装，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线位于所述上线路层或所述下线路层的两个导电迹线之间。
16.根据权利要求11所述的半导体封装，其中所述上线路层的所述接垫为指部，所述指部与所述下线路层的导电迹线重叠。
17.根据权利要求11所述的半导体封装，其中所述下线路层的所述接垫为球垫，所述上线路层的导电迹线与所述球垫重叠。
18.根据权利要求11所述的半导体封装，其中所述上线路层的导电迹线的侧壁轮廓呈现往内的弧形，且所述下线路层的导电迹线的侧壁轮廓呈现往内的弧形。
19.根据权利要求11所述的半导体封装，其进一步包括保护层，其围绕且覆盖所述上线路层及所述下线路层的导电迹线。
20.根据权利要求11所述的半导体封装，其进一步包括加强层，其位于所述上线路层的所述接垫下方。
21.一种制造衬底的方法，其包括：
提供导电箔，所述导电箔包括第一表面及第二表面；
图案化所述第一表面以形成至少一第一导电迹线及第一接垫；以及
图案化所述第二表面以形成至少一第二导电迹线及第二接垫。
22.根据权利要求21所述的制造衬底的方法，其中所述上线路层的所述至少一导电迹线与所述下线路层的所述至少一导电迹线的最小距离并非零。
23.根据权利要求21所述的制造衬底的方法，其中在图案化所述第一表面与图案化所述第二表面的步骤之间，进一步包括形成围绕且覆盖所述至少一第一导电迹线的第一保护层的步骤。
24.根据权利要求23所述的制造衬底的方法，其中在形成所述第一保护层的步骤之后，进一步包括形成开口于所述第一保护层以露出所述第一接垫的步骤。
25.根据权利要求21所述的制造衬底的方法，其中在图案化所述第二表面的步骤之后，进一步包括形成围绕且覆盖所述至少一第二导电迹线的第二保护层的步骤。
26.根据权利要求24所述的制造衬底的方法，其中在形成所述第二保护层的步骤之后，进一步包括形成开口于所述第二保护层以露出所述第二接垫的步骤。
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