CN105097565B - The forming method of encapsulating structure - Google Patents

The forming method of encapsulating structure Download PDF

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Publication number
CN105097565B
CN105097565B CN201510373719.4A CN201510373719A CN105097565B CN 105097565 B CN105097565 B CN 105097565B CN 201510373719 A CN201510373719 A CN 201510373719A CN 105097565 B CN105097565 B CN 105097565B
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connecting key
chip
carrier
layer
encapsulating structure
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CN105097565A (en
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石磊
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

A kind of forming method of encapsulating structure, including：Carrier is provided；In carrier surface fixed chip, chip has relative first surface and second surface, and the second surface of chip includes functional areas, and first surface and the carrier surface of chip interfix；Key is fixedly connected with the carrier surface of chip circumference, connecting key includes conductor wire, connecting key includes exposing first end and the second end of conductor wire, and first end and the carrier surface of connecting key interfix, and the second end of connecting key is higher than or be flush to the functional areas surface of chip；Plastic packaging layer is formed in carrier surface, plastic packaging layer surrounds chip and connecting key, the surface of plastic packaging layer expose the second end of connecting key and the functional areas surface of chip；The wiring layer again electrically connected with the second end of connecting key and the functional areas of chip is formed in plastic packaging layer surface；The first soldered ball is formed connecting up layer surface again；Carrier is removed afterwards.The forming method of the encapsulating structure is simple, process costs reduce, the encapsulating structure accurate size of formation and diminution.

Description

The forming method of encapsulating structure
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of encapsulating structure.
Background technology
In the prior art, chip is that the side of (Wire Bonding) is bonded by metal lead wire with the connection of external circuit Formula realization, i.e. Wire Bonding Technology.As the feature size downsizing of chip and the integrated level of integrated circuit improve, wire bonding skill The art no longer growth requirement of applicable technology.
In order to improve the integrated level of chip package, Stacked Die Packaging (stacked die package) technology gradually into For the main flow of technology development.Stacked Die Packaging technology, also known as three-dimensional packaging technology, specifically stacked in same packaging body The encapsulation technology of at least two chips.Stacked Die Packaging technology can realize the Large Copacity of semiconductor devices, multi-functional, small chi The technical need such as very little, inexpensive, therefore laminated chips technology is flourished in recent years.
By taking the memory using stacked package technology as an example, compared to the memory for not using Stack Technology, using heap The memory of folded encapsulation technology can possess more than twice of memory capacity.In addition, more can be effective using stacked package technology Ground utilizes the area, USB flash disk, SD card more applied to big memory space etc. of chip.
Stacked chips encapsulation technology can be realized by multiple technologies means, such as routing technique, silicon hole (through silicon via, abbreviation TSV) technology or plastic packaging through hole (through molding via, abbreviation TMV) skill Art.
However, above-mentioned technological means still faces various technique limitations and cost limitation, further subtract moreover, being faced with The problem of thin encapsulating structure thickness.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of encapsulating structure, the forming method letter of the encapsulating structure Single, process costs reduce, the encapsulating structure accurate size formed and diminution.
To solve the above problems, the present invention also provides a kind of forming method of encapsulating structure, including：Carrier is provided；Institute Carrier surface fixed chip is stated, the chip has relative first surface and second surface, the second surface bag of the chip Functional areas are included, first surface and the carrier surface of the chip interfix；Fix and connect in the carrier surface of the chip circumference Key is connect, the connecting key includes conductor wire, and the connecting key includes first end and the second end, the first end of the connecting key and Two ends expose the conductor wire, and the first end of the connecting key interfixes with the carrier surface, and the of the connecting key Two ends are higher than or are flush to the functional areas surface of the chip；Plastic packaging layer is formed in the carrier surface, the plastic packaging layer surrounds The chip and connecting key, the surface of the plastic packaging layer expose the second end of the connecting key and the functional areas surface of chip； Wiring layer again, the wiring layer again and the second end of the connecting key and the functional areas of chip are formed in the plastic packaging layer surface Electrical connection；The first soldered ball is formed in the layer surface that connects up again；After first soldered ball is formed, the carrier is removed, cruelly Expose the first end of the connecting key.
Optionally, the connecting key also includes the protective layer positioned at the conductor wire sidewall surfaces, the protective layer exposure Go out the conductor wire at the connecting key first end and the second end.
Optionally, the forming step of the connecting key includes：Initial conduction line is provided, the initial conduction line has the 3rd End and the 4th end；Initial protective layers are formed in the sidewall surfaces of the initial conduction line, form initial connecting key, the initial guarantor Sheath exposes the 3rd end and the 4th end of the initial conduction line；Cut along perpendicular to the direction of the initial conduction line side wall The initial protective layers and initial conduction line, form some sections of conductor wires and the protective layer positioned at conductor wire sidewall surfaces.
Optionally, the formation process of the initial protective layers include chemical vapor deposition method, physical gas-phase deposition, Atom layer deposition process, spraying coating process or Shooting Technique.
Optionally, from the direction at the 3rd end to the 4th end of the initial conduction line, if the initial connecting key has Dry cut length, each cut length are respectively provided with close to the 5th end at the 3rd end and close to the 6th end at the 4th end；The cut length The initial protective layers thickness at five ends is more than the initial protective layers thickness at the end of cut length the 6th；Cut the initial connecting key it Afterwards, some cut length are separate, and each cut length forms the connecting key, and the 5th end of the cut length turns into connecting key First end, the 6th end of the cut length turn into the second end of connecting key.
Optionally, the forming step of the initial protective layers includes：Using coating process on the initial conduction line surface Form diaphragm；It is moulding to diaphragm progress using mould, form the initial protective layers.
Optionally, the material of the protective layer is insulating materials.
Optionally, the insulating materials is organic insulation or inorganic insulating material；The organic insulation includes Polyvinyl chloride；The inorganic insulating material includes the one or more in silica, silicon nitride and silicon oxynitride.
Optionally, the first end size of the connecting key is more than the second end size of the connecting key.
Optionally, the first end size of the connecting key is identical with the second end size.
Optionally, the connecting key first end to the second end distance be 40 microns~400 microns.
Optionally, the conductive linear dimension of the connecting key first end and the conductive linear dimension at the second end are identical.
Optionally, the material of the conductor wire is copper, tungsten, aluminium, gold or silver.
Optionally, the first surface of the chip is fixed on the carrier surface by tack coat；The of the connecting key The carrier surface is fixed in one end by tack coat.
Optionally, the functional areas surface of the chip exposes pad；The bond pad surface has projection, the projection Top surface protrudes from the second surface of the chip；The plastic packaging layer exposes the top surface of the projection, the projection Top surface be the chip functional areas surface.
Optionally, in addition to：Before the wiring layer again is formed, in the plastic packaging layer surface the first insulating barrier of formation, If with the conductor wire and chip functions area surface for exposing the end of connecting key second respectively in first insulating barrier Dry first through hole；In the first through hole and the surface of insulating layer of part first forms the wiring layer again.
Optionally, in addition to：Before the soldered ball is formed, the second insulating barrier, institute are formed in the layer surface that connects up again Stating has the second through hole for exposing partly again wiring layer in the second insulating barrier；First weldering is formed in second through hole Ball.
Optionally, in addition to：After the carrier is removed, the is formed on the conductor wire surface of the connecting key first end Two soldered balls.
Optionally, in addition to：Packaging body is provided, the packaging body has the 3rd surface, the 3rd surface of the packaging body Expose conductive structure；Make the first surface of the chip and plastic packaging layer surface is relative with the 3rd surface of the packaging body sets Put, and second soldered ball is connected with each other with the conductive structure by welding procedure.
Compared with prior art, technical scheme has advantages below：
It is direct in the carrier surface of chip circumference before plastic packaging layer is formed in the forming method of encapsulating structure of the present invention It is fixedly connected with key.The connecting key includes conductor wire, and the first end of the connecting key and the second end expose conductor wire；By After the first end of the connecting key is fixed on into carrier surface, the second end of the connecting key can be higher than or be flush to described The functional surfaces of chip, therefore, after the carrier surface forms and exposes the plastic packaging floor in chip functions area, the connecting key Second end can also be higher than or be flush to the plastic packaging layer surface, so as to which the conductor wire can pass through from the plastic packaging layer surface Wear to carrier surface, so as to the electrical connection of follow-up chip first surface to second surface.Because the connecting key is directly fixed on Carrier surface, the step of being handled in plastic packaging layer is avoided, can simplify the forming method of encapsulating structure.Moreover, institute State connecting key and be directly fixed on carrier surface, the connecting key can be made more accurate relative to the position of the chip and be easy to Regulation and control, not only contribute to ensure the accurate size of formed encapsulating structure, and be advantageous to the wiring layer again that is subsequently formed with Realize electrical connection in second end of the connecting key.Therefore, the forming method processing step simplification of the encapsulating structure, process costs Reduce, technology difficulty reduction, and the size of the encapsulating structure formed is more accurate, is advantageous to reduce the chi of encapsulating structure It is very little.
Further, the connecting key also includes the protective layer positioned at the conductor wire sidewall surfaces.The protective layer is not only The conductor wire can be protected when carrier surface is fixedly connected with key, additionally it is possible to so that the cross sectional dimensions increase of connecting key, makes Obtain the connecting key to be easier to be aligned when being fixed on carrier surface, advantageously ensure that position of the connecting key relative to chip Accurately.
Further, the first end size of the connecting key is more than the second end size of the connecting key.Due to the connection Carrier surface is fixed at second end of key, and the first end size of the connecting key is larger, is advantageous to carrying the connecting key The fixation in body surface face is more stable, can avoid during plastic packaging layer is formed, the connecting key is subjected to displacement, so as to ensure Relative position between connecting key and chip is accurate.
Brief description of the drawings
Fig. 1 is that through-silicon via structure is introduced in encapsulating structure to realize the cross-sectional view of chip chamber conducting；
Fig. 2 is that plastic packaging through-hole structure is introduced in encapsulating structure to realize the cross-sectional view of chip chamber conducting；
Fig. 3 to Figure 16 is the cross-sectional view of the forming process of the encapsulating structure of one embodiment of the invention；
Figure 17 to Figure 20 is the cross-sectional view of the forming process of the encapsulating structure of another embodiment of the present invention.
Embodiment
As stated in the Background Art, existing stacked chips encapsulation technology faces technique limitation and cost limitation, for technology Popularization and application cause limitation, moreover, stacked chips encapsulation technology is also faced with that encapsulating structure thickness is further being thinned The problem of, to further improve the integrated level of chip, reduce size.
Stacked chips encapsulation technology can pass through silicon hole (through silicon via, abbreviation TSV) technology or plastic packaging Through hole (through molding via, abbreviation TMV) technology is realized.However, either silicon hole technology or plastic packaging through hole Technology, it is respectively provided with certain defect.
Fig. 1 is refer to, Fig. 1 is that through-silicon via structure is introduced in encapsulating structure to realize that the cross-section structure of chip chamber conducting shows It is intended to, including：Carrier 100；The chip 101 on the surface of carrier 100 is fixed on, the chip 101 includes relative non-functional face 102 And functional surfaces 103, the non-functional face 102 of the chip 101 are in contact with the surface of carrier 100, the functional surfaces of the chip 101 103 surfaces have pad 104；Through the conductive plunger 105 of the chip 101, one end and the weldering of the conductive plunger 105 Disk 104 electrically connects；Plastic packaging layer 106 positioned at the surface of carrier 100, the plastic packaging layer 106 surround the chip 101, and institute State plastic packaging layer 106 and expose the pad 104；Positioned at wiring layer 107 again on the surface of plastic packaging layer 106, the wiring layer again 107 electrically connect with the pad 104；Soldered ball 108 positioned at the surface of wiring layer again 107.
Wherein, the conductive plunger 105 is generally formed before cutting forms independent chip 101；The conductive plunger 105 forming step includes：Substrate is provided, the substrate has functional surfaces, and the substrate includes some chip regions；Using quarter Etching technique forms through hole in the chip region of the substrate from the functional surfaces；Formed in the side wall and lower surface of the through hole Insulating barrier (does not indicate)；Surface of insulating layer in the through hole forms conductive plunger 105；It is relative with functional surfaces from the substrate Surface is polished, until exposing an end position of the conductive plunger 105；After the glossing, described in cutting Substrate, some chip regions are made to form independent chip 101.
However, it is necessary to form through hole in substrate during the conductive plunger 105 is formed, and the through hole Depth is the thickness of chip 101 that is formed, therefore the depth of the through hole is deeper, and the depth-to-width ratio of the through hole is higher, therefore, right Form that the etching technics requirement of the through hole is higher, and the difficulty of the etching technics is larger.Moreover, subsequently need in the through hole Interior filling conductive material is to form conductive plunger 105, and the depth-to-width ratio of the through hole is higher, the filling difficulty of the conductive material It is larger, it is higher for the technological requirement of formation conductive plunger 105.In addition, realize the etching technics and profundity of above-mentioned high-aspect-ratio The wide process costs than through hole filling are higher.To sum up, because the technology difficulty of through-silicon via structure is higher, technique is complex, and Process costs are higher, and being applied to stacked chips encapsulation for silicon hole technology causes limitation.
In order to reduce technology difficulty, a kind of plastic packaging through hole technology is had also been proposed.Fig. 2 is refer to, Fig. 2 is in encapsulating structure Plastic packaging through-hole structure is introduced to realize the cross-sectional view of chip chamber conducting, including：Carrier 110；It is fixed on the table of carrier 110 The chip 111 in face, the chip 111 include relative non-functional face 112 and functional surfaces 113, the chip 111 it is non-functional Face 112 is in contact with the surface of carrier 110, and the surface of functional surfaces 113 of the chip 111 has pad 114；Positioned at the carrier The plastic packaging layer 115 on 110 surfaces, the plastic packaging layer 115 surrounds the chip 111, and the plastic packaging layer 115 exposes the pad 114；Through the conductive plunger 116 of the plastic packaging layer 115；Positioned at wiring layer 117 again on the surface of plastic packaging layer 115, it is described again Wiring layer 117 electrically connects with the pad 114 and conductive plunger 116；Soldered ball 118 positioned at the surface of wiring layer again 117.
Wherein, the forming step of the conductive plunger 116 includes：Formed using etching technics in the plastic packaging layer 115 It is through to the through hole on the surface of carrier 110；Conductive plunger 116 is formed in the through hole.
However, because the thickness of the plastic packaging layer 115 is the thickness of the chip 111, and the through hole runs through the modeling Sealing 115, therefore the depth of the through hole is deeper, the depth-to-width ratio of the through hole is higher；Etching technics to forming the through hole With higher required precision, the difficulty of the etching technics is larger.Secondly as follow-up need to fill in the through hole to lead Electric material is to form conductive plunger 116, and the depth-to-width ratio of the through hole is higher, cause to fill the difficulty of the conductive material compared with Greatly.It is additionally, since the conductive plunger 116 to be formed at around the chip 111, therefore, it is necessary to is accurately set to described conductive slotting 116 positions relative to chip are filled in, it is therefore, higher for positioning accuracy request when forming the through hole.To sum up, though using Plastic packaging through hole technology realizes that stacked chips encapsulate, and is still faced with that complex process, technology difficulty are higher and cost is higher Problem.
In order to solve the above problems, the present invention provides a kind of forming method of encapsulating structure, including：Carrier is provided；Institute Carrier surface fixed chip is stated, the chip has relative first surface and second surface, the second surface bag of the chip Functional areas are included, first surface and the carrier surface of the chip interfix；Fix and connect in the carrier surface of the chip circumference Key is connect, the connecting key includes conductor wire, and the connecting key includes first end and the second end, the first end of the connecting key and Two ends expose the conductor wire, and the first end of the connecting key interfixes with the carrier surface, and the of the connecting key Two ends are higher than or are flush to the functional areas surface of the chip；Plastic packaging layer is formed in the carrier surface, the plastic packaging layer surrounds The chip and connecting key, the surface of the plastic packaging layer expose the second end of the connecting key and the functional areas surface of chip； In plastic packaging layer surface formation, wiring layer, the wiring layer again electrically connect with the second end of the connecting key and pad again； The first soldered ball is formed in the layer surface that connects up again；After first soldered ball is formed, the carrier is removed, is exposed described The first end of connecting key.
Wherein, before plastic packaging layer is formed, key is directly fixedly connected with the carrier surface of chip circumference.The connecting key bag Conductor wire is included, and the first end of the connecting key and the second end expose conductor wire；Due to by the first end of the connecting key After being fixed on carrier surface, the second end of the connecting key can be higher than or be flush to the functional surfaces of the chip, therefore, in institute State carrier surface to be formed after the plastic packaging floor for exposing chip functions area, the second end of the connecting key also can be higher than or flush In the plastic packaging layer surface, so as to which the conductor wire can be through to carrier surface from the plastic packaging layer surface, so as to follow-up core Piece first surface to second surface electrical connection.Because the connecting key is directly fixed on carrier surface, avoid in plastic packaging layer It the step of inside being handled, can simplify the forming method of encapsulating structure.Moreover, the connecting key is directly fixed on carrier table Face, the connecting key can be made more accurate relative to the position of the chip and be easy to regulate and control, not only contribute to ensure institute's shape Into encapsulating structure accurate size, and be advantageous to the wiring layer again and connecting key being subsequently formed the second end realize electricity Connection.Therefore, the forming method processing step of the encapsulating structure is simplified, process costs reduce, technology difficulty reduces, Er Qiesuo The size of the encapsulating structure of formation is more accurate, is advantageous to reduce the size of encapsulating structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Fig. 3 to Figure 16 is the cross-sectional view of the forming process of the encapsulating structure of one embodiment of the invention.
It refer to Fig. 3, there is provided carrier 200.
The carrier 200 provides workbench for subsequent technique, for the plastic packaging layer for carrying chip He being subsequently formed.
In the present embodiment, the carrier 200 is rigid substrate, and the rigid substrate is PCB substrate, glass substrate, gold Belong to substrate, semiconductor substrate or polymeric substrates.The rigid substrate has higher hardness, deformation is not susceptible to, follow-up It is enough supporting-core piece and plastic packaging layer in technique.
In other embodiments, the carrier can also be flexible base plate.
Fig. 4 is refer to, in the surface fixed chip 201 of carrier 200, the chip 201 has relative first surface 210 and second surface 220, the second surface 220 of the chip 201 includes functional areas (not shown), and the first of the chip 201 Surface 210 interfixes with the surface of carrier 200.
The first surface 210 of the chip 201 is fixed on the surface of carrier 200 by tack coat (not shown).It is described The material of tack coat is UV glue, and UV glue viscosity after ultraviolet irradiates reduces, so as to subsequently by carrier 200 from encapsulating structure Middle stripping.
In one embodiment, tack coat is adhered in the first surface 210 of the chip 201, then the tack coat is adhered to In the surface of carrier 200, to realize the bonding between chip 201 and carrier 200.And the first surface 210 of the chip 201 does not have Functional area, i.e., the first surface 210 of described chip 201 do not have electric connection structure, and the first surface 210 of chip 201 is fixed After the surface of carrier 200, the functional areas of the second surface 220 of chip 201 can be exposed.
In another embodiment, additionally it is possible to need the correspondence position of fixed chip 201 to be formed on the surface of the carrier 200 Tack coat, or tack coat is formed in the surface global of carrier 200, then the first surface 210 of the chip 201 is adhered to described Tie layer surface, chip 201 is set to be fixed on the surface of carrier 200.
In the present embodiment, the surface global of carrier 200 covers the tack coat.
The chip 201 can be sensor chip, logic circuit chip, storage chip etc..The table of chip 201 second Can have transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, sensing in the functional areas in face 220 One or more of device, electric interconnection structure.
The forming step of the chip 201 includes：Substrate is provided, the substrate has some chip regions, the substrate bag Relative first surface and second surface are included, there are functional areas in the chip region of the substrate second surface；The substrate is entered Row cutting, is separated from each other some chip regions, forms independent chip 201.
In the present embodiment, the functional areas surface of the chip 201 exposes pad；The bond pad surface has projection 221, the top surface of the projection 221 protrudes from the second surface 220 of the chip 201, the top surface of the projection 221 The functional areas surface of i.e. described chip 201.The material of the projection 221 includes copper, gold or tin, and the projection 221 has default Thickness.The projection 221 can be realized with the circuit in functional areas or device and electrically connected.The projection 221 is used for subsequently setting The connecting key electrical connection put, so as to realize the electrical connection between the functional areas of chip 201 and other chips or external circuit.At this In embodiment, the functional areas surface of the chip 201 is the top surface of the projection 221.In other embodiments, the work( Energy area can also be sensor region, have sensor in the sensor region, and the sensor is used to obtain external environment condition In information.
Fig. 5 is refer to, the surface of carrier 200 around the chip 201 is fixedly connected with key 203, and the connecting key 203 wraps Conductor wire 230 is included, the connecting key 230 includes the end 232 of first end 231 and second, the He of first end 231 of the connecting key 203 Second end 232 exposes the conductor wire 230, and the first end 231 of the connecting key 203 and the surface of carrier 200 are mutually solid Fixed, the second end 232 of the connecting key 203 is higher than or is flush to the functional areas surface of the chip 201.
The first end 231 of the connecting key 203 is fixed on the surface of carrier 200 by tack coat.The tack coat Material is UV glue, and UV glue viscosity after ultraviolet irradiates reduces, subsequently to peel off carrier 200 from encapsulating structure.
In one embodiment, in the surface adhesion tack coat of first end 231 of the connecting key 203, then by the tack coat The surface of carrier 200 is adhered to, to realize the bonding between connecting key 203 and carrier 200.
In another embodiment, additionally it is possible to need to be fixedly connected with the correspondence position shape of key 203 on the surface of the carrier 200 Tack coat is covered into tack coat, or in the surface global of carrier 200, then the first surface 210 of the connecting key 203 is adhered to The tie layer surface, connecting key 203 is set to be fixed on the surface of carrier 200.
In the present embodiment, the functional areas surface of the chip 201 is the top surface of the projection 221, and in carrier 200 surfaces are fixedly connected after the first end 231 of key 203, and the surface of the second end 232 of connecting key 203 is higher than or is flush to described The functional areas surface of chip 201, i.e., the surface of the second end 232 of described connecting key 203 are higher than or are flush to the top of the projection 221 Portion surface.
The surface of carrier 200 around a chip 201, fixes one or several connecting keys 203.When a chip When the quantity of connecting key 203 around 201 is more than 1, the quantity of the connecting key 203 can count with the projection 221 on the surface of chip 201 Amount is consistent, and the position of the connecting key 203 is corresponding with the position of projection 221 on the surface of chip 201.
The end 232 of first end 231 and second of the connecting key 203 exposes conductor wire 230, by the connecting key 203 First end 231 and the surface of carrier 200 interfix after, i.e., conduction that the described first end 231 of connecting key 203 exposes Line 230 interfixes with the surface of carrier 200, and the surface of conductor wire 230 that second end 232 exposes is higher than or flushed In the top surface of the projection 221.Subsequently after plastic packaging layer surface forms wiring layer again, the wiring layer again can be realized Electrical connection between conductor wire 230 and projection 221 that second end 232 exposes, so that projection 221 arrives the table of carrier 200 Face can realize electrical connection.
Because the connecting key 203 is directly fixed on the surface of carrier 200, avoid be subsequently formed plastic packaging layer and then The step of carrying out routing technique or forming plastic packaging through-hole structure, can simplify processing step, and reduce technology difficulty, so as to Cost can be reduced.Moreover, the connecting key 203 is directly fixed on the surface of carrier 200 so that the connecting key 203 relative to The position of chip 201 is more accurate, avoids during plastic packaging through-hole structure is formed, caused error during etching through hole Problem.In addition, the second end 232 of the connecting key 203 is higher than or is flush to the top surface of the projection 221, then follow-up shape Into the surface of plastic packaging layer can be flush to the bond pad surface；Compared in routing technique, plastic packaging layer surface needs to be higher than core The problem of piece surface, the modeling seal coat thickness that the present embodiment is subsequently formed is relatively thin, is advantageous to the thickness of thinned formed encapsulating structure Spend size.
In the present embodiment, the distance at 231 to the second end of first end 232 of connecting key 203 is 40 microns~400 micro- Rice；The distance at 231 to the second end of first end 232 of connecting key 203 is more than or equal to the thickness of the chip 201, the core The thickness of piece 201 is distance of the top surface of projection 221 to the first surface 210 of chip 201.Thus, it is possible to ensure rear Continuous to be formed after plastic packaging layer, the plastic packaging layer surface can flush with the top surface of projection 221, while the plastic packaging layer can be sudden and violent Expose the second end 232 of connecting key 203.
The material of the conductor wire 230 is conductive material, and the conductor wire 230 is used to realize chip 201 from first surface 210 to second surface 220 conducting；It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the connecting key 203 also includes the protective layer 233 positioned at the sidewall surfaces of conductor wire 230, The protective layer 233 exposes the conductor wire 230 at the first end 231 of connecting key 203 and the second end 232.
In another embodiment, the connecting key can not also include the protective layer, and only have the conductor wire.
The material of the protective layer 233 is insulating materials.The insulating materials is organic insulation or inorganic insulation material Material；The organic insulation includes polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzo Cyclobutane resin or polybenzoxazoles resin；The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride Kind is a variety of.
The protective layer 233 can not only be when being fixed on 200 surface of carrier, for protecting described lead by connecting key 203 The surface of electric wire 230 can increase the sectional dimension of the connecting key 203 from damage, so as to consolidate by connecting key 203 Determine with being more easy to be aligned during 200 surface of carrier, so that being fixed on the connecting key 203 on the surface of carrier 200 relative to the position of chip 201 Put more accurate.
In the present embodiment, the size of first end 231 of the connecting key 203 is identical with the size of the second end 232.The connection The size of conductor wire 230 of the first end 231 of key 203 is identical with the size of conductor wire 230 at the second end 232.Wherein, the conductor wire 230 a diameter of 30 microns~150 microns, the thickness of the protective layer 233 is 10 nanometers~10 microns；When the conductor wire 230 Material when being copper, the minimum diameter of the conductor wire 230 is 30 microns；It is described when the material of the conductor wire 230 is aluminium The minimum diameter of conductor wire 230 is 100 microns.
In the present embodiment, the conductor wire 230 is cylinder, i.e., the section of described conductor wire 230 is circular, the company The end 232 of first end 231 and second for connecing key 203 exposes the cylindrical both ends of conductor wire 230 respectively；The connecting key 203 first ends 231 and the size of conductor wire 230 at the second end 232 are the diameter of the cylindrical conductive line 230.
In the present embodiment, the cylindrical conductor wire 230 is from the diameter of 203 first end of connecting key, 231 to the second end 232 It is identical.
In the present embodiment, the sidewall surfaces of conductor wire 230 are also covered with protective layer 233, and the protective layer 233 Thickness is homogeneous, so as to after the Surface coating protective layer 233 of conductor wire 230, the connecting key 203 from first end 231 to The size at the second end 232 is still identical.
In other embodiments, the size at the second end of the connecting key can also be less than the size of the first end.
The forming step of the connecting key is illustrated below with reference to accompanying drawing.
It refer to Fig. 6, there is provided initial conduction line 300, the initial conduction line 300 have the 3rd end 301 and the 4th end 302。
The initial conduction line 300 forms conductor wire 230 (as shown in Figure 5) for cutting.The initial conduction line 300 Material is conductive material；It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the initial conduction line 300 is cylinder, i.e., the section of described initial conduction line 300 is circle Shape；And size of the initial conduction line 300 from the end 302 of the 3rd end 301 to the 4th is identical, i.e., described cylindrical conductor wire 300 diameter from the end 302 of the 3rd end 301 to the 4th is identical.
Fig. 7 is refer to, initial protective layers 303 is formed in the sidewall surfaces of the initial conduction line 300, forms initial connection Key 310, the initial protective layers 303 expose the 3rd end 301 and the 4th end 302 of the initial conduction line 300.
The formation process of the initial protective layers 303 includes chemical vapor deposition method, physical gas-phase deposition, atom Layer depositing operation, spraying coating process or Shooting Technique.
The material of the initial protective layers 303 is insulating materials；The insulating materials is organic insulation or inorganic exhausted Edge material.
In one embodiment, when the material of the initial protective layers 303 is organic insulation, the organic insulation Including polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polyphenyl and disliked Azoles resin；The formation process of the initial protective layers 303 can be spraying coating process or Shooting Technique.
In another embodiment, the material of the initial protective layers 303 is inorganic insulating material, the inorganic insulating material Including the one or more in silica, silicon nitride and silicon oxynitride；The formation process of the initial protective layers 303 being capable of chemistry Gas-phase deposition, physical gas-phase deposition, atom layer deposition process；And the technique for forming the initial protective layers 303 needs There is good covering power and uniformity, formed initial protective layers 303 is evenly covered on described first The surface of beginning conductor wire 300.
Fig. 8 is refer to, it is described initial along being cut perpendicular to the direction of initial conduction line 300 (as shown in Figure 7) side wall Protective layer 303 (as shown in Figure 7) and initial conduction line 300 (as shown in Figure 7), form some sections of conductor wires 230 and positioned at leading The protective layer 233 of the sidewall surfaces of electric wire 230.
In the present embodiment, the sidewall surfaces of the initial conduction line 300 are around the axis A (as shown in Figure 7) Surface, the axis A are the central shaft by the 3rd end 301 and the 4th end 302 in the initial conduction line 300；Along perpendicular to The direction cutting of the side wall of initial conduction line 300 is along perpendicular to the axis A direction cutting initial protective layers 303 and just Beginning conductor wire 300.
The cutting technique can be laser cutting parameter.After cutting technique, the initial protective layers 303 and just Beginning conductor wire 300 forms some discrete connecting keys 203.
Fig. 9 is refer to, forms plastic packaging layer 204 on the surface of carrier 200, the plastic packaging layer 204 surrounds the chip 201 With connecting key 203, the surface of the plastic packaging layer 204 exposes the second end 232 and the function of chip 201 of the connecting key 203 Area surface.
In the present embodiment, the surface of the plastic packaging layer 204 and the top of projection 221 of the second surface 220 of chip 201 Surface flushes, i.e., described plastic packaging layer 204 exposes the top surface of the projection 221.Due to the second end of the connecting key 203 232 are higher than or are flush to the top surface of the projection 221, so as to make the plastic packaging layer 204 expose the connecting key 203 the second end 232.Electrical connection between connecting key 203 and projection 221 subsequently can be realized by forming again wiring layer.
The surface for being additionally, since the plastic packaging layer 204 flushes with the top surface of projection 221, the thickness of the plastic packaging layer 204 , the thinner thickness of the plastic packaging layer 204 identical with the thickness of chip 201 is spent, the thickness gauge of formed encapsulating structure can be made It is very little smaller.
In the present embodiment, the forming step of the plastic packaging layer 204 includes：Covering institute is formed on the surface of carrier 200 State the initial plastic packaging layer of the projection 221 on chip 201 and chip 201；The initial plastic packaging layer is polished, until exposure Untill the top surface for going out the projection 221, the plastic packaging layer 204 is formed.
The plastic packaging layer 204 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, the plastic packaging layer 204 is photosensitive dry film, and the formation process of the initial plastic packaging layer is pasted for vacuum Membrane process.
In another implementation, the material of the plastic packaging layer 204 is capsulation material, the capsulation material include epoxy resin, It is polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, makrolon, poly- to benzene Naphthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, second Alkene-acetate ethylene copolymer, polyvinyl alcohol or other suitable polymeric materials.
The formation process of the initial plastic packaging layer includes Shooting Technique (injection molding), turns modeling technique (transfer molding) or silk-screen printing technique.The Shooting Technique includes：Mould is provided；Filling modeling in the mold Closure material, the capsulation material is set to coat the chip 201 and connecting key 203；Elevated cure, shape are carried out to the capsulation material Into plastic packaging layer 204.
In other embodiments, the material of the plastic packaging layer 204 can also be other insulating materials.
Subsequently formed on the surface of plastic packaging layer 204 and electrically connected with the end 232 of connecting key 203 second and projection 221 Wiring layer again.In one embodiment, the wiring layer again can be formed directly into the surface of plastic packaging layer 204.In this implementation In example, the first insulating barrier can be formed on the surface of plastic packaging layer 204 and then is connected up again in the formation of the first surface of insulating layer Layer；Illustrated below with reference to accompanying drawing.
Figure 10 is refer to, the first insulating barrier 205 is formed on the surface of plastic packaging layer 204, is had in first insulating barrier 205 Have some the first of the conductor wire 230 for exposing the end 232 of connecting key 203 second respectively and the functional areas surface of chip 201 Through hole 206.
First insulating barrier 205 is used to protect the surface of plastic packaging layer 204；First in first insulating barrier 205 The wiring layer again that through hole 206 is used to enable to be subsequently formed electrically connects with conductor wire 230 and projection 221.
The forming step of first insulating barrier 205 includes：In the plastic packaging layer 204, connecting key 203 and the table of projection 221 Face forms the first dielectric film；First dielectric film is patterned, forms the first insulating barrier 205, and first insulation There is first through hole 206 in layer 205.
In one embodiment, the material of first insulating barrier 205 is polymeric material or inorganic insulating material；It is described poly- Compound material can be insulating resin；The inorganic insulating material can be silica, silicon nitride, one kind in silicon oxynitride or Multiple combinations.
The technique being patterned to first dielectric film includes：Using coating process and exposure imaging technique first Insulating film surface forms patterned photoresist layer；First dielectric film is etched with the photoresist layer.
The technique for etching first dielectric film is anisotropic dry etch process；The anisotropic dry method is carved The etching gas of etching technique include CH4、CHF3、CH3One or more in F, bias power are more than 100 watts, and bias voltage is more than 10 volts.
In another embodiment, the material of the first insulating barrier 205 is photoresist, and the first through hole 206 uses photoetching work Skill is formed.
Figure 11 is refer to, in the first through hole 206 (as shown in Figure 10) and the surface shape of the first insulating barrier of part 205 Into wiring layer 207 again, the wiring layer again 207 electrically connects with the second end 232 of the connecting key 203 and projection 221.
The forming step of described wiring layer again 207 includes：In the first through hole 206 and the first insulating barrier 205 Surface forms conducting film, the full first through hole 206 of conducting film filling；Planarize the conducting film；In flatening process Afterwards, patterned layer, the patterned layer covering part conducting film are formed on the conducting film surface；Using the patterned layer as Mask, the conducting film is etched, untill the surface of the first insulating barrier 205 is exposed；After the conducting film is etched, remove The patterned layer.
The material of the conducting film includes the one or more in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver；Carve The technique for losing the conducting film is anisotropic dry etch process or wet processing；The patterned layer can be figure The photoresist layer of change, additionally it is possible to be patterned hard mask, the material of the hard mask is silica, silicon nitride, silicon oxynitride In one kind or it is a variety of；The flatening process can be CMP process.
The wiring layer again 207 can be single layer structure or sandwich construction, the cloth again of the single layer structure or sandwich construction Line layer 207 is used to realize specific circuit function.In the present embodiment, the wiring layer again 207 is single layer structure.In other realities Apply in example, the wiring layer again can be sandwich construction, and be electrically isolated between adjacent two layers wiring layer with insulating barrier.
Figure 12 is refer to, in the second insulating barrier 208 of the surface of wiring layer again 207 formation, second insulating barrier 208 With the second through hole 280 for exposing partly again wiring layer 207.
Second insulating barrier 208 is solder mask, and second insulating barrier 208 is used for described in protective layer in wiring layer 207, And the second through hole 280 in second insulating barrier 208 is used for the position for the first soldered ball that definition is subsequently formed.
The forming step of second insulating barrier 208 includes：Formed on the surface of 207 and first insulating barrier of wiring layer 205 again Second dielectric film；Second dielectric film is patterned, forms the second insulating barrier 208, and in second insulating barrier 208 With second through hole 280.
In one embodiment, the material of second insulating barrier 208 is polymeric material or inorganic insulating material；It is described poly- Compound material can be insulating resin；The inorganic insulating material can be silica, silicon nitride, one kind in silicon oxynitride or Multiple combinations.
The technique being patterned to second dielectric film includes：Using coating process and exposure imaging technique second Insulating film surface forms patterned photoresist layer；First dielectric film is etched with the photoresist layer.
The technique for etching second dielectric film is anisotropic dry etch process；The anisotropic dry method is carved The etching gas of etching technique include CH4、CHF3、CH3One or more in F, bias power are more than 100 watts, and bias voltage is more than 10 volts.
In another embodiment, the material of the second insulating barrier 208 is photoresist, and second through hole 208 uses photoetching work Skill is formed.
Figure 13 is refer to, first soldered ball 281 is formed in second through hole 280 (as shown in figure 12).
The material of first soldered ball 281 includes tin.The forming step of first soldered ball 281 includes：Described second The surface printing tin cream of wiring layer again 207 of the bottom of through hole 280, then high temperature reflux is carried out, under surface tension effects, form first Soldered ball 281.
In another embodiment, additionally it is possible to which first the surface printing of wiring layer 207 helps weldering to the electricity in the bottom of two through hole 280 again Agent and soldered ball particle, then high temperature reflux form the first soldered ball 281.In other embodiments, additionally it is possible in wiring layer 207 again Upper electrotinning post, then high temperature reflux form the first soldered ball 281.
In one embodiment, between the wiring layer again 207 and first soldered ball 281, additionally it is possible to which there is gold under ball Belong to structure (Under Ball Metal, abbreviation UBM)；Metal structure can include single metal layer or multiple-layer overlapped under the ball Metal level；The material of the single metal layer or more metal layers includes the one or more in copper, aluminium, nickel, cobalt, titanium, tantalum Combination.
Figure 14 is refer to, after first soldered ball 281 is formed, removes the carrier 200 (as shown in figure 13), exposure Go out the first end 231 of the connecting key 203.
In the present embodiment, the surface global of the carrier 200 covering tack coat, and the material of the tack coat is UV glue, The chip 201 and connecting key 203 are fixed by the tack coat and the carrier 200, and the plastic packaging layer 204 is formed at institute State tie layer surface.By carrying out ultraviolet light to the tack coat, make the viscosity reduction of tack coat；Again by the carrier 200 from the first surface 210 of chip 201, the first end 231 of connecting key 203 and the sur-face peeling of plastic packaging layer 204, so as to expose The first end 231 of the first surface 210 of chip 201 and connecting key 203.After the carrier 200 is peeled off, carry out cleaning with Remove the tack coat of residual.
In other embodiments, additionally it is possible to which the carrier 200 is removed by etching technics or CMP process.
Figure 15 is refer to, after the carrier 200 (as shown in figure 13) is removed, in the first end 231 of connecting key 203 The surface of conductor wire 230 formed the second soldered ball 209.
Formed after second soldered ball 209, that is, realize the two-sided plant ball of formed encapsulating structure, the encapsulating structure Both side surface can realize stacked package with other packaging bodies.
The material of second soldered ball 209 includes tin.The forming step of second soldered ball 209 includes：In the connection The surface printing tin cream of conductor wire 230 of the first end 231 of key 203, then carry out high temperature reflux, under surface tension effects, form the Two soldered balls 209.
In another embodiment, additionally it is possible to first helped in the surface printing of conductor wire 230 of the first end 231 of connecting key 203 Solder flux and soldered ball particle, then high temperature reflux form the second soldered ball 209.In other embodiments, additionally it is possible in the connecting key 203 The electroplating surface tin post of conductor wire 230 of first end 231, then high temperature reflux form the second soldered ball 209.
In another embodiment, Figure 16 is refer to, after the second soldered ball 209 is formed, in addition to：Packaging body 400 is provided, The packaging body 400 has the 3rd surface 401, and the 3rd surface 401 of the packaging body 400 exposes conductive structure 402；Make institute The first surface 210 and the surface of plastic packaging layer 204 and the 3rd surface 401 of the packaging body 400 for stating chip 201 are oppositely arranged, and Second soldered ball 209 is set to be connected with each other with the conductive structure 402 by welding procedure.
There is chip or semiconductor devices, and the chip or semiconductor devices and the conduction in the packaging body 400 Structure electrically connects.Because the conductive structure 402 is electrically connected by the second soldered ball 209 and connecting key 203 with chip 201, so as to It can realize that the chip in packaging body 400 or semiconductor devices electrically connect with the chip 201, stacked chips encapsulation is formed with this Structure, and that formed is packaging body stacked structure (Package On Package, abbreviation POP).
To sum up, in the present embodiment, before plastic packaging layer is formed, key is directly fixedly connected with the carrier surface of chip circumference. Wherein, the connecting key includes conductor wire, and the first end of the connecting key and the second end expose conductor wire；By by institute After first end fixation and the carrier surface of stating connecting key, the second end of the connecting key can be higher than or be flush to the chip Functional surfaces, therefore, after the carrier surface forms and exposes the plastic packaging floor in chip functions area, the second end of the connecting key Also it can be higher than or be flush to the plastic packaging layer surface, so as to which the conductor wire can be through to load from the plastic packaging layer surface Body surface face, so as to the electrical connection of follow-up chip first surface to second surface.Because the connecting key is directly fixed on carrier table Face, the step of being handled in plastic packaging layer is avoided, can simplify the forming method of encapsulating structure.Moreover, the connection Key is directly fixed on carrier surface, and the connecting key can be made more accurate relative to the position of the chip and be easy to regulate and control, Not only contribute to ensure the accurate size of formed encapsulating structure, and be advantageous to the wiring layer again that is subsequently formed and the company Realize electrical connection in the second end for connecing key.Therefore, the forming method processing step of the encapsulating structure is simplified, process costs reduce, Technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is advantageous to reduce the size of encapsulating structure.
Figure 17 to Figure 20 is the cross-sectional view of the forming process of the encapsulating structure of another embodiment of the present invention.
It refer to Figure 17, there is provided carrier 500；In the surface fixed chip 501 of carrier 500, the chip 501 has phase To first surface 510 and second surface 520, the second surface 520 of the chip 501 includes functional areas (not shown), described The first surface 510 of chip 501 interfixes with the surface of carrier 500；The surface of carrier 500 around the chip 501 is fixed Connecting key 503, the connecting key 503 include conductor wire 530, and the connecting key 530 includes the end 532 of first end 531 and second, institute The end 532 of first end 531 and second for stating connecting key 503 exposes the conductor wire 530, the first end 531 of the connecting key 503 Interfixed with the surface of carrier 500, the second end 532 of the connecting key 503 is higher than or be flush to the work(of the chip 501 Can area surface.
The carrier 500, the chip 501, in the technique of the surface fixed chip 501 of carrier 500 and in carrier 500 The technique that surface is fixedly connected with key 503 is identical with the related content of previous embodiment, will not be described here.
In the present embodiment, the connecting key 503 also includes the protective layer 533 positioned at the sidewall surfaces of conductor wire 530, The protective layer 533 exposes the conductor wire 530 at the first end 531 of connecting key 503 and the second end 532.
The material of the protective layer 533 is insulating materials.The insulating materials is organic insulation or inorganic insulation material Material；The organic insulation includes polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzo Cyclobutane resin or polybenzoxazoles resin；The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride Kind is a variety of.
In the present embodiment, the size of first end 531 of the connecting key 503 is more than the second end 532 of the connecting key 503 Size.Moreover, the side wall of the connecting key 503 tilts relative to the surface of the first end 531 of connecting key 503, the connecting key Acute angle between 503 sidewall surfaces and the surface of the first end 531 is 75 °~89 °.
In the present embodiment, the conductor wire 530 is cylinder, i.e., the section of described conductor wire 530 is circular, the company The end 532 of first end 531 and second for connecing key 503 exposes the cylindrical both ends of conductor wire 530 respectively；The connecting key 503 first ends 531 and the size of conductor wire 530 at the second end 532 are the diameter of the cylindrical conductive line 530.
In the present embodiment, the cylindrical conductor wire 530 is from the diameter phase of 503 first end of connecting key, 531 to the second end 532 Together.
In the present embodiment, the sidewall surfaces of conductor wire 530 are also covered with protective layer 533, and positioned at connecting key 503 the The thickness of protective layer 533 of one end 531 is more than the thickness of protective layer 533 positioned at the second end 532, so that the connecting key 503 The size of first end 531 is more than the size of the second end 532 of the connecting key 503.
Because the first end 531 of the connecting key 503 is fixed on the surface of carrier 500 by tack coat, when the connecting key When 531 size of first end 531 is more than the second 532 size of end, fixation of the connecting key 503 on the surface of carrier 500 is more steady Fixed, during plastic packaging layer is subsequently formed, the connecting key 503 is not susceptible to displacement, advantageously ensures that the connecting key 503 Position relative to chip 500 is accurate.
And the conductor wire 530 in the connecting key 503 is identical from 503 first end of connecting key, 531 to the second end, 532 diameters, It is smaller from the end 532 of 503 first end of connecting key 531 to the second, the resistivity contrasts of the conductor wire 530 so that the conductor wire 530 electric performance stablity.
The forming step of the connecting key is illustrated below with reference to accompanying drawing.
It refer to Figure 18, there is provided initial conduction line 600, the initial conduction line 600 have the 3rd end 601 and the 4th end 602；Initial protective layers 603 are formed in the sidewall surfaces of the initial conduction line 600, form initial connecting key 610, it is described initial Protective layer 601 exposes the 3rd end 601 and the 4th end 602 of the initial conduction line 600.
In the present embodiment, it is described first from the direction at the end 602 of the 3rd end 601 to the 4th of the initial conduction line 600 Beginning connecting key 600 has some cut length 620, and each cut length 620 is respectively provided with close to the 5th end 621 at the 3rd end 601 and leaned on 6th end 622 at nearly 4th end 602；The thickness of initial protective layers 603 at the end 621 of the cut length 620 the 5th is more than cut length the The thickness of initial protective layers 603 at six ends 622.
The formation process of the initial protective layers 603 is Shooting Technique.The forming step bag of the initial protective layers 603 Include：Diaphragm is formed on the surface of initial conduction line 600 using coating process；The diaphragm is moulded using mould Shape, form the initial protective layers 603.
Wherein, the inner wall surface pattern of the mould is identical with the surface topography of the initial protective layers 603 of required formation, from And by the moulding of the mould, the thickness of protective layer 603 can be made to produce difference, the surface of protective layer 603 is serrated.
The material of the protective layer 233 is organic insulation；The organic insulation includes polyvinyl chloride or resin； The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
Figure 19 is refer to, it is described first along being cut perpendicular to the direction of initial conduction line 600 (as shown in figure 18) side wall Beginning protective layer 603 (as shown in figure 18) and initial conduction line 601 (as shown in figure 18), form some sections of conductor wires 530, Yi Jiwei In the protective layer 533 of the sidewall surfaces of conductor wire 530.
After the initial connecting key 610 (as shown in figure 18) is cut, some cut length 620 (as shown in figure 18) are mutual Independent, each cut length 620 forms the connecting key 503, and the 5th end 621 (as shown in figure 18) of the cut length 620 turns into The first end 531 of connecting key 503,622 the second end 532 (as shown in figure 18) as connecting key of the 6th end of the cut length.
In the present embodiment, the sidewall surfaces of the initial conduction line 600 are around the axis B (as shown in figure 18) Surface, the axis B are the central shaft by the 3rd end 601 and the 4th end 602 in the initial conduction line 600；Along perpendicular to The direction cutting of the side wall of initial conduction line 600 is along perpendicular to the axis B direction cutting initial protective layers 603 and just Beginning conductor wire 600.
The cutting technique can be laser cutting parameter.After cutting technique, the initial protective layers 603 and just Beginning conductor wire 600 forms some discrete connecting keys 503.Moreover, edge of the cutting technique along the cut length 620 enters OK, so that some cut length 620 can be mutually discrete.
Figure 20 is refer to, forms plastic packaging layer 504 on the surface of carrier 500, the plastic packaging layer 504 surrounds the chip 501 and connecting key 503, the surface of the plastic packaging layer 504 expose the second end 532 and the work(of chip 501 of the connecting key 503 Can area surface；Wiring layer 507 again, the wiring layer again 507 and the connecting key 503 are formed on the surface of plastic packaging layer 504 Second end 532 and the electrical connection of the functional areas of chip 501；The first soldered ball 581 is formed on the surface of wiring layer again 507；In shape Into after first soldered ball 581, the carrier 500 (as shown in figure 19) is removed, exposes the first end of the connecting key 503 531。
The plastic packaging layer 504, the technique for forming plastic packaging layer 504, the wiring layer again 507, the work for forming again wiring layer 507 Skill, first soldered ball 581, the technique for forming the first soldered ball 581 and the technique and previous embodiment phase that remove carrier 500 Together, will not be described here.
In the present embodiment, it is additionally included in the surface of plastic packaging layer 504 and forms the first insulating barrier 505, first insulation There is conductor wire 530 and the functional areas surface of chip 501 for exposing the end 532 of connecting key 503 second respectively in layer 505 Some first through hole；The functional areas surface of chip 501 is the top surface of the projection 521 on chip 501.Described In the first through hole and surface of the first insulating barrier of part 505 forms wiring layer 507 again, the wiring layer again 507 with it is described Second end 532 of connecting key 503 and projection 521 electrically connect.
In the present embodiment, it is additionally included in the surface of wiring layer 507 again and forms the second insulating barrier 508, described second is exhausted There is the second through hole for exposing partly again wiring layer 507 in edge layer 508；First soldered ball is formed in second through hole 581。
In addition, after the carrier 500 is removed, additionally it is possible in the conductor wire 530 of the first end 531 of connecting key 503 Surface forms the second soldered ball.
Moreover, after the second soldered ball is formed, in addition to：Packaging body is provided, the packaging body has the 3rd surface, described 3rd surface of packaging body exposes conductive structure；Make first surface 510 and the surface of plastic packaging layer 504 and the institute of the chip 501 The 3rd surface for stating packaging body is oppositely arranged, and second soldered ball is mutually interconnected with the conductive structure by welding procedure Connect.
To sum up, in the present embodiment, the first end size of the connecting key is more than the second end size of the connecting key.Due to Carrier surface is fixed at second end of the connecting key, and the first end size of the connecting key is larger, is advantageous to make the company The fixation that key is connect in carrier surface is more stable, can avoid during plastic packaging layer is formed, and the connecting key is subjected to displacement, So as to ensure that the relative position between connecting key and chip is accurate.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (16)

  1. A kind of 1. forming method of encapsulating structure, it is characterised in that including：
    Carrier is provided；
    In the carrier surface fixed chip, the chip has relative a first surface and second surface, and the of the chip Two surfaces include functional areas, and first surface and the carrier surface of the chip interfix；
    Key is fixedly connected with the carrier surface of the chip circumference, the connecting key includes conductor wire and positioned at the conduction The protective layer of line side wall surface, the protective layer expose the conductor wire at the connecting key first end and the second end, the connection Key includes first end and the second end, and the first end of the connecting key and the second end expose the conductor wire, the connecting key First end interfixes with the carrier surface, and the second end of the connecting key is higher than or be flush to the functional areas table of the chip Face；
    The forming step of the connecting key includes：Initial conduction line is provided, the initial conduction line has the 3rd end and the 4th end； Initial protective layers are formed in the sidewall surfaces of the initial conduction line, form initial connecting key, the initial protective layers expose The 3rd end and the 4th end of the initial conduction line；Along perpendicular to the direction of the initial conduction line side wall cutting initial guarantor Sheath and initial conduction line, form some sections of conductor wires and the protective layer positioned at conductor wire sidewall surfaces；Initially led from described On the direction at the 3rd end to the 4th end of electric wire, the initial connecting key has some cut length, and each cut length is respectively provided with close 5th end at the 3rd end and the 6th end at close 4th end；The initial protective layers thickness at the end of cut length the 5th, which is more than, to be cut Cut the initial protective layers thickness at the end of section the 6th；After the initial connecting key is cut, some cut length are separate, each cutting Section forms the connecting key, and the 5th end of the cut length turns into the first end of connecting key, the 6th end of the cut length into For the second end of connecting key；
    Plastic packaging layer is formed in the carrier surface, the plastic packaging layer surrounds the chip and connecting key, the surface of the plastic packaging layer Expose the second end of the connecting key and the functional areas surface of chip；
    Wiring layer again, the wiring layer again and the second end of the connecting key and the work(of chip are formed in the plastic packaging layer surface Can area's electrical connection；
    The first soldered ball is formed in the layer surface that connects up again；
    After first soldered ball is formed, the carrier is removed, exposes the first end of the connecting key.
  2. 2. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the formation process of the initial protective layers Including chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process, spraying coating process or Shooting Technique.
  3. 3. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the forming step of the initial protective layers Including：Diaphragm is formed on the initial conduction line surface using coating process；It is moulding to diaphragm progress using mould, Form the initial protective layers.
  4. 4. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the material of the protective layer is insulation material Material.
  5. 5. the forming method of encapsulating structure as claimed in claim 4, it is characterised in that the insulating materials is organic insulation material Material or inorganic insulating material；The organic insulation includes polyvinyl chloride；The inorganic insulating material includes silica, nitridation One or more in silicon and silicon oxynitride.
  6. 6. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the first end size of the connecting key is big In the second end size of the connecting key.
  7. 7. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the first end size of the connecting key with Second end size is identical.
  8. 8. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the connecting key first end to the second end Distance be 40 microns~400 microns.
  9. 9. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the conductor wire of the connecting key first end Size is identical with the conductive linear dimension at the second end.
  10. 10. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the material of the conductor wire be copper, Tungsten, aluminium, gold or silver.
  11. 11. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the first surface of the chip passes through Tack coat is fixed on the carrier surface；The first end of the connecting key is fixed on the carrier surface by tack coat.
  12. 12. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the functional areas surface of the chip is sudden and violent Exposed pad；The bond pad surface has projection, and the top surface of the projection protrudes from the second surface of the chip；It is described Plastic packaging layer exposes the top surface of the projection, and the top surface of the projection is the functional areas surface of the chip.
  13. 13. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：The cloth again described in formed Before line layer, the first insulating barrier is formed in the plastic packaging layer surface, has in first insulating barrier and exposes the company respectively Connect the conductor wire at the end of key second and some first through hole on chip functions area surface；In the first through hole and part First surface of insulating layer forms the wiring layer again.
  14. 14. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：Formed the soldered ball it Before, the second insulating barrier is formed in the layer surface that connects up again, has in second insulating barrier and exposes partly again wiring layer Second through hole；First soldered ball is formed in second through hole.
  15. 15. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：Remove the carrier it Afterwards, the second soldered ball is formed on the conductor wire surface of the connecting key first end.
  16. 16. the forming method of encapsulating structure as claimed in claim 15, it is characterised in that also include：Packaging body is provided, it is described Packaging body has the 3rd surface, and the 3rd surface of the packaging body exposes conductive structure；
    The first surface and plastic packaging layer surface and the 3rd surface of the packaging body for making the chip are oppositely arranged, and pass through welding Technique makes second soldered ball be connected with each other with the conductive structure.
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CN105489569B (en) * 2015-12-24 2020-01-07 合肥矽迈微电子科技有限公司 Packaging structure of pressure sensor and manufacturing method thereof
CN106783643A (en) * 2016-12-29 2017-05-31 华进半导体封装先导技术研发中心有限公司 A kind of chip and its method for packing
CN111146099B (en) * 2019-12-31 2021-12-24 中芯集成电路（宁波）有限公司 Semiconductor structure and manufacturing method thereof

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