CN105845672B - Encapsulating structure - Google Patents
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- CN105845672B CN105845672B CN201610422460.2A CN201610422460A CN105845672B CN 105845672 B CN105845672 B CN 105845672B CN 201610422460 A CN201610422460 A CN 201610422460A CN 105845672 B CN105845672 B CN 105845672B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
A kind of encapsulating structure, including：First chip, the first chip have functional surfaces；Substrate core layer, substrate core layer include with opposite first surface and second surface, substrate core layer：Plastic package structure and the connection bond structure in plastic package structure；Plastic packaging layer surrounds first chip, and the functional surfaces of the first chip are arranged towards first surface；It includes the first connecting key and the second connecting key being electrically connected to connect bond structure, the distance of second connecting key to first surface is more than the first connecting key to the distance of first surface, the distance of second connecting key to the first chip is more than the distance of the first connecting key to the first chip, and the first connecting key is electrically connected with functional surfaces；Second chip, is located at second surface, and the second chip and the first chip are located at the same side of connection bond structure；Bond wire line, one end and the second connecting key of the bond wire line are electrically connected, and the other end of bond wire line is electrically connected with the second chip.The reliability of the encapsulating structure is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of encapsulating structures.
Background technology
Wafer-level packaging (Wafer Level Packaging, abbreviation WLP) technology is to be packaged test to full wafer wafer
It cuts to obtain the technology of single finished product chip again afterwards.With ceramic leadless chip carrier (Ceramic Leadless Chip
Carrier) or organic leadless chip carrier (Organic Leadless Chip Carrier) isotype is compared, wafer scale
Encapsulation technology has many advantages, such as lighter, smaller, shorter, thinner and more cheap.Wafer level packaging be can by IC design,
The technology that wafer manufacture, packaging and testing, substrate manufacture integrate, thus as the hot spot in current encapsulation field and the following hair
The trend of exhibition.
Fan-out wafer encapsulation is one kind of wafer-level packaging.Fan-out wafer packaging method comprises the following steps that：It is carrying
Body surface face forms stripping film, and forms first medium layer in stripping film surface, and the first graph layer, institute are formed on first medium layer
The first graph layer is stated with the first opening；The first metal electrode for being connect with edge of substrate is formed in the first opening, the
One figure layer surface forms interconnection metal layer again；In the first surface of metal electrode, again wiring metal layer surface and first medium
Layer surface forms second dielectric layer, and forms second graph layer in second medium layer surface, and the second graph layer has second
Opening；The second metal electrode for being connect with die terminals is formed in the second opening；By flip-chip to the second metal electrode
Afterwards, plastic packaging layer is formed in second dielectric layer and chip surface, the plastic packaging layer surrounds the chip, forms encapsulating structure；It will carry
Body and stripping film are detached with encapsulating structure；Ball reflux is planted, soldered ball is formed；Monolithic cutting forms fan-out chip packaging structure.
However, the reliability for the encapsulating structure that existing Wafer level packaging is formed is poor.
Invention content
Problems solved by the invention is to provide a kind of encapsulating structure, to improve the reliability of encapsulating structure.
To solve the above problems, the present invention provides a kind of encapsulating structure, including：First chip, the first chip have function
Face；Substrate core layer, the substrate core layer include with opposite first surface and second surface, substrate core layer：Plastic packaging
Structure and the connection bond structure in plastic package structure；The plastic package structure surrounds first chip, and first chip
Functional surfaces be arranged towards the first surface；The connection bond structure includes the first connecting key being electrically connected and the second connection
Key, the distance of the second connecting key to first surface are more than the first connecting key to the distance of first surface, and second connecting key arrives
The distance of first chip is more than the distance of the first connecting key to the first chip, and first connecting key connects with the functional surfaces electricity
It connects；Second chip, is located at second surface, and second chip and the first chip are located at the same side of connection bond structure；Bonding gold
Belong to line, one end and the second connecting key of the bond wire line are electrically connected, the other end of bond wire line and the second chip electricity
Learn connection.
Optionally, the connection bond structure further includes intermediate connecting key, and the first connecting key and the second connecting key pass through centre
Connecting key is electrically connected.
Optionally, the material of the first connecting key, the second connecting key and intermediate connecting key is copper, tungsten, aluminium, gold or silver.
Optionally, the intermediate connecting key has the first opposite connecting pin and second connection end, the first connecting pin to the
The distance of one chip is less than second connection end to the distance of the first chip, and the first connecting pin connect key connection with first, and second connects
It connects end and connect key connection with second.
Optionally, the surface of second chip has lead end；The other end of the bond wire line and the lead
End connection.
Optionally, the material of the bond wire line is copper, tungsten, aluminium, gold or silver.
Optionally, the substrate core layer further includes：First pad, first pad have the first opposite face of weld and
Second face of weld, first face of weld connect key connection with second, and second face of weld is connect with bond wire line.
Optionally, first connecting key includes opposite first end and second end, and first end is arranged towards first surface,
Second end is electrically connected with the second connecting key.
Optionally, the substrate core layer further includes：Second pad and multiple third connecting keys, second pad pass through
Multiple third connecting keys are connect with the first end surfaces and functional surfaces of the first connecting key respectively.
Optionally, the functional surfaces include functional areas, and the surfaces of the functional areas is connected with third connecting key, and described second
Pad is connect by the third connecting key on functional areas surface with functional areas.
Optionally, further include：Soldered ball is located at the second bond pad surface.
Optionally, further include：Protective layer, the protective layer cover second chip, bond wire line and second surface.
Optionally, further include：Master bond layer, between the second chip and second surface.
Optionally, further include：Passive device, in plastic package structure, the passive device and the first connecting key electricity connect
It connects；First connecting key is between the passive device and the first chip.
Compared with prior art, technical scheme of the present invention has the following advantages：
Encapsulating structure provided by the invention, since connection bond structure includes the first connecting key and the second connecting key, second connects
The distance that key is more than the first connecting key to the first chip to the distance of the first chip is connect, and the second chip and the first chip are located at company
The same side of bond structure is connect, so that the distance of the second connecting key to the second chip is more than the first connecting key to the second chip
Distance.So that the distance of the second connecting key to the second chip is larger, enough spaces are provided for the bond wire line so that
Bond wire line is easy to be formed, therefore the reliability of bond wire line improves.To improve the reliability of encapsulating structure.
Description of the drawings
Fig. 1 is a kind of schematic diagram of encapsulating structure；
Fig. 2 is the structural schematic diagram for the encapsulating structure that one embodiment of the invention provides；
Fig. 3 to Figure 13 is the structural schematic diagram of the forming process of encapsulating structure provided by the invention.
Specific implementation mode
As described in background, the reliability for the encapsulating structure that the prior art is formed is to be improved.
Fig. 1 is a kind of cross-sectional view of encapsulating structure, and encapsulating structure includes：First chip 100, first core
Piece 100 has functional surfaces；Plastic packaging layer 130, the plastic packaging layer 130 have opposite first surface and second surface, the plastic packaging
Layer 130 surrounds first chip 100, and the functional surfaces of first chip 100 are arranged towards first surface；Conductive plunger 120,
In plastic packaging layer 130, the conductive plunger 120 has opposite first total end face and second total end face, first total end face court
It is arranged to first surface, first total end face is electrically connected with functional surfaces；Second chip 160 is located at second surface, second core
Piece 160 and the first chip 100 are located at the same side of conductive plunger 120；Bond wire line 170, the one of the bond wire line 170
End is electrically connected with second total end face, and the other end of the bond wire line 170 is electrically connected with the second chip 160.
The bond wire line 170 is formed using routing technique.
However, the reliability of above-mentioned encapsulating structure is poor, reason is：
With the continuous reduction of characteristic size, the distance of the 120 to the second chip of conductive plunger 160 constantly reduces, and leads to
The distance of two total end faces to the second chip 160 reduces.In addition, first total end face of conductive plunger 120 to the first chip 100 away from
With a distance from second total end face to the first chip 100 equal to conductive plunger 120.When the second chip 160 is in the throwing of second surface
Shadow area is more than the first chip 100 in the projected area of second surface, and the distance of second total end face to the second chip 160 subtracts
It is small.
Since the distance of second total end face to the second chip 160 reduces, cause to be supplied to the space of bond wire line 170 compared with
Small, resulting in bond wire line 170 cannot be normally carried out using routing technique, influence the formation of bond wire line 170.To
The reliability of encapsulating structure is caused to reduce.
On this basis, the present invention provides a kind of encapsulating structure, including：First chip, the first chip have functional surfaces；Base
Plate core layer, the substrate core layer include with opposite first surface and second surface, substrate core layer：Plastic package structure and
Connection bond structure in plastic package structure；The plastic package structure surrounds first chip, and the function of first chip
It is arranged facing towards the first surface；The connection bond structure includes the first connecting key and the second connecting key being electrically connected, the
The distance of two connecting keys to first surface is more than the first connecting key to the distance of first surface, second connecting key to the first core
The distance of piece is more than the distance of the first connecting key to the first chip, and first connecting key is electrically connected with the functional surfaces；The
Two chips, are located at second surface, and second chip and the first chip are located at the same side of connection bond structure；Bond wire line,
One end of the bond wire line is electrically connected with the second connecting key, and the other end of bond wire line and the second chip electricity connect
It connects.
Since connection bond structure includes the first connecting key and the second connecting key, the distance of the second connecting key to the first chip is big
In the first connecting key to the distance of the first chip, and the second chip and the first chip are located at the same side of connection bond structure, therefore
So that the distance of the second connecting key to the second chip is more than the distance of the first connecting key to the second chip.So that the second connecting key arrives
The distance of second chip is larger, and enough spaces are provided for the bond wire line so that and bond wire line is easy to be formed, because
The reliability of this bond wire line improves.To improve the reliability of encapsulating structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 2 is the schematic diagram for the encapsulating structure that one embodiment of the invention provides.
The encapsulating structure, with reference to figure 2, including：
First chip 210, the first chip 210 have functional surfaces；
Substrate core layer, the substrate core layer include with opposite first surface and second surface, substrate core layer：
Plastic package structure and the connection bond structure in plastic package structure；
The plastic package structure surrounds first chip 210, and the functional surfaces of first chip 210 are towards described first
Surface is arranged；
The connection bond structure includes the first connecting key 240 and the second connecting key 280 being electrically connected, the second connecting key
The distance of 280 to first surface is more than the first connecting key 240 to the distance of first surface, second connecting key 280 to the first
The distance of chip 210 is more than the distance of first the 240 to the first chip of connecting key 210, first connecting key 240 and the function
Face is electrically connected；
Second chip 350, is located at second surface, and second chip, 350 and first chip 210 is located at connection bond structure
The same side；
Bond wire line 360, one end of the bond wire line 360 are electrically connected with the second connecting key 280, bond wire
The other end of line 360 is electrically connected with the second chip 350.
First chip 210 can be sensor chip, logic circuit chip, storage chip etc..
In the present embodiment, the first chip 210 has opposite functional surfaces and non-functional surface, first chip 210
Functional surfaces are arranged towards first surface, and the functional surfaces include functional areas.
In the functional areas can have transistor, passive device (such as resistance, capacitance and inductance etc.), memory device,
One or more of sensor, electric interconnection structure.
The functional areas surface of first chip 210 exposes initial pad；The initial bond pad surface has convex block
213, the convex block 213 protrudes from the functional surfaces of first chip 210, functional areas surface, that is, institute of first chip 210
State the bottom surface of convex block 213.
The material of the convex block 213 includes copper, gold or tin, and the convex block 213 has preset thickness.213 energy of the convex block
Enough circuit or device realizations in functional areas are electrically connected.The convex block 213 is used to carry out with the connection bond structure being subsequently arranged
Electrical connection, the second chip and passive device and external circuit to realize the functional areas of the first chip 210 and be subsequently formed
Between electrical connection.
There is first connecting key 240 opposite first end and second end, first end to be arranged towards first surface, and second
End is electrically connected with the second connecting key.
The connection bond structure further includes intermediate connecting key 260.Second connecting key 280 passes through intermediate connecting key 260 and
One connecting key 240 is electrically connected.
First connecting key 240, intermediate 260 and second connecting key 280 of connecting key material be conductive material, it is described to lead
Electric material is copper, tungsten, aluminium, gold or silver.
The intermediate connecting key 260 has the first opposite connecting pin and second connection end, the first connecting pin to the first core
The distance of piece 210 is less than second connection end to the distance of the first chip 210, and the first connecting pin is connect with the first connecting key 240, the
Two connecting pins are connect with the second connecting key 280.
Specifically, the first connecting pin of intermediate connecting key 260 is connect with the second end of the first connecting key 240.
Due to the distance of the first connecting pin to the first chip 210 be less than second connection end to the first chip 210 distance, the
One connecting key 240 is connect with the first connecting pin, and the second connecting key 280 is connect with second connection end, so that being parallel to
On the direction on two surfaces, the distance of second the 280 to the first chip of connecting key 210 is more than first the 240 to the first chip of connecting key 210
Distance.
The substrate core layer further includes：First pad 300, the first pad 300 have opposite first face of weld and second
The face of weld, first face of weld are connect with the second connecting key 280, and second face of weld is connect with bond wire line 360.
The material of first pad 300 is metal, such as copper, tungsten, aluminium, gold or silver.
The substrate core layer further includes：Second pad 340 and multiple third connecting keys 320, second pad 340 are logical
Multiple third connecting keys 320 are crossed to connect with the first end surfaces of the first connecting key 240 and functional surfaces respectively.
Specifically, the functional surfaces of functional areas are connected with third connecting key 320, second pad 340 passes through functional areas table
The third connecting key 320 in face is connect with functional areas.
The functional surfaces are electrically connected with the first connecting key 240.Specifically, the functional surfaces pass through 340 He of the second pad
The realization of third connecting key 320 is electrically connected with the first connecting key 240.
The encapsulating structure further includes passive device 220, and the passive device 220 is embedded in plastic package structure.Described first
Connecting key 240 is between the passive device 220 and the first chip 210.
The passive device 220 can be resistance, capacitance, inductance, converter, taper, resonator, filtering net, mixing
Device or switch.
Specifically, the passive device 220 has opposite third surface and the 4th surface, the third surface is towards institute
State first surface setting.
The passive device 220 is electrically connected with the first connecting key 240.Specifically, the third surface is connect with first
Key 240 is electrically connected.
The third surface is also connected with third connecting key 320, and second pad 340 passes through multiple third connecting keys
320 connect with the first end surfaces of the first connecting key 240, functional surfaces and third surface respectively.
The plastic package structure, connection bond structure, the first pad 300, third connecting key 320 and the second pad 340 constitute base
Plate core layer.
Second chip 350 can be sensor chip, logic circuit chip, storage chip etc..
Second chip 350 is fixed on second surface by master bond layer.The material of the master bond layer be UV glue or
The other cohesive materials of person.
The surface of second chip 350 has lead end；The other end of the bond wire line 360 and the lead end
Connection, to realize being electrically connected for bond wire line 360 and the second chip 350.
The material of the bond wire line 360 is metal, such as copper, tungsten, aluminium, gold or silver.
In the present embodiment, one end of the bond wire line 360 passes through 280 electricity of the first pad 300 and the second connecting key
Connection, the other end of the bond wire line 360 are connect with the lead end.
Since the distance of second the 280 to the first chip of connecting key 210 is more than first the 240 to the first chip of connecting key 210
Distance, and the second chip 350 and the first chip 210 are located at the same side of connection bond structure, so that the second connecting key 280 arrives
The distance of second chip 350 is more than the distance of first the 240 to the second chip of connecting key 350.Make the second connecting key 350 to the second
The distance of chip 350 is larger, provides enough spaces for the bond wire line 360 so that bond wire line 360 is easy shape
At, therefore the reliability of bond wire line 360 improves.To improve the reliability of encapsulating structure.
The encapsulating structure further includes protective layer 370, and the protective layer 370 covers second chip 350, bond wire
Line 360 and second surface.
The material of the protective layer 370 is insulating materials, and the insulating materials is organic insulating material or inorganic insulation material
Material.
In one embodiment, when the material of the protective layer 370 is organic insulating material, the organic insulating material includes
Polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles tree
Fat.In another embodiment, the material of the protective layer 370 is inorganic insulating material, and the inorganic insulating material includes oxidation
It is one or more in silicon, silicon nitride and silicon oxynitride.
The encapsulating structure further includes soldered ball 380, and the soldered ball 380 is located at 340 surface of the second pad.
The material of the soldered ball 380 includes tin.
Between second pad 340 and the soldered ball 380, moreover it is possible to which there is metal structure (Under Ball under ball
Metal, abbreviation UBM).Metal structure can include the metal layer of single metal layer or multiple-layer overlapped under the ball；The single layer
The material of metal layer or more metal layers includes one or more combinations in copper, aluminium, nickel, cobalt, titanium, tantalum.
The forming process of encapsulating structure in above-described embodiment is discussed in detail with reference to Fig. 3 to Figure 13.
With reference to figure 3, support plate 200 is provided, the support plate 200 includes the 5th surface 201.
The support plate 200 provides workbench for subsequent technique, the part plastic packaging for carrying the first chip, being subsequently formed
Structure and the part connection bond structure being subsequently formed.
The support plate 200 has opposite the 5th surface 201 and the 6th surface 202.
In the present embodiment, the support plate 200 is rigid substrate, and the rigid substrate is PCB substrate, glass substrate, gold
Belong to substrate, semiconductor substrate or polymeric substrates.The rigid substrate has higher hardness, deformation is not susceptible to, follow-up
Enough support forces are provided in technique.
In other embodiments, the support plate can also be flexible base plate.
With continued reference to Fig. 3, the first chip 210 is fixed on the 5th surface 201 of the support plate 200, the first chip 210 has
Opposite functional surfaces 211 and non-functional surface 212, the functional surfaces 211 include functional areas, the functional surfaces of first chip 210
211 are arranged towards the 5th surface 201.
First chip 210 can be sensor chip, logic circuit chip, storage chip etc..The functional surfaces 211
Functional areas in can have transistor, passive device (such as resistance, capacitance and inductance etc.), memory device, sensor, electricity mutually
Link one or more of structure.
The forming step of first chip 210 includes：Substrate is provided, the substrate has several chip regions, the lining
Bottom includes opposite the first initial surface and the second initial surface, has work(in the chip region of the second initial surface of the substrate
It can area；The substrate is cut, several chip regions is made to be separated from each other, forms independent first chip 210.
In the present embodiment, the functional areas surface of first chip 210 exposes initial pad；The initial pad table
There is convex block 213, the convex block 213 to protrude from the functional surfaces 211 of first chip 210, the work(of first chip 210 in face
The bottom surface of energy area surface, that is, convex block 213.
The material of the convex block 213 includes copper, gold or tin, and the convex block 213 has preset thickness.213 energy of the convex block
Enough circuit or device realizations in functional areas are electrically connected.The convex block 213 is used to carry out with the connection bond structure being subsequently arranged
Electrical connection, the second chip and passive device and external circuit to realize the functional areas of the first chip 210 and be subsequently formed
Between electrical connection.
The functional surfaces 211 of first chip 210 are fixed on the 5th table of the support plate 200 by adhesive layer (not shown)
Face 201.
In the present embodiment, the material of the adhesive layer is UV glue, and UV glue viscosity after ultraviolet light irradiates reduces, so as to
Subsequently support plate 200 is removed from encapsulating structure.The material of the adhesive layer can also be other cohesive materials.
In one embodiment, adhesive layer is adhered in the functional surfaces 211 of first chip 210, then by the adhesive layer
It is adhered to the 5th surface 201 of support plate 200, to realize the bonding between the first chip 210 and support plate 200.In another implementation
In example, the corresponding position for needing to fix the first chip on the 5th surface of the support plate forms adhesive layer, then by the first chip
Functional surfaces are adhered to the tie layer surface, and first chip is made to be fixed on the 5th surface of support plate.
In the present embodiment, the 5th surface 201 of the support plate 200 is global covers the adhesive layer.
In the present embodiment, further include：Passive device 220 is fixed on the 5th surface 201 of the support plate 200.It is described passive
Device 220 is fixed on the 5th surface 201 of the support plate 200 by the adhesive layer.
The passive device 220 has opposite third surface and the 4th surface, the third surface and the 5th surface 201
It is fixed.
The passive device 220 can be resistance, capacitance, inductance, converter, taper, resonator, filtering net, mixing
Device or switch.
With reference to figure 4, forms the first plastic packaging layer 230 on the 5th surface 201 and connect through the first of the first plastic packaging layer 230
Key 240 is connect, the first plastic packaging layer 230 surrounds the first chip 210.
In the present embodiment, the first plastic packaging layer 230 also covers the passive device 220.
First connecting key 240 connects a part for bond structure for subsequently constituting.The material of first connecting key 240
Material is conductive material, and the conductive material is copper, tungsten, aluminium, gold or silver.
The first plastic packaging layer 230 is photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, the first plastic packaging layer 230 is photosensitive dry film, the formation process of the first plastic packaging layer 230
For vacuum film coating process.In another implementation, the material of the first plastic packaging layer 230 is capsulation material, the capsulation material packet
Include epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, poly- carbon
Acid esters, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, gathers polyethylene terephthalate
Polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymer materials.In other embodiments, described
First plastic packaging layer material may be other insulating materials.
In the present embodiment, the first plastic packaging layer 230 is formed on the 5th surface 201, the first plastic packaging layer 230 surrounds institute
It states the first chip 210 and exposes the non-functional surface 212, the first plastic packaging layer 230 also covers the passive device 220,
There is the first opening (not shown), first opening to expose the 5th surface of support plate 200 in the first plastic packaging layer 230
201；First connecting key 240 is formed in first opening using electroplating technology or sputtering technology.
There is first connecting key 240 opposite first end and second end, first end to be arranged towards the 5th surface 201,
First plastic packaging layer 230 exposes the second end of the first connecting key 240.The intermediate connecting key and the first connecting key 240 being subsequently formed
Second end connection.
Specifically, the step of forming the first plastic packaging layer 230 includes：Covering described first is formed on the 5th surface 201
First plastic packaging film of chip 210 and passive device 220；First plastic packaging film is polished, until exposing described first
The non-functional surface 212 of chip 210；Then the graphical initial plastic packaging layer, to form the first plastic packaging layer 230, the first plastic packaging
There is the first opening in layer 230.
In other embodiments, the first plastic packaging layer can also cover the non-functional surface.Correspondingly, forming the first modeling
The step of sealing is：The first plastic packaging film for covering first chip and passive device is formed in first sublist face；Figure
Change first plastic packaging film, to form the first plastic packaging layer, there is the first opening in the first plastic packaging layer.
The formation process of first plastic packaging film includes Shooting Technique (injection molding), turns modeling technique
(transfer molding) or silk-screen printing technique.
Forming the Shooting Technique that the first plastic packaging film uses includes：Mold is provided；Capsulation material is filled in the mold, is made
The capsulation material coats first chip 210 and passive device 220；Elevated cure is carried out to the capsulation material, is formed
First plastic packaging film.
In other embodiments, Ke Yishi：The first connecting key is fixed on the 5th surface around first chip, described
There is first connecting key opposite first end and second end, the first end to be fixed with the 5th surface, first connecting key
The second end is flushed higher than non-functional surface or with the non-functional surface；It is formed on the 5th surface and surrounds first chip
The first plastic packaging layer, the first plastic packaging layer exposes second end.
Specifically, the first end of first connecting key is fixed on the 5th surface by the adhesive layer.
With reference to figure 5, the shape on the surface and the first chip 210 of the first plastic packaging layer 230 and the first connecting key 240
At the second plastic packaging layer 250 and through the intermediate connecting key 260 of the second plastic packaging layer 250, the intermediate connecting key 260 and first
Connecting key 240 connects.
Material of the material of the second plastic packaging layer 250 with reference to the first plastic packaging layer 230；The material of the intermediate connecting key 260
Material is no longer described in detail with reference to the material of the first connecting key 240.
The intermediate connecting key 260 connects a part for bond structure for subsequently constituting.
First connecting key 240 second connect key connection by intermediate connecting key 260 with what is be subsequently formed, to realize
First connecting key 240 and the second connecting key for being subsequently formed are electrically connected.
The intermediate connecting key 260 has the first opposite connecting pin and second connection end, the first connecting pin to the first core
The distance of piece 210 is less than second connection end to the distance of the first chip 210, and the first connecting pin is connect with the first connecting key 240, the
Two connecting pins second connect key connection with what is be subsequently formed.
Specifically, the first connecting pin of the intermediate connecting key 260 is connect with the second end of the first connecting key 240.
In the present embodiment, on the surface and the first chip 210 of the first plastic packaging layer 230 and the first connecting key 240
The second plastic packaging layer 250 is formed, there is the second opening for exposing the first connecting key 240 (not scheme in the second plastic packaging layer 250
Show), specifically, second opening exposes 240 second end of the first connecting key；Using electroplating technology or sputtering technology in institute
It states and forms intermediate connecting key 260 in the second opening.
Specifically, the forming step of the second plastic packaging layer 250 includes：It is connected in the first plastic packaging layer 230 and first
The second plastic packaging film is formed on the surface of key 240 and the first chip 210；Second plastic packaging film is patterned, forms the
Two plastic packaging layers 250, and there is the second opening in the second plastic packaging layer 250.
In other embodiments, Ke Yishi：It is first on the surface of first connecting key and the surface of part the first plastic packaging layer
Form intermediate connecting key；Then it is formed on the surface of the first plastic packaging layer and the first chip and surrounds the intermediate connecting key
Second plastic packaging layer, the second plastic packaging layer expose the surface of intermediate connecting key.
With reference to figure 6, forms third plastic packaging layer 270 on the surface of the second plastic packaging layer 250 and intermediate connecting key 260 and pass through
The second connecting key 280 of third plastic packaging layer 270 is worn, the second connecting key 280 is connect with intermediate connecting key 260.
The material of the third plastic packaging layer 270 is with reference to the material of the first plastic packaging layer 230, the material ginseng of the second connecting key 280
According to the material of the first connecting key 240, no longer it is described in detail.
Specifically, the second connecting key 280 is connect with the second connection end of intermediate connecting key 260.
Second connecting key 280 connects a part for bond structure for subsequently constituting.
Since the distance of second connection end to the first chip 210 is more than the distance of the first connecting pin to the first chip 210, the
One connecting key 240 is connect with the first connecting pin, and the second connecting key 280 is connect with second connection end, so that being parallel to
On the direction in one sublist face 201, the distance of second the 280 to the first chip of connecting key 210 is more than first the 240 to the first core of connecting key
The distance of piece 210.
In the present embodiment, third plastic packaging layer 270 is formed on the surface of the second plastic packaging layer 250 and intermediate connecting key 260,
There is the third opening (not shown) for exposing intermediate connecting key 260, specifically, the third in the third plastic packaging layer 270
Opening exposes second connection end；Second connecting key is formed in third opening using electroplating technology or sputtering technology
280。
Specifically, the forming step of the third plastic packaging layer 270 includes：In the second plastic packaging layer 250 and intermediate connection
The surface of key 260 forms third plastic packaging film；The third plastic packaging film is patterned, forms third plastic packaging layer 270, and described
There is third opening in third plastic packaging layer 270.
In other embodiments, Ke Yishi：It is fixedly connected with the second connecting key in the second connection end；Later, described
The surface of second plastic packaging layer and intermediate connecting key forms the third plastic packaging layer for surrounding second connecting key, the third plastic packaging layer
Expose the surface of the second connecting key.
With reference to figure 7, the first pad 300 and encirclement first are formed on the surface of the second connecting key 280 and third plastic packaging layer 270
4th plastic packaging layer 290 of pad 300, the 4th plastic packaging layer 290 expose the surface of the first pad 300, the first pad 300 with
Second connecting key 280 connects.
The material of first pad 300 is metal, such as copper, tungsten, aluminium, gold or silver.
There is first pad 300 opposite first face of weld and second face of weld, first face of weld and the second connecting key 280 to connect
It connects, second face of weld is connect with the bond wire line being subsequently formed.
In the present embodiment, it is initially formed the first pad 300, the first pad 300 is located at 280 surface of the second connecting key and part
The surface of three plastic packaging layers 270；Then it is formed on the surface of the third plastic packaging layer 270 and surrounds the 4th of first pad 300
Plastic packaging layer 290, the 4th plastic packaging layer 290 expose second face of weld of the first pad 300.
The technique for forming the 4th plastic packaging layer 290 is silk-screen printing technique, such as silk-screen printing green oil technique.
In the present embodiment, second face of weld of the 4th plastic packaging layer 290 also the first pad of covering part 300.
In other embodiments, Ke Yishi：It is initially formed the 4th plastic packaging layer, has in the 4th plastic packaging layer and exposes second
The 4th opening for connecting key surface forms the first pad in the 4th opening.
With reference to figure 8, after forming the first pad 300 and the 4th plastic packaging layer 290, support plate 200 (with reference to figure 7) is removed, described the
The surface of one plastic packaging layer 230 exposes the first end surfaces of functional surfaces 211 and the first connecting key 240.
Specifically, after removal support plate 200, the surface of the first plastic packaging layer 230 exposes the surface of functional areas.
In the present embodiment, the surface of the first plastic packaging layer 230 also exposes the third surface of passive device 220.
In the present embodiment, the adhesive layer, the bonding are covered since the 5th surface of the support plate 200 201 is global
Layer material be UV glue, first chip 210, the first connecting key 240 and passive device 220 by the adhesive layer with it is described
5th surface 201 of support plate 200 is fixed, and the first plastic packaging layer 230 is formed in the tie layer surface, therefore can be passed through
Ultraviolet light is carried out to the adhesive layer, so that the viscosity of adhesive layer is reduced, then by the support plate 200 from first chip
230 sur-face peeling of 210 functional surfaces 211, the first end of the first connecting key 240 and the first plastic packaging layer, to expose the first core
The third surface of the functional surfaces of piece 210, the first end surfaces of the first connecting key 240 and passive device 220.
After removing the support plate 200, cleaning is used to remove remaining adhesive layer.
In other embodiments, additionally it is possible to which the support plate is removed by etching technics or CMP process.
With reference to figure 9, after removing the support plate 200, in the first end of the first plastic packaging layer 230 and the first connecting key 240
Surface and functional surfaces 211 form the 5th plastic packaging layer 310 and multiple third connecting keys 320, the third connecting key 320 run through
The 5th plastic packaging layer 310, the third connecting key 320 are connected to the first end surfaces and function of the first connecting key 240
Face 211.
Specifically, the third connecting key 320 is connected to the surface of functional areas.
In the present embodiment, the third surface of the passive device 220 is also connected with third connecting key 320.
Specifically, the first end surfaces of the first plastic packaging layer 230 and the first connecting key 240, passive device 220
Three surfaces and functional surfaces 211 form the 5th plastic packaging layer 310, have multiple 5th openings in the 5th plastic packaging layer 310 (not
Diagram), the first end surfaces of the first connecting key 240, the third surface of passive device 220 and functional surfaces 211 are corresponding with the
Five openings；Third connecting key 320 is formed in the 5th opening using electroplating technology or sputtering technology.
In other embodiments, third connecting key is individually fixed in the first end surfaces, the passive device of the first connecting key
Third surface and functional surfaces；Later, on the third surface of the surface of the first plastic packaging layer, functional surfaces and passive device
The 5th plastic packaging layer for surrounding the third connecting key is formed, the 5th plastic packaging layer exposes the surface of third connecting key.
With reference to figure 10,330 He of the 6th plastic packaging layer is formed on the surface of the 5th plastic packaging layer 310 and third connecting key 320
Through the second pad 340 of the 6th plastic packaging layer 330, second pad 340 by multiple third connecting keys 320 respectively with
The first end surfaces and functional surfaces of first connecting key 240 connect.
The surface of the functional areas is connected with third connecting key 320, second pad 340 pass through functional areas surface
Three connecting keys 320 are connect with functional areas.
Material of the material of second pad 340 with reference to the first pad 300.
In the present embodiment, second pad 340 also connects with the third connecting key 320 on the third surface of passive device 220
It connects.
Specifically, the 6th plastic packaging layer 330 is formed on the surface of the 5th plastic packaging layer 310 and third connecting key 320, it is described
Have multiple six to be open (not shown) in 6th plastic packaging layer 330, the 6th opening exposes the third connecting key 320；
Second pad 340 is formed in the 6th opening using electroplating technology or sputtering technology.
In other embodiments, the second pad is fixed on third connecting key and the 5th plastic packaging layer surface；Later, described
5th plastic packaging layer surface forms the 6th plastic packaging layer for surrounding second pad, and the 6th plastic packaging layer exposes the second pad
Surface.
Wherein, the first plastic packaging layer 230, the second plastic packaging layer 250, third plastic packaging layer 270, the 4th plastic packaging layer the 290, the 5th
Plastic packaging layer 310 and the 6th plastic packaging layer 330 constitute plastic package structure；First connecting key 240,260 and second connecting key of intermediate connecting key
280 constitute connection bond structure.
The plastic package structure, connection bond structure, the first pad 300, third connecting key 320 and the second pad 340 constitute base
Plate core layer.
The substrate core layer has opposite first surface and second surface.
The second surface corresponds to second face of weld on the surface and the first pad 300 of the 4th plastic packaging layer exposed.
With reference to figure 11, the second chip 350,350 He of the second chip are fixed in the second surface of the substrate core layer
First chip 210 is located at the same side of connection bond structure.
Second chip 350 can be sensor chip, logic circuit chip, storage chip etc..
Second chip 350 is fixed on second surface by main binder (not shown).The material of the main binder
With reference to the material of the binder, no longer it is described in detail.
Since the second connecting key 280 is more than the first connecting key 240 and the first chip 210 at a distance from the first chip 210
Distance, and the second chip 350 and the first chip 210 are located at the same side of connection bond structure so that the second connecting key 280 with
The distance of second chip 350 is more than the first connecting key 240 at a distance from the second chip 400.
Continue to refer to figure 11, bond wire line 360 formed using routing technique, one end of the bond wire line 360 with
First pad 300 connects, and the other end of the bond wire line 360 is connect with the second chip 350.
The material of the bond wire line 360 is metal, such as copper, tungsten, aluminium, gold or silver.
In the present embodiment, second face of weld of one end connection of the bond wire line 360, the one of the bond wire line 360
End is electrically connected by the first pad 300 with the second connecting key 280.Second chip, 350 surface has lead end, the key
The other end for closing metal wire 360 is connect with the lead end.
In the present embodiment, the routing technological requirement bond wire line 360 has certain radian, it is therefore desirable to the first weldering
The distance between the routing point on 300 surface of disk and the routing point on 350 surface of the second chip cannot be too small, if 300 table of the first pad
The distance between the routing point in face and the routing point on 350 surface of the second chip are too small, then cause routing technique that cannot be normally carried out,
So that the reliability of encapsulating structure reduces.
When the area that the second chip 350 is projected in second surface is more than the first chip 210 and is projected in the area of second surface
When, if connection bond structure is equal to connection bond structure far from the second table close to one end of second surface at a distance from the second chip 350
The one end in face at a distance from the second chip 350, cause to connect bond structure close to one end of second surface and the second chip 350 away from
From too small, it cannot be that bond wire line 360 provide enough spaces, influence the formation of bond wire line 360.
In the present embodiment, since the second connecting key 280 is more than the first connecting key 240 and the at a distance from the second chip 350
The distance of two chips 350 so that the second connecting key 280 is larger at a distance from the second chip 350, to form 360 line of bond wire
Provide enough spaces so that routing technique can be normally carried out, to improve the reliability of encapsulating structure.
With reference to figure 12, the protective layer 370 for covering second chip 350, bond wire line 360 and second surface is formed.
The protective layer 370 covers the first pad 300 and the 4th plastic packaging layer 290.
The material of the protective layer 370 is insulating materials, and the insulating materials is organic insulating material or inorganic insulation material
Material.
In one embodiment, when the material of the protective layer 370 is organic insulating material, the organic insulating material includes
Polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles tree
Fat.Correspondingly, the formation process of the protective layer 370 can be spraying process or Shooting Technique.
In another embodiment, the material of the protective layer 370 is inorganic insulating material, and the inorganic insulating material includes
It is one or more in silica, silicon nitride and silicon oxynitride.Correspondingly, the formation process of the protective layer 370 being capable of chemistry
Gas-phase deposition, physical gas-phase deposition, atom layer deposition process.
With reference to figure 13, after forming protective layer 370, soldered ball 380 is formed on 340 surface of the second pad.
The material of the soldered ball 380 includes tin.
In the present embodiment, the forming step of the soldered ball 380 includes：In the surface printing tin cream of second pad 340；
High temperature reflux is carried out to the tin cream, under surface tension effects, forms soldered ball 380.In another embodiment, additionally it is possible to first exist
The surface printing scaling powder and soldered ball particle of second pad, then high temperature reflux form soldered ball.In another embodiment, described
The electroplating surface tin column of two pads, then high temperature reflux form soldered ball.
Between second pad 340 and the soldered ball 380, moreover it is possible to be formed with (the Under Ball of metal structure under ball
Metal, abbreviation UBM).Metal structure can include the metal layer of single metal layer or multiple-layer overlapped under the ball；The single layer
The material of metal layer or more metal layers includes one or more combinations in copper, aluminium, nickel, cobalt, titanium, tantalum.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of encapsulating structure, which is characterized in that including：
First chip, the first chip have functional surfaces；
Substrate core layer, the substrate core layer include with opposite first surface and second surface, substrate core layer：Plastic packaging
Structure and the connection bond structure in plastic package structure；
The plastic package structure surrounds first chip, and the functional surfaces of first chip are arranged towards the first surface；
The connection bond structure includes the first connecting key and the second connecting key being electrically connected, the second connecting key to first surface
Distance is more than the first connecting key to the distance of first surface, and the distance of second connecting key to the first chip is more than the first connection
To the distance of the first chip, first connecting key is electrically connected key with the functional surfaces；
Second chip, is located at second surface, and second chip and the first chip are located at the same side of connection bond structure；
Bond wire line, one end and the second connecting key of the bond wire line are electrically connected, the other end of bond wire line with
Second chip is electrically connected.
2. encapsulating structure according to claim 1, which is characterized in that the connection bond structure further includes intermediate connecting key,
First connecting key and the second connecting key are electrically connected by intermediate connecting key.
3. encapsulating structure according to claim 2, which is characterized in that the first connecting key, the second connecting key and intermediate connection
The material of key is copper, tungsten, aluminium, gold or silver.
4. encapsulating structure according to claim 2, which is characterized in that the intermediate connecting key has the first opposite connection
End and second connection end, the distance of the first connecting pin to the first chip are less than second connection end to the distance of the first chip, and first
Connecting pin connect key connection with first, and second connection end connect key connection with second.
5. encapsulating structure according to claim 1, which is characterized in that the surface of second chip has lead end；Institute
The other end for stating bond wire line is connect with the lead end.
6. encapsulating structure according to claim 1, which is characterized in that the material of the bond wire line be copper, tungsten, aluminium,
Gold or silver.
7. encapsulating structure according to claim 1, which is characterized in that the substrate core layer further includes：First pad, institute
Stating the first pad, there is opposite first face of weld and second face of weld, first face of weld to connect key connection, second face of weld and key with second
Close metal wire connection.
8. encapsulating structure according to claim 1, which is characterized in that first connecting key include opposite first end and
Second end, first end are arranged towards first surface, and second end is electrically connected with the second connecting key.
9. encapsulating structure according to claim 8, which is characterized in that the substrate core layer further includes：Second pad and
Multiple third connecting keys, second pad by multiple third connecting keys respectively with the first end surfaces of the first connecting key and
Functional surfaces connect.
10. encapsulating structure according to claim 9, which is characterized in that the functional surfaces include functional areas, the functional areas
Surface be connected with third connecting key, second pad is connect by the third connecting key on functional areas surface with functional areas.
11. encapsulating structure according to claim 9, which is characterized in that further include：Soldered ball is located at the second bond pad surface.
12. encapsulating structure according to claim 1, which is characterized in that further include：Protective layer, the protective layer cover institute
State the second chip, bond wire line and second surface.
13. encapsulating structure according to claim 1, which is characterized in that further include：Master bond layer, be located at the second chip and
Between second surface.
14. encapsulating structure according to claim 1, which is characterized in that further include：Passive device, in plastic package structure,
The passive device is electrically connected with the first connecting key；First connecting key be located at the passive device and the first chip it
Between.
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| CN109103266B (en) * | 2018-09-19 | 2024-02-06 | 华天科技（西安）有限公司 | Photoelectric sensor packaging structure and packaging method thereof |
| KR102216738B1 (en) * | 2019-04-17 | 2021-02-18 | 제엠제코(주) | Metal Clip for Semiconductor package |
| CN110299332A (en) * | 2019-07-19 | 2019-10-01 | 安徽安努奇科技有限公司 | Chip-packaging structure |
| CN111128925B (en) * | 2019-12-27 | 2021-12-24 | 中国电子科技集团公司第十三研究所 | Packaging structure and packaging method of digital circuit |
| US11791232B2 (en) | 2019-12-27 | 2023-10-17 | The 13Th Research Institute Of China Electronics Technology Group Corporation | Packaging structure and packaging method of digital circuit |
| CN111276451A (en) * | 2020-03-26 | 2020-06-12 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure, packaging assembly and packaging method |
| CN112133695B (en) * | 2020-09-07 | 2022-07-01 | 矽磐微电子(重庆)有限公司 | System-in-package structure and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814474A (en) * | 2009-02-20 | 2010-08-25 | 联发科技股份有限公司 | Wire bond chip package |
| KR101237587B1 (en) * | 2011-08-08 | 2013-02-26 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
| KR101238213B1 (en) * | 2011-01-31 | 2013-03-04 | 하나 마이크론(주) | Stack semiconductor package and method of manufacturing the same |
| CN104538375A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Fan-out PoP packaging structure and manufacturing method thereof |
| CN104733463A (en) * | 2013-12-18 | 2015-06-24 | 瑞萨电子株式会社 | Semiconductor device |
| CN105428334A (en) * | 2014-09-15 | 2016-03-23 | 联发科技股份有限公司 | Semiconductor package assembly |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7829998B2 (en) * | 2007-05-04 | 2010-11-09 | Stats Chippac, Ltd. | Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer |
| KR101855294B1 (en) * | 2010-06-10 | 2018-05-08 | 삼성전자주식회사 | Semiconductor package |
-
2016
- 2016-06-15 CN CN201610422460.2A patent/CN105845672B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814474A (en) * | 2009-02-20 | 2010-08-25 | 联发科技股份有限公司 | Wire bond chip package |
| KR101238213B1 (en) * | 2011-01-31 | 2013-03-04 | 하나 마이크론(주) | Stack semiconductor package and method of manufacturing the same |
| KR101237587B1 (en) * | 2011-08-08 | 2013-02-26 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
| CN104733463A (en) * | 2013-12-18 | 2015-06-24 | 瑞萨电子株式会社 | Semiconductor device |
| CN105428334A (en) * | 2014-09-15 | 2016-03-23 | 联发科技股份有限公司 | Semiconductor package assembly |
| CN104538375A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Fan-out PoP packaging structure and manufacturing method thereof |
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