CN105096793B

CN105096793B - Gate driving circuit and its driving method

Info

Publication number: CN105096793B
Application number: CN201410200453.9A
Authority: CN
Inventors: 吴泽宏; 陈炎伯
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2014-05-13
Filing date: 2014-05-13
Publication date: 2017-12-15
Anticipated expiration: 2034-05-13
Also published as: CN105096793A

Abstract

The present invention provides a kind of gate driving circuit and its driving method.Above-mentioned gate driving circuit includes control signal generator and an at least gate channels set.The each of an at least gate channels set has multiple gate channels, and this little gate channels shares a level shifter.Above-mentioned driving method includes starting multiple first control signals of pulses generation and multiple second control signals according to gate drivers, and according to this little first control signal and a little second control signals to determine that the one of which of this little gate channels uses level shifter in a time interval.The quantity of level shifter can so be reduced.

Description

Gate driving circuit and its driving method

Technical field

The invention relates to a kind of display, and in particular to a kind of gate driving circuit and its driving method.

Background technology

Gate driving circuit (Gate Driving Circuit) 100 is for driving display panel (Display Panel the grid of all transistors in every scan line), its typical circuit structure diagram are as shown in Figure 1.Wherein Fig. 1 is only Wherein four ch_1~ch_4 in n gate channels of gate driving circuit 100 are shown, wherein each gate channels include One shift register (Shift Register), a logic unit (Logic Unit), a level shifter (Level Shifter) and one exports buffer cell (Output Buffer).When being intended to show that a picture frame (Image Frame) is being shown During panel (Display Panel, be not shown), timer (Timing controller, be not shown) can export a raster data model Device starts pulse GDSP to gate driving circuit 100.Gate drivers are started arteries and veins by gate channels ch_1 shift register 121 GDSP readings are rushed, and produces delay and starts pulse g1 to logic unit 141, and gate drivers are started into pulse GDSP and transmitted To next stage shift register 122.The operation of remaining shift register 122~124 is referred to shift register 121 and class Push away.Therefore, shift register 121~124 may decide that the drive of every scan line (scan line, be not shown) of display panel Dynamic order simultaneously sequentially produces delay beginning pulse g1~g4, and delay is started into pulse g1~g4 is respectively transmitted to logic unit 141~144.Logic unit 141~144 can be controlled by output enable signal OE and produce first signal LVS1~LVS4, then First signal LVS1~LVS4 is sent to level shifter 161~164 to carry out voltage level processing.After voltage level processing Drive signal HVS1~HVS4 respectively via output buffer cell 181~184 drive respectively on display panel different scanning line Transistor (not shown) grid.Therefore, as seen from Figure 1, typical gate driving circuit 100 is receiving raster data model After device starts pulse GDSP, first signal LVS1~LVS4 can sequentially be transmitted step by step via the shift register of each passage.

Each gate channels (such as ch_1~ch_4 shown in Fig. 1) includes in typical gate driving circuit 100 One level shifter, the first signal received is converted into high-voltage signal output.However, when the number increase of gate channels When, the number of level shifter certainly will increase therewith, will thus increase the cost of gate driving circuit.

The content of the invention

The present invention provides a kind of gate driving circuit and its driving method, effectively reduces the level deviation of gate driving circuit The quantity of device.

One embodiment of the invention provides a kind of gate driving circuit, including control signal generator and at least one first Gate channels set.Control signal generator to receive gate drivers start pulse with produce multiple first control signals with Multiple second control signals.An above-mentioned at least first grid passage set is coupled to control signal generator.Above-mentioned at least 1 The each of one gate channels set each has multiple first grid passages.This little first grid passage is controlled by above-mentioned multiple First control signal and above-mentioned multiple second control signals produce multiple raster data models to share one first level shifter Signal.

In one embodiment of this invention, each of an above-mentioned at least first grid passage set each includes multiple Front passage, one first level shifter and multiple rear end passages.The driving signal output end coupling of this each a little front passage The input of the first level shifter is connected to, wherein this little front passage are mutually concatenated each to receive one in this little front passage The output pulse signal of prime front passage, and this each a little front passage are each controlled by above-mentioned multiple first control signals One of which is to judge whether the input of one first signal output to the first level shifter.This each a little rear end passage Input is couple to the output end of the first level shifter, and this little rear end passage of each of which are each controlled by above-mentioned multiple second The one of which of control signal is to judge whether that the output signal according to the first level shifter produces this little gate drive signal.

In one embodiment of this invention, the control according to the second control signal, this above-mentioned a little rear end passage are wherein One receives the output signal of above-mentioned first level shifter with the corresponding one of which for producing this little gate drive signal, and its Other gate drive signals are maintained a voltage level by his rear end passage.

In one embodiment of this invention, this above-mentioned each a little front passage are each patrolled including a shift register, one Collect unit and a first switch.The output pulse signal that shift register receives prime front passage is postponed with producing one first Start pulse.The input of logic unit is coupled to shift register and starts pulse to receive the first delay.Logic unit foundation An output enable signal from outside carries out a logical operation and produces above-mentioned first signal.The first end coupling of first switch To the output end of logic unit to receive the first signal.Second end of first switch is coupled to the defeated of above-mentioned first level shifter Enter end, wherein first switch is controlled by the one pair of which person of answering of this little first control signal.

In one embodiment of this invention, this above-mentioned each a little front passage are each patrolled including a shift register, one Collect unit and a first switch.The output pulse signal that shift register receives prime front passage is postponed with producing one first Start pulse.The first end of first switch is couple to shift register and starts pulse, wherein first switch to receive the first delay The one pair of which person of answering for being controlled by this little first control signal is used as the second delay correspondingly to export the first delay beginning pulse Start pulse.The second end that the input of logic unit is couple to first switch starts pulse to receive the second delay.Logic list The output end of member is coupled to the input of the first level shifter, and wherein logic unit is according to the output enable signal from outside Start pulse to second delay to carry out logical operation and produce above-mentioned first signal.

In one embodiment of this invention, this above-mentioned each a little front passage each include a shift register and one Logic unit.The output pulse signal that shift register receives prime front passage starts pulse to produce one first delay.Patrol The input of volume unit is couple to shift register and starts pulse to receive the first delay.One output end of logic unit is coupled to The input of first level shifter, wherein logic unit first prolong according to the output enable signal from outside to this Start pulse late to carry out a logical operation and produce above-mentioned first signal, and logic unit is controlled by this little first control signal The one pair of which person of answering with decide whether export the first signal.

In one embodiment of this invention, this above-mentioned each a little front passage each include a shift register and one First switch.Shift register receives the output pulse signal of prime front passage to produce above-mentioned first signal.First switch First end be couple to shift register to receive the first signal.Second end of first switch is coupled to the first level shifter Input, wherein first switch are controlled by the one pair of which person of answering of this little first control signal.

In one embodiment of this invention, this above-mentioned each a little rear end passage each include a second switch and a drive Dynamic voltage hold circuit.The first end of second switch is couple to the output end of the first level shifter, and wherein second switch is controlled In the one pair of which person of answering of this little second control signal.The output end of driving voltage holding circuit is couple to the second of second switch End.When second switch disconnects, the one pair of which person of answering of this little gate drive signal is maintained one by driving voltage holding circuit Voltage level.When second switch turns on, second switch exports the output signal of the first level shifter as this little grid The wherein corresponding person of drive signal.

In one embodiment of this invention, above-mentioned driving voltage holding circuit is opened including a voltage source and one the 3rd Close.The first end of 3rd switch is couple to the second end of above-mentioned second switch, and the second end of the 3rd switch is couple to voltage source, its In the 3rd switch be controlled by this little second control signal wherein corresponding person it is anti-phase.

In one embodiment of this invention, above-mentioned driving voltage holding circuit includes a voltage source and a capacitor. The first end of capacitor is couple to the second end of above-mentioned second switch, and the second end of capacitor is couple to voltage source.

In one embodiment of this invention, this above-mentioned each a little rear end passage also each include an output buffer cell. The input of output buffer cell is couple to the second end of above-mentioned second switch.

In one embodiment of this invention, above-mentioned output buffer cell includes an at least phase inverter.

In one embodiment of this invention, above-mentioned control signal generator includes multiple triggers, an OR gate and more Individual 3rd level shifter.The first input end of OR gate receives gate drivers and starts pulse.This little trigger is producing this A little first control signals.The clock pulse end of this little trigger receives clock signal.The input of the first order trigger of this little trigger End is coupled to the output end of OR gate.The input of each trigger in addition to first order trigger is couple to this little trigger The output end of middle previous stage trigger.Second input of OR gate is couple to the defeated of the afterbody trigger in this little trigger Go out end.The input of each of this little 3rd level shifter each is coupled to the one pair of which person's of answering of this little positive trigger Output end, to produce the one of which of this little second control signal.

One embodiment of the invention provides a kind of driving method of gate driving circuit, and this driving method includes：According to grid Driver starts multiple first control signals of pulses generation and multiple second control signals；And believed according to this little first control Number and this little second control signal, by time sharing shared one first level of multiple first grid passages of first grid passage set Deviator, to produce multiple gate drive signals.

In one embodiment of this invention, in above-mentioned driving method, when this little first grid passage one of which in When in one time interval using the first level shifter, the gate drive signal of each of other first grid passages is maintained In a voltage level.

Based on above-mentioned, the gate driving circuit and its driving method of the embodiment of the present invention are in the first control signal and second Under the control of control signal, multiple first grid passages are shared into first level shifter, can so reduce grid drive The quantity of first level shifter in dynamic circuit.

For features described above of the invention and advantage can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make Carefully it is described as follows.

Brief description of the drawings

Fig. 1 is a kind of circuit diagram of known gate driving circuit；

Fig. 2 is the display system applied according to a kind of gate driving circuit of one embodiment of the invention；

Fig. 3 A are a kind of circuit diagrams of first grid passage set according to one embodiment of the invention；

Fig. 3 B are a kind of time diagrams of gate driving circuit shown in Fig. 3 A；

Fig. 4 is a kind of circuit diagram of first grid passage set according to one embodiment of the invention；

Fig. 5 is the circuit diagram of the logic unit shown in Fig. 4；

Fig. 6 is a kind of circuit diagram of first grid passage set according to one embodiment of the invention；

Fig. 7 is a kind of circuit diagram of first grid passage set according to one embodiment of the invention；

Fig. 8 is a kind of gate driving circuit flow chart according to one embodiment of the invention；

Fig. 9 is the circuit diagram of the control signal generator shown in Fig. 8；

Figure 10 is a kind of gate driving circuit schematic diagram according to one embodiment of the invention；

Figure 11 is a kind of gate driving circuit schematic diagram according to one embodiment of the invention；

Figure 12 is a kind of gate driving circuit schematic diagram according to one embodiment of the invention.

Description of reference numerals：

100：Gate driving circuit；

121~124,221~22n：Shift register；

141~144：Logic unit；

161~164：Level shifter；

181~184：Export buffer cell；

200：First grid passage set

201：End points；

202：First level shifter

211~21n, 411~41n, 611~61n, 711~71n：Front passage；

231~23n：Logic unit；

241~24n：First switch；

251~25n：Rear end passage；

261~26n：Second switch；

271~27n：Driving voltage holding circuit；

281~28n：3rd switch；

291~29n：Export buffer cell；

400：Gate driving circuit；

410：Control signal generator；

421~42M：Gate channels set

521~52n：D flip-flop；

540：OR gate；

561~56n：3rd level shifter；

600：Gate driving circuit；

620、640、660：First grid passage set；

700：Gate driving circuit；

720、740、760：First grid passage set；

800：Gate driving circuit；

820、840、860：First grid passage set；

880：Second grid passage set；

900：Display system；

910：Display panel；

920：Source electrode drive circuit；

930：Gate driving circuit；

982：NAND gate：

984：Transmission gate；

986：Pull-up power supply；

988：Draw power；

CLK：Clock signal

Ch (1)~Ch (M*N)：Gate channels；

DQ1~DQN：First control signal；

GDSP：Gate drivers start pulse；

GL1~GLn：Gate line；

G1~GN：Gate drive signal；

HVS, HVS1~HVSN：High-voltage signal；

HS1~HSN：Second control signal；

HS1B~HSNB：Second control signal it is anti-phase；

LVS1~LVSN：First signal；

LS、LS1、LS2：Level shifter；

OE：Export enable signal；

O1~On：Driving signal output end；

OP_S：Computing signal；

SL1~SLn：Source electrode line；

SP0~SP (N-1)：Output pulse signal；

SFR：Front passage；

T0~TN：Time；

V1~Vn：Voltage source；

Ch_1~ch_n：Gate channels；

G1~gn：First delay starts pulse；

Gs1~gsn：Second delay starts pulse.

Embodiment

" coupling " one word of this case specification in full used in (including claim) can refer to it is any direct or Indirect connection means.For example, if described in the text first device is coupled to second device, should be construed as this first Device can be directly connected to the second device, or the first device can by other devices or certain connection means and Grounding connection is to the second device.In addition, all possible parts, use element/structure of identical label in drawings and the embodiments Part/step represents same or like part.In different embodiments using identical label or using identical term element/component/ Step can be with cross-referenced related description.

Fig. 2 is refer to, Fig. 2 is the display system applied according to a kind of gate driving circuit of one embodiment of the invention System.Display system 900 includes source electrode drive circuit (the Source Driving of a display panel (Display Panel) 910, one Circuit) 920 and a gate driving circuit (Gate Driving Circuit) 930.Source electrode drive circuit 920 and grid Drive circuit 930 be couple to display panel 910 with drive respectively multiple source electrode lines of display panel 910 (such as SL1 shown in Fig. 2, SL2 ..., SLn) with multiple gate lines (such as GL1, GL2 shown in Fig. 2 ..., GLn).Gate driving circuit 930, which includes control, to be believed Number generator 410 and multiple gate channels.These gate channels can each self-driven display panel 910 different gate lines (or Claim scan line).

, can be by raster data model in order to reduce the level shifter of gate driving circuit 930 (Level Shifter) quantity All gate channels of circuit 930 divide group into one or more groups (hereinafter referred to as gate channels set).Each gate channels Set include multiple gate channels ch_1, ch_2 ..., ch_n.The quantity n of gate channels included by one gate channels set It can be determined depending on actual design demand.It is more to produce that the reception gate drivers of control signal generator 410 start pulse GDSP Individual first control signal DQ1~DQn and multiple second control signal HS1~HSN.According to this little first control signal DQ1~DQn With this little second control signal HS1~HSN, this little gate channels ch_1~ch_ of each first grid passage set 200 can be allowed The mutual time sharing shared level shifter of n.Consequently, it is possible to include the grid of an above-mentioned at least first grid passage set 200 Drive circuit 930 will can reach the purpose for the quantity for reducing level shifter.

The circuit that Fig. 3 A, Fig. 3 A are a kind of first grid passage set according to one embodiment of the invention is refer to below Schematic diagram.Can be seen that by Fig. 3 A, first grid passage set 200 have N level gate channels ch_1, ch_2, ch_3 ..., ch_n, And N level gate channels ch_1~ch_n shares mutually first level shifter 202, wherein gate channels ch_1 includes front end Passage 211, the first level shifter 202 and rear end passage 251, gate channels ch_2 include front passage 212, the first level Deviator 202 and rear end passage 252, gate channels ch_3 include front passage 213, the first level shifter 202 and after Passage 253 is held, and gate channels ch_n then includes front passage 21n, the first level shifter 202 and rear end passage 25n.

It is connected in parallel to each other between 211~21n of front passage shown in Fig. 3 A, and 211~21n of front passage multiple drivings letter Number output end O1, O2, O3 ..., On be each coupled to same end point 201.Each front passage can receive prime front passage and be produced Raw output pulse signal to produce one first signal, and multiple first control signals the one pair of which person of answering control it Under, judge whether the input to the first level shifter 202 by first signal output.In order to be easier to understand, one will be entered Step is described as follows.Such as gate channels ch_1 front passage 211 can receive the output pulse of prime front passage (not shown) Signal SP0 determines to produce the first signal LVS1 and output pulse signal SP1, and under the first control signal DQ1 control Whether first signal LVS1 is output to the input of the first level shifter 202, wherein above-mentioned output pulse signal SP0 can be with It is that gate drivers start the pulse GDSP or output pulse signal SPN from a upper gate channels set.Gate channels Ch_2 front passage 212 receives the output pulse signal SP1 of prime front passage (front passage 211) to produce the first signal LVS2 and output pulse signal SP2, and under the first control signal DQ2 control, decide whether the first signal LVS2 is defeated Go out the input to the first level shifter 202.Gate channels ch_3 front passage 213 is that reception prime front passage is (preceding Hold passage 212) output pulse signal SP2 to produce the first signal LVS3 and output pulse signal, and in the first control signal Under DQ3 control, decide whether for the first signal LVS3 to be output to the input of the first level shifter 202.The rest may be inferred, Gate channels ch_n front passage 21n is the output pulse signal SP (N-1) for receiving prime front passage (not shown) with production Raw first signal LVSN and output pulse signal SPN, and under the first control signal DQN control, decide whether first Signal LVSN is output to the input of the first level shifter 202.

The input of the first level shifter 202 shown in Fig. 3 A is couple to end points 201.First level shifter 202 Output end is couple to rear end 251~25n of passage input.First signal of the receiving endpoint 201 of the first level shifter 202 with Boosted and produce a high-voltage signal HVS to rear end 251~25n of passage input.

Rear end 251~25n of passage shown in Fig. 3 A to produce multiple gate drive signal G1, G2, G3 ..., GN.More Individual second control signal HS1, HS2, HS3 ..., under HSN control, 251~25n of this little rear end passage one of which can be each From wherein the one of the high-voltage signal HVS generation gate drive signals G1~GN judged whether according to the first level shifter 202 Person, and other gate drive signals then maintain a voltage level.It is further described below, such as gate channels ch_1 rear end Passage 251 under the second control signal HS1 control, decide whether by this high-voltage signal HVS export to display panel 910 with As gate drive signal G1.Gate channels ch_2 rear end passage 252, can be with the second control signal HS2 control Decide whether to export this high-voltage signal HVS to display panel 910 with as gate drive signal G2.After gate channels ch_3 Passage 253 is held to decide whether to export this high-voltage signal HVS to display panel 910 under the second control signal HS3 control With as the 3rd gate drive signal G3.By that analogy, gate channels ch_n rear end passage 25n is the second control signal HSN's Under control, decide whether to export this high-voltage signal HVS to display panel 910 with as gate drive signal GN.

In certain embodiments, a little 211~21n of front passage of this shown in Fig. 3 A can be respectively provided with it is substantially the same (or It is similar) structure and function.In one embodiment of this invention, front passage 211 includes shift register 221, logic unit 231 and first switch 241.Shift register 221 receive previous stage front passage (not shown) output pulse signal SP0 with Produce the first delay and start pulse g1 and output pulse signal SP1.Logic unit 231 receives the first delay and starts pulse g1.Patrol Collect unit 231 and carry out logical operation according to the output enable signal OE from outside, and produce the first signal LVS1.In the present invention An embodiment in, above-mentioned logic unit 231 can be with NAND gate (NAND gate), transmission gate or other on-off circuits come real It is existing, but the present invention is not limited thereto.As an example it is assumed that realize logic unit 231 with NAND gate, then the first of this NAND gate Input and the second input can distinguish the delays of Rreceive output enable signal OE and first and start pulse g1, and this NAND gate Output end exports the first signal LVS1.First switch 241 is controlled by the wherein control signal DQ1 of the first control signal to determine Whether first switch 241 turns on.When first switch 241 turns on, the first signal LVS1 can be transferred into the first level deviation The input of device 202.

Front passage 212 includes shift register 222, logic unit 232 and first switch 242.Front passage 213 is wrapped Include shift register 223, logic unit 233 and first switch 243.Front passage 21n includes shift register 22n, logic Unit 23n and first switch 24n.212~21n of front passage embodiment refers to the described above of front passage 211 And analogize, it will not be repeated here.

In certain embodiments, 251~25n of a little rear end passages of this shown in Fig. 3 A can be respectively provided with it is substantially the same (or It is similar) structure and function.In one embodiment of this invention, rear end passage 251 includes second switch 261, driving voltage is protected Hold circuit 271 and output buffer cell 291.The first end of second switch 261 is coupled to the output of the first level shifter 202 Hold to receive high-voltage signal HVS.The control terminal of second switch 261 is controlled by wherein one corresponding control of this little second control signal Signal HS1 is to determine whether second switch 261 turns on.Driving voltage holding circuit 271 is couple to the second of second switch 261 End.The input of output buffer cell 291 is coupled to the second end of second switch 261, and exports the output end of buffer cell 291 It is coupled to a wherein gate line for display panel 910.When second switch 261 disconnects, driving voltage holding circuit 271 can be with Gate drive signal G1 is maintained at a voltage level.When second switch 261 turns on, output buffer cell 291 can receive The high-voltage signal HVS of first level shifter 202 is to produce the 1st gate drive signal G1.That is, second switch 261 can So that the output signal of the first level shifter 202 to be exported gate drive signal G1 is used as to output buffer cell 291.

In different embodiments of the invention, driving voltage holding circuit 271 can be realized with various ways.Such as Fig. 3 A In illustrated embodiment, driving voltage holding circuit 271 may include the 3rd 281 and voltage source V1 of switch.The of 3rd switch 281 One end is respectively coupled to voltage source V1 and second switch 261 the second end with the second end.3rd switch 281 be controlled by those second The anti-phase HS1B of the one pair of which person of answering of control signal.That is, when second switch 261 turns on, the 3rd switch 281 is to disconnect, such as This one can receive the high-voltage signal HVS of the first level shifter 202 to produce gate drive signal to export buffer cell 291 G1；Conversely, when second switch 261 disconnects, the 3rd switch 281 is conducting, then it is receiving voltage source V1 to export buffer cell 291 Voltage signal, gate drive signal G1 is maintained into a voltage level.In addition, voltage source V1 voltage level can regard in fact Border design requirement determines.For example, voltage source V1 can be operating voltage source (system voltage source) or ground voltage supplies.

In other embodiments, the 3rd switch 281 can also electricity container substitute.If with the switch of capacitor substitution the 3rd 281, then the first end of this capacitor and the second end are respectively coupled to voltage source V1 and second switch 261 the second end.Voltage source V1 can be operating voltage source, ground voltage supplies or other any fixed reference potentials.

In addition, in another embodiment of the invention, the output buffer cell 291 of rear end passage 251 is including at least one Phase inverter, but should not be as limit.Such as in another embodiment of the invention, the output buffer cell of rear end passage 251 291 may also omit and not have to.In other embodiments, the phase inverter of buffer cell 291 is exported shown in Fig. 3 A and can also be used and is delayed Device, module gain buffer (unity gain buffer) or other gain circuitries are rushed to substitute.

Rear end passage 252 includes second switch 262, driving voltage holding circuit 272 and output buffer cell 292.Afterwards Passage 253 is held to include second switch 263, driving voltage holding circuit 273 and output buffer cell 293.Rear end passage 25n bags Include second switch 26n, driving voltage holding circuit 27n and output buffer cell 29n.Rear end 252~25n of passage embodiment party Formula refers to the described above of rear end passage 251 and analogized, and will not be repeated here.

Fig. 3 B are a kind of time diagrams of gate driving circuit shown in Fig. 3 A.Referring to Fig. 3 A and Fig. 3 B, During time T0, the gate channels ch_1 of first grid passage set 200 receives the output pulse signal of previous stage gate channels SP0.The shift register 221 of gate channels ch_1 front passage 211 can be according to output pulse signal SP0 and in time T1 Produce the first delay and start pulse g1 and output pulse signal SP1.Logic unit 231 receives the first delay and starts pulse g1 with coming From outside output enable signal OE with carry out logical operation and produce the first signal LVS1.It is worth noting that, in time T1 During T2, the first control signal DQ1 and the second control signal HS1 that are input to gate channels ch_1 are enabled status (being, for example, logic high), and the controls of other gate channels ch_2~ch_n first control signal DQ2~DQN and second are believed Number HS2~HSN is illegal state (being, for example, logic low), therefore gate channels ch_1 first switch 241 and the Two switches 261 are switched on, and the 3rd switch 281 is disconnected, and remaining gate channels ch_2~ch_n first switch 242~ 24n and 262~26n of second switch is disconnected and the 3rd 282~28n of switch is switched on.Consequently, it is possible to the first level shifter 202 give the first signal LVS1 for receiving gate channels ch_1 to gate channels ch_1 to be boosted and produced high-voltage signal HVS Rear end passage 251, and export buffer cell 291 by gate channels ch_1 second switch 261 receive high-voltage signal HVS with Produce gate drive signal G1.During time T1 to T2,292~29n of output buffer cell then distinguishes receiving voltage source V2 ~Vn voltage signal is so that gate drive signal G2~GN is maintained on a fixed voltage level (such as logic low).

In time T2, the gate channels ch_2 of first grid passage set 200 receives gate channels ch_1 output Pulse signal SP1.The shift register 222 of gate channels ch_2 front passage 212 can according to output pulse signal SP1 and in The first delay is produced during time T2 and starts pulse g2 and output pulse signal SP2, as shown in Figure 3 B.Logic unit 232 receives the One delay starts the pulse g2 and output enable signal OE from outside to carry out logical operation and produce the first signal LVS2.Value Obtain it is noted that during time T2 to T3, the controls of the first control signal DQ2 and second for being input to gate channels ch_2 are believed Number HS2 is enabled status (being, for example, logic high), and other gate channels ch_1, ch3~ch_n the first control signal DQ1, DQ3~DQN and the second control signal HS1, HS3~HSN are illegal state (are, for example, logic low), therefore grid Passage ch_2 first switch 242 and second switch 262 is switched on, and the 3rd switch 282 is disconnected, and remaining gate channels Ch_1, ch_3~ch_n first switch 241,243~24n and second switch 261,263~26n are disconnected, and the 3rd opens 281,283~28n is closed to be switched on.Consequently, it is possible to the first level shifter 202 will receive gate channels ch_2 the first signal LVS2 exports buffer cell 292 to be boosted and produced rear end passages 252 of the high-voltage signal HVS to gate channels ch_2 High-voltage signal HVS is received to produce gate drive signal G2 by gate channels ch_2 second switch 262.In time T2 to T3 During, output buffer cell 291,293~29n then respectively receiving voltage source V1, V3~Vn voltage signal so that grid to be driven Dynamic signal G1, G3~GN maintain a fixed voltage level (such as logic low).The set 200 of first grid passage is in the time T3~TN running refers to the explanation of the above-mentioned running in time T1 or T2 and analogized, and will not be repeated here.It is from the foregoing, it will be observed that logical This little first control signal DQ1~DQN and this little second control signal HS1~HSN control are crossed, multiple grids can be reached Passage ch_1~ch_n shares the purpose of a level shifter 202.

Next Fig. 4 is refer to, Fig. 4 is a kind of circuit of first grid passage set according to one embodiment of the invention Schematic diagram.Embodiment illustrated in fig. 4 is referred to Fig. 3 A and Fig. 3 B related description and analogized.Compared to Fig. 3 A, Fig. 4 front end leads to Road 411,412,413 ... ,~41n 231~23n of logic unit and 241~24n of first switch position and Fig. 3 A it is different. In the present embodiment, 411~41n of front passage is respectively provided with the structure and function of substantially the same (or similar).Below only with Fig. 4's Front passage 411 illustrates, and 412~41n of remaining front passage is referred to the related description of front passage 411 and analogizes.

Front passage 411 includes shift register 221, first switch 241 and logic unit 231.Shift register 221 The output pulse signal SP0 for receiving prime front passage (not shown) starts pulse g1 and output pulse to produce one first delay Signal SP1.First switch 241 be controlled by corresponding to this little first control signal one of which DQ1 to decide whether first Delay starts pulse g1 and transmitted to the input of logic unit 231 as the second delay beginning pulse gs1.Logic unit 231 connects Receive the second delay and start the pulse gs1 and output enable signal OE from outside to carry out logical operation and produce the first signal LVS1.Because the function of Fig. 4 first grid passage set 200 is similar with Fig. 3 A with mode of operation, therefore it is operated in detail Above-mentioned Fig. 3 A explanation is referred to, will not be repeated here.

In one embodiment of this invention, Fig. 4 231~23n of logic unit can with a NAND gate and a transmission gate come Realize, as shown in Figure 5.Logic unit 231 includes a NAND gate 982, a transmission gate 984, a pull-up power supply 986 and a drop-down Power supply 988.The output end of NAND gate 982 is couple to the input of transmission gate 984.The output end of transmission gate 984 is as logic list Member 231 output end and be couple to the input of the first level shifter 202.The inverted control terminals of transmission gate 984 are couple to Draw power supply 986 and be controlled by the second delay and start pulse gs1.The noninverting control terminal of transmission gate 984 is couple to draw power 988 And it is controlled by the second delay and starts pulse gs1.NAND gate 982 receives the output enable signal OE from outside and opened with the second delay Initial pulse gs1 is to produce the first signal LVS1.It is a high impedance signal or suspension joint when the second delay starts pulse gs1 (floating) when (when first switch 241 disconnects), the noninverting control terminal of transmission gate 984 is pulled down power supply 988 and is pulled down to Logic low and inverted control terminals are pulled up power supply 986 and are pulled to logic high, therefore the output end of transmission gate 984 is height Resistance state is without exporting the first signal LVS1.Conversely, when the second delay beginning pulse gs1 is located at logic high, transmission The level of the noninverting control terminal of door 984 is logic high, therefore transmission gate 984 can transmit the first signal LVS1 to first The input of level shifter 202.When the second delay, which starts pulse gs1, is located at logic low, the anti-phase control of transmission gate 984 The level at end processed is logic low, therefore transmission gate 984 can transmit the first signal LVS1 to the first level shifter 202 Input.

Next Fig. 6 is refer to, Fig. 6 is that a kind of circuit of the first grid passage set implemented according to the present invention shows It is intended to.Embodiment illustrated in fig. 6 is referred to Fig. 3 A and Fig. 3 B related description and analogized.Compared to Fig. 3 A, the front end shown in Fig. 6 Passage 611,612,613 ..., 61n 231~23n of logic unit has switching function, therefore can omit shown in Fig. 3 A first and open Close 241~24n.In the present embodiment, 611~61n of front passage is respectively provided with the structure and function of substantially the same (or similar). Only illustrated below with Fig. 6 front passage 611, and 612~61n of remaining front passage is referred to the phase of front passage 611 Speak on somebody's behalf bright and analogize.

Front passage 611 includes shift register 221 and logic unit 231, and wherein shift register 221 receives prime The output pulse signal SP0 of front passage (not shown) starts pulse g1 and output pulse signal SP1 to produce one first delay. The input of logic unit 231 is couple to shift register 221 and starts pulse g1 to receive the first delay.Logic unit 231 Output end is coupled to the input of the first level shifter 202.Logic unit 231 is according to the output enable signal OE from outside Start pulse g1 to the first delay to carry out logical operation and produce the first signal LVS1.Logic unit 231 be controlled by corresponding to this Whether the one of which DQ1 of a little first control signals exports the first signal LVS1 with decision logic unit 231.Work as logic unit During 231 conducting, then the first signal LVS1 is exported.Due to Fig. 6 first grid passage set 200 function and mode of operation with Fig. 3 A are identical, therefore its Detailed Operation refers to above-mentioned Fig. 3 A explanation, will not be repeated here.

Fig. 7 is refer to, Fig. 7 is a kind of circuit signal of first grid passage set according to one embodiment of the invention Figure.Embodiment illustrated in fig. 7 is referred to Fig. 3 A and Fig. 3 B related description and analogized.Compared to Fig. 3 A, Fig. 7 front passage 711st, 712,713 ..., 71n eliminates logic unit.In the present embodiment, 711~71n of front passage is respectively provided with substantial phase With structure and function, therefore it is following only illustrated with Fig. 7 front passage 711, and 712~71n of remaining front passage can be with Analogize with reference to the related description of front passage 711.

Front passage 711 includes shift register 221 and first switch 241.Shift register 221 receives prime front end The output pulse signal SP0 of passage (not shown) is to produce the first signal LVS1.First switch 241 is controlled by this little first control The one pair of which person of the answering DQ1 of signal is to determine whether first switch 241 turns on.When first switch 241 turns on, the shift LD First signal LVS1 of device 221 is transferred to the input of level shifter 202.Due to Fig. 7 first grid passage set 200 Function it is identical with Fig. 3 A with mode of operation, therefore its Detailed Operation refers to above-mentioned Fig. 3 A explanation, will not be repeated here.

Next Fig. 8 is refer to, Fig. 8 is a kind of gate driving circuit flow chart according to one embodiment of the invention.Fig. 8 Illustrated embodiment is referred to Fig. 2 related description and analogized.Gate driving circuit 400 include control signal generator 410 with And 421~42M of multiple gate channels set, wherein control signal generator 410 receive gate drivers start pulse GDSP with Produce multiple first control signal DQ1~DQN and multiple second control signal HS1~HSN, and by this little first control signal DQ1~DQN and this little second control signal HS1~HSN be sent to gate channels set 421,422,423 ..., 42M it is every One.Wherein 421~42M of gate channels set embodiment is referred to Fig. 3 A and analogized to Fig. 7 related description.Example Such as, the circuit structure of 421~42M of this little gate channels set each is that the shared level of every N levels gate channels is inclined Move device.Due to shared M group gate channels set, so M*N raster data model passage can be provided altogether, but this M*N grid Passage only uses M level shifter, therefore can reach the purpose for the number for reducing level shifter.It is to be understood that M can be with 1 integer is greater than, the present invention is not intended to limit 421~42M of gate channels set quantity M.In addition, the present invention is not intended to limit often The quantity N of gate channels, i.e. the first grid passage of this little first grid passage set number in one gate channels set Can be different.

In addition, the M group gate channels set shown in Fig. 8 can be that gate channels set as shown in Figure 1 (calls in the following text Two gate channels set) combined with the arbitrary arrangement of the first grid passage set shown in Fig. 3 A, Fig. 4, Fig. 6~Fig. 7.For example, Gate channels set 421 is second grid passage set as shown in Figure 1, and 422~42M of remaining gate channels set is such as figure First grid passage set shown in 3A, Fig. 4, Fig. 6~Fig. 7.Or gate channels set 421,423 etc. is marked as odd number Gate channels set is the first grid passage set 200 as shown in Fig. 3 A, Fig. 4, Fig. 6~Fig. 7, and remaining is marked as even number Gate channels set is second grid passage set as shown in Figure 1, but the present invention is not limited thereto.

In addition, each gate channels set shown in Fig. 8 (can also call second gate in the following text by gate channels as shown in Figure 1 Pole passage) formed with the first grid passage shown in Fig. 3 A, Fig. 4, Fig. 6~Fig. 7 in a manner of replacing or be continuous, i.e., each grid Unlimited pole passage set is entirely first grid passage or second grid passage surely, for example, the of gate channels set 421 1 to the 4th gate channels ch_1~ch_4 is second grid passage as shown in Figure 1, and remaining gate channels be then as Fig. 3 A, First grid passage shown in Fig. 4, Fig. 6~Fig. 7, but the present invention is not limited thereto.

Fig. 9 is refer to, Fig. 9 is the circuit diagram of the control signal generator 410 shown in Fig. 8.Control signal generator 410 providing first control signal DQ1~DQN and second control signal HS1~HSN as shown in Figure 3 B.Control signal is produced Raw device 410 include multiple triggers (such as D flip-flop 521 shown in Fig. 9,522,523 ..., 52n), an OR gate 540 and more Individual 3rd level shifter (such as the 3rd level shifter 561 shown in Fig. 9,562,563 ..., 56n).This little D flip-flop 521~52n is producing multiple first control signal DQ1~DQN.Each D flip-flop has a clock pulse end CK, an input A D and output end Q.521~52n of D flip-flop each clock pulse end CK receives clock signal CLK.D flip-flop 521 The input D of first order D flip-flop 521 in~52n is coupled to the output end of OR gate 540 to receive a computing signal OP_ S.Each (such as third level D flip-flop of 522~52n of D flip-flop in addition to first order D flip-flop 521 523) input D is concatenated into the output end Q of its previous stage D flip-flop (such as second level D flip-flop 522).OR gate 540 First input end receive gate drivers start pulse GDSP.Second input of OR gate 540 be couple to trigger 521~ The output end Q of afterbody D flip-flop 52n in 52n is with Rreceive output signal DQN.OR gate 540 is carried out or computing and produced Computing signal OP_S.3rd 561~56n of level shifter input is respectively coupled to the defeated of the positive 521~52n of trigger of D types Go out to hold Q, to produce multiple second control signal HS1~HSN.

Figure 10~Figure 12 is a kind of gate driving circuit schematic diagram according to different embodiments of the invention.On reading It is convenient, in Figure 10~embodiment illustrated in fig. 12, each front passage is represented with SFR, and represent each with phase inverter symbol Rear end passage.Before front passage SFR shown in Figure 10~Figure 12 is referred to shown in 211~21n of front passage, Fig. 4 shown in Fig. 3 A Hold the related description of 711~71n of front passage shown in front passage 611~61n and/or Fig. 7 shown in 411~41n of passage, Fig. 6 And analogize.Rear end passage shown in Figure 10~Figure 12 (i.e. phase inverter symbol shown in Figure 10~Figure 12) is referred to rear end shown in Fig. 3 A 251~25n of passage related description and analogize.

Gate driving circuit 600 shown in Figure 10 is referred to gate driving circuit 930 shown in Fig. 2, raster data model shown in Fig. 8 The related description of circuit 400 and analogize.In the embodiment shown in fig. 10, gate driving circuit 600 has 3 groups or more groups first Gate channels set (such as set of first grid passage shown in Figure 10 620,640 and 660).First grid passage set 620, 640 and 660 each have 4 first grid passages in any one first grid passage set, and 4 first grid passages share One the first level shifter LS1.

Gate driving circuit 700 shown in Figure 11 is referred to gate driving circuit 930 shown in Fig. 2, raster data model shown in Fig. 8 The related description of circuit 400 and analogize.In the embodiment shown in fig. 11, gate driving circuit 700 has 3 groups or more groups first Gate channels set (such as set of first grid passage shown in Figure 11 720,740 and 760).First grid passage set 720, 740 and 760 each have the gate channels of varying number.For example, there are 4 first grids to lead to for first grid passage set 720 Road, first grid passage set 740 have 3 first grid passages, and first grid passage set 760 has 4 first Gate channels.4 first grid passages of first grid passage set 720 share a first level shifter LS1, the first grid 3 first grid passages of pole passage set 740 share a first level shifter LS1, and first grid passage set 760 4 first grid passages share a first level shifter LS1.

Gate driving circuit 800 shown in Figure 12 is referred to gate driving circuit 930 shown in Fig. 2, raster data model shown in Fig. 8 The related description of circuit 400 and analogize.In the embodiment shown in fig. 12, gate driving circuit 800 has 4 groups or more group grids Passage set (such as gate channels set shown in Figure 12 820,840,860 and 880).Gate channels set 820,840,860 with 880 each have the gate channels of varying number.For example, first grid passage set 820 has 4 first grid passages, the One gate channels set 840 has 3 first grid passages, and first grid passage set 860 has 2 first grid passages, And second grid passage set 880 has 1 second grid passage.4 first grids of first grid passage set 820 lead to Road shares a first level shifter LS1, and 3 first grid passages of first grid passage set 840 share one first Level shifter LS1, the shared level shifter LS1 of 2 first grid passages of first grid passage set 860, and the 1 second grid passage of two gate channels set 880 uses a second electrical level deviator LS2.

In addition, one embodiment of the invention also provides a kind of driving method of gate driving circuit, wherein above-mentioned grid Pole drive circuit is to produce multiple gate drive signals.This gate driving circuit is including a control signal generator and extremely A few first grid passage set.Each at least first grid passage set has multiple first grid passages.Above-mentioned grid The driving method of drive circuit includes starting multiple first control signals of pulses generation and multiple the according to a gate drivers Two control signals, further according to those first control signals and those second control signals, by same first grid channel set This little time sharing shared one first level shifter of first grid passage closed, and produce this little gate drive signal.In some realities Apply in example, when the one of which of first grid passage is when the first level shifter is used in above-mentioned time interval, by other The gate drive signal of each of one gate channels maintains a voltage level.

In summary, gate driving circuit is divided at least one group by embodiments of the invention, and each group includes more Individual gate channels are to form a gate channels set.The whole or part gate channels for belonging to same gate channels set can Share a level shifter.Consequently, it is possible to the gate driving circuit comprising at least one above-mentioned gate channels set can then reduce Level shifter quantity.

Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to The technical scheme described in foregoing embodiments can so be modified, either which part or all technical characteristic are entered Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology The scope of scheme.

Claims

A kind of 1. gate driving circuit, it is characterised in that including：

Control signal generator, receive gate drivers and start pulse to produce multiple first control signals and the multiple second controls Signal；And

An at least first grid passage set, is coupled to the control signal generator, an at least first grid passage set Each each has multiple first grid passages, and the multiple first grid passage is controlled by the multiple first control signal And the multiple second control signal and produces multiple gate drive signals to share the first level shifter.
2. gate driving circuit according to claim 1, it is characterised in that the multiple first grid passage includes：

First level shifter；

Multiple front passages, the driving signal output end of each of the multiple front passage are couple to first level deviation The input of device, led to wherein the multiple front passage mutually concatenates with each receiving prime front end in the multiple front passage The output pulse signal in road, and each of the multiple front passage is each controlled by its of the multiple first control signal Middle one is to judge whether the input of the first signal output to first level shifter；And

Multiple rear end passages, the input of each of the multiple rear end passage are couple to the output of first level shifter End, wherein each of the multiple rear end passage is each controlled by the one of which of the multiple second control signal to judge Whether according to the output signal of first level shifter the multiple gate drive signal is produced.
3. gate driving circuit according to claim 2, it is characterised in that the control according to the multiple second control signal System, the one of which of the multiple rear end passage receive the output signal of first level shifter with it is corresponding produce it is described more The one of which of individual gate drive signal, other the multiple rear end passages maintain other the multiple gate drive signals Logic low.
4. gate driving circuit according to claim 2, it is characterised in that each of the multiple front passage is each Including：

Shift register, the output pulse signal for receiving the prime front passage start pulse to produce the first delay；

Logic unit, its input are coupled to the shift register and start pulse, wherein the logic list to receive first delay Member carries out logical operation according to the output enable signal from outside and produces first signal；And

First switch, its first end are coupled to the output end of the logic unit to receive first signal, and the of the first switch Two ends are coupled to the input of first level shifter, and the wherein first switch is controlled by the multiple first control signal One of corresponding person.
5. gate driving circuit according to claim 2, it is characterised in that each of the multiple front passage is each Including：

Shift register, the output pulse signal for receiving the prime front passage start pulse to produce the first delay；

First switch, its first end are couple to the shift register and start pulse to receive first delay, and wherein this first is opened Close be controlled by one of corresponding person of the multiple first control signal using it is corresponding export first delay start pulse as Second delay starts pulse；And

Logic unit, the second end that its input is couple to the first switch start pulse, the logic to receive second delay The output end of unit is coupled to the input of first level shifter, and wherein the logic unit is according to the output from outside Enable signal, which starts pulse to second delay, to carry out logical operation and produces first signal.
6. gate driving circuit according to claim 2, it is characterised in that each of the multiple front passage is each Including：

Shift register, the output pulse signal for receiving the prime front passage start pulse to produce the first delay；And

Logic unit, its input are couple to the shift register and start pulse to receive first delay, the logic unit Output end is coupled to the input of first level shifter, and the wherein logic unit is believed according to the output enable from outside Number starting pulse to first delay carries out logical operation and produces first signal, and the logic unit be controlled by it is the multiple One of corresponding person of first control signal is to decide whether to export first signal.
7. gate driving circuit according to claim 2, it is characterised in that each of the multiple front passage is each Including：

Shift register, the output pulse signal of the prime front passage is received to produce first signal；And

First switch, its first end are couple to the shift register to receive first signal, the second end coupling of the first switch The input of first level shifter is connected to, the wherein first switch is controlled by the multiple first control signal wherein One corresponding person.
8. gate driving circuit according to claim 2, it is characterised in that each of the multiple rear end passage is each Including：

Second switch, its first end are couple to the output end of first level shifter, and the wherein second switch is controlled by institute State one of corresponding person of multiple second control signals；And

Driving voltage holding circuit, the output end of the driving voltage holding circuit are couple to the second end of the second switch,

Wherein when the second switch disconnects, the driving voltage holding circuit by the multiple gate drive signal one of them Corresponding person maintains logic low, and when the second switch turns on, and the second switch is by first level shifter The output signal exports wherein corresponding person as the multiple gate drive signal.
9. gate driving circuit according to claim 8, it is characterised in that the driving voltage holding circuit includes：

Voltage source；And

3rd switch, its first end are couple to second end of the second switch, and the second end of the 3rd switch is couple to the electricity Potential source, the wherein the 3rd switch are controlled by the anti-phase of the wherein corresponding person of the multiple second control signal.
10. gate driving circuit according to claim 9, it is characterised in that the voltage source is ground voltage supplies or behaviour Make voltage source.
11. gate driving circuit according to claim 8, it is characterised in that the driving voltage holding circuit includes：

Voltage source；And

Capacitor, its first end is couple to second end of the second switch, and the second end of the capacitor is couple to the voltage Source.
12. gate driving circuit according to claim 8, it is characterised in that each of the multiple rear end passage is also Each include：

Buffer cell is exported, its input is couple to second end of the second switch.
13. gate driving circuit according to claim 12, it is characterised in that the output buffer cell includes at least one Phase inverter.
14. gate driving circuit according to claim 1, it is characterised in that the control signal generator includes：

OR gate, the first input end of the OR gate receive the gate drivers and start pulse；

Multiple triggers, received to produce the clock pulse end of the multiple first control signal, the multiple trigger each Clock signal, the input of the first order trigger of the multiple trigger are coupled to the output end of the OR gate, except this first The input of each of the multiple trigger outside level trigger is couple to the prime triggering in the multiple trigger Second input of the output end of device, the wherein OR gate is couple to the output of the afterbody trigger of the multiple trigger End；And

Multiple 3rd level shifters, the input of each of the multiple 3rd level shifter each are coupled to described more Output end of one of corresponding person of individual trigger, to produce the one of which of the multiple second control signal.
15. gate driving circuit according to claim 1, it is characterised in that in an at least first grid passage set First grid passage number it is different from each other.
16. gate driving circuit according to claim 1, it is characterised in that an at least first grid passage set Each also has an at least second grid passage, and each of an at least second grid passage each has non-common Second electrical level deviator.
17. gate driving circuit according to claim 1, it is characterised in that also include：

An at least second grid passage set,

The wherein each of an at least second grid passage set each includes an at least second grid passage, and this at least one The each of second grid passage each has the second electrical level deviator of non-common.
18. a kind of driving method of gate driving circuit, it is characterised in that the driving method of the gate driving circuit includes：

Start multiple first control signals of pulses generation and multiple second control signals according to gate drivers；And

According to the multiple first control signal and the multiple second control signal, by the multiple of first grid passage set Time sharing shared first level shifter of first grid passage, to produce multiple gate drive signals.
19. the driving method of gate driving circuit according to claim 18, it is characterised in that when the multiple first grid The one of which of pole passage is when first level shifter is used in time interval, by other the multiple first grid passages The gate drive signal of each maintain logic low.