CN105070682A - Method of preparing silicon switch plate efficiently - Google Patents
Method of preparing silicon switch plate efficiently Download PDFInfo
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- CN105070682A CN105070682A CN201510423748.7A CN201510423748A CN105070682A CN 105070682 A CN105070682 A CN 105070682A CN 201510423748 A CN201510423748 A CN 201510423748A CN 105070682 A CN105070682 A CN 105070682A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Abstract
The invention discloses a method of preparing a silicon switch plate efficiently, comprising the steps of: 1) spin coating a photoresist, photoetching and developing; 2) etching; 3) oxidation; 4) sputtering seed layers such as Ti/Cu, etc. 5) bonding a dry film photoresist, photoetching and developing; 6) filling a TSV; and 7) removing of the photoresist and seed layers, wherein the prepared Cu-TSV and Cu-Pad are in flawless connection. The method can prepare a silicon switch plate with higher efficiency and lower preparation cost, and has the characteristics of firm bonding and more flexible preparation processes.
Description
Technical field
The present invention relates to microelectronics Packaging field, particularly, relate to the preparation method of the efficient silicon substrate pinboard that a kind of Cu-TSV and TSV-Pad generates simultaneously continuously.
Background technology
The three-dimension packaging (3D-TSV) of silicon through hole has high-speed interconnect, High Density Integration, miniaturization, provides the advantage such as homogeneity and heterogeneous Function Integration Mechanism simultaneously, becomes the research direction that semiconductor technology is the most popular in recent years.Although 3D-TSV encapsulation technology has many advantages, still there is the development of some unfavorable factors restriction 3D-TSV technology at present.Specifically comprise: the thermomechanical problem that the disappearance of design software and method, power density increase and cause, critical process and plant issue and a system testing difficult problem etc.Wherein, 3D-TSV encapsulates the key process technology related to and comprises: the etching of high-aspect-ratio (TSV diameter/TSV degree of depth) TSV, flawless deep hole TSV plating, wafer thinning techniques, multilayer are aimed at and bonding techniques etc.These techniques not yet full maturity, thus constrain the application & development of 3D encapsulation technology.
Reliability is a huge challenge for 3D-TSV encapsulation technology.The failure mode of 3D-TSV encapsulation technology mainly thermomechanical load causes, comprise the inefficacy of solder joint, the inefficacy of TSV itself, chip break and fatigue failure, layering and crackle etc. between interface.No matter first via process or after via process, Cu-TSV and TSVPad completes step by step.Thermal stress between Cu-TSV and TSV-Pad between Presence of an interface, and TSV filling is blind hole filling, needs to carry out wafer reduction process after having electroplated.At wafer thinning process, the accumulation of residual stress, will directly affect thermo mechanical stability and the electrical property of TSV.
Summary of the invention
For the shortcoming preparing TSV in above-mentioned traditional handicraft, the present invention proposes a kind of method efficiently preparing silicon keyset.The Seed Layer suppressing copper to be deposited on beyond TSV-Pad by dry film photoresist is surperficial.TSV copper column and Pad are formed in filling perforation process simultaneously, thus make Cu-TSV and TSV-Pad have no time to connect.Save the processes such as wafer is thinning, wafer holds, enhance the reliability of 3D-TSV encapsulation simultaneously.
For achieving the above object, the present invention realizes by the following technical solutions:
Efficiently prepare a method for silicon keyset, complete according to the following steps:
Said method comprising the steps of:
1) by positive for spin coating on Silicon Wafer more than 10 μm glue or more than 10 μm negative glue, with baking oven or hot plate drying glue, photoetching and development are carried out to the silicon chip having dried glue;
2) deep reaction ion etching technology is adopted through step 1) silicon chip that processes etches the silicon through hole TSV of different-diameter and the degree of depth;
3) through step 2) silicon chip surface that processes is oxidized, and the thickness be oxidized is more than 0.2 μm;
4) through step 3) Seed Layer of the silicon chip surface that processes and through-hole inner surface sputtered with Ti/Cu;
5) at silicon chip surface bonding dry film photoresist, then photoetching and development is carried out;
6) electroplating technology filling silicon through holes TSV is adopted;
7) by step 6) in the silicon through hole TSV silicon chip for preparing, remove photoresist with sodium hydroxide solution and use washed with de-ionized water, use the mixed liquor of ammoniacal liquor and hydrogen peroxide remove Cu Seed Layer and use washed with de-ionized water, Cu-TSV and the Cu-Pad of preparation has no time to connect.
Preferably, in the described step 3 of execution), adopt 800 DEG C of-1200 DEG C of high-temperature oxydations or chemical deposition technique to be oxidized silicon chip surface; Silicon dioxide thickness is 0.1-3 μm.
Preferably, in the described step 5 of execution) time, adopt heat pressing process at silicon face bonding dry film photoresist.
Preferably, in the described step 5 of execution) time, the thickness of dry film photoresist is 10-200 μm.
Preferably, in the described step 6 of execution) time, adopt two copper coins or phosphorous copperplate as anode.
Preferably, in the described step 6 of execution) time, Cu-TSV and TSV-Pad is electroforming simultaneously.
Preferably, in the described step 7 of execution) time, the mass concentration of sodium hydrate aqueous solution is 5% ~ 40%, and in the mixed liquor of ammoniacal liquor and hydrogen peroxide, ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1 ~ 1:1.
Preferably, in the described step 1 of execution) time, the positive glue of spin coating is positive glue 5-30 μm or negative glue 10-60 μm.
Preferably, in the described step 4 of execution) time, adopt sputtering method depositing Ti/Cu Seed Layer.
Additive used in the present invention comprises accelerator, inhibitor, poising agent, plating before three kinds of additives are added in plating solution, be used for control plating Cu speed, prepare without hole Cu-TSV.The depth-to-width ratio of the Cu-TSV of preparation is 0.5 ~ 30.Especially, Cu-TSV and the Cu-Pad that prepared by the present invention has no time to connect.
Compared with existing TSV technology, the invention has the beneficial effects as follows:
The present invention can prepare a kind of silicon substrate pinboard efficiently on Silicon Wafer, and this Cu-TSV and Cu-Pad, without interface, directly combines, the good bonding strength of Cu-TSV and Cu-Pad, and thermo mechanical stability is better, and the electric conductivity of TSV is also better, and preparation process flexibility is strong.
Compared with traditional TSVs preparation technology, dry film photoresist process and through hole preparation technology combine by the present invention, eliminate thinning back side of silicon wafer, wafer support, wafer bonding, separate the steps necessary that the secondary of bonding, insulating barrier and Seed Layer the traditional handicraft such as to prepare, enormously simplify processing step, reduce process costs.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the schematic flow sheet of an embodiment of preparation method of the present invention;
Fig. 2 is silicon substrate pinboard section of structure in the embodiment of the present invention;
Fig. 3 is silica-based TSVs keyset prepared by the embodiment of the present invention, wherein (a) TSVs keyset vertical view, (b) TSVs keyset profile.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art and understand the present invention further, but not limit the present invention in any form.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, some distortion and improvement can also be made.These all belong to protection scope of the present invention.
As shown in Figure 1, be the schematic flow sheet of the specific embodiment of the invention.Following examples are carried out with reference to this flow process.
As shown in Figure 2,1 is silicon chip, and 2 is dry film photoresist, and 3 is copper seed layer, and 4 is the copper post that plating is filled, and 5 is the Cu-Pad that plating is filled.First the silicon chip electroplating being bonded with dry film photoresist is filled copper post and Pad, then remove dry film photoresist, Seed Layer, concrete steps are carried out with reference to flow process according to following examples.
Embodiment 1:
In the present embodiment, adopt sputtering technology barrier layer and Seed Layer such as depositing Ti/Cu in oxide layer, adopt hot-pressing technique by dry film photoresist and Silicon Wafer bonding, adopt electroplating technology to fill silicon through hole and Pad region.
1) by 15 μm, positive for spin coating on Silicon Wafer glue, use baking oven drying glue, photoetching and development are carried out to the silicon chip having dried glue;
2) deep reaction ion etching technology is adopted through step 1) silicon chip that processes etches TSV (diameter is 25 μm, and depth-to-width ratio is 6);
3) high-temperature oxydation (800 DEG C-1200 DEG C) is adopted through step 2) silicon chip surface that processes is oxidized, and the thickness be oxidized is 0.2 μm;
4) through step 3) Seed Layer of silicon chip surface sputtered with Ti/Cu that processes;
5) at silicon chip surface bonding dry film photoresist, then photoetching and development is carried out;
6) electroplating technology is adopted to fill TSV;
7) by step 6) in the silicon substrate pinboard for preparing, remove photoresist with acetone and alcohol and use washed with de-ionized water, using the mixed liquor (ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1 ~ 1:1) of ammoniacal liquor and hydrogen peroxide remove Cu Seed Layer and use washed with de-ionized water.
Embodiment 2
In the present embodiment, step above with embodiment 1, unlike selecting negative glue as coating here.
1) 10 μm, glue is born in spin coating on Silicon Wafer, use hot plate drying glue, photoetching and development are carried out to the silicon chip having dried glue;
2) deep reaction ion etching technology is adopted through step 1) silicon chip that processes etches TSV (diameter is 25 μm, and depth-to-width ratio is 6);
3) chemical deposition technique is adopted through step 2) silicon chip surface that processes is oxidized, and the thickness be oxidized is more than 0.21 μm;
4) through step 3) Seed Layer of silicon chip surface sputtered with Ti/Cu that processes;
5) at silicon chip surface bonding dry film photoresist, then photoetching and development is carried out;
6) electroplating technology is adopted to fill TSV;
7) by step 6) in the silicon substrate pinboard for preparing, remove photoresist with acetone and alcohol and use washed with de-ionized water, using the mixed liquor (ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1 ~ 1:1) of ammoniacal liquor and hydrogen peroxide remove Cu Seed Layer and use washed with de-ionized water.
Embodiment 3
In the present embodiment, step above, with embodiment 2, unlike plating here, the TSV (depth-to-width ratio is 10) being filled with high-aspect-ratio, adopts chemical deposition technique cvd silicon oxide insulation film.
1) 20 μm, glue is born in spin coating on Silicon Wafer, use program-control baking oven drying glue, photoetching and development are carried out to the silicon chip having dried glue;
2) deep reaction ion etching technology is adopted through step 1) silicon chip that processes etches TSV (diameter is 15 μm, and depth-to-width ratio is 10);
3) chemical deposition technique is adopted through step 2) silicon chip surface that processes is oxidized, and the thickness be oxidized is 0.22 μm;
4) through step 3) Seed Layer of silicon chip surface sputtered with Ti/Cu that processes;
5) paste dry film photoresist at silicon chip surface, then carry out photoetching and development;
6) adopt electroplating technology to fill TSV, the time vacuumized before plating increases by 1.2 times;
7) by step 6) in the silicon substrate pinboard for preparing, remove photoresist with acetone and alcohol and use washed with de-ionized water, using the mixed liquor (ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1 ~ 1:1) of ammoniacal liquor and hydrogen peroxide remove Cu Seed Layer and use washed with de-ionized water.
Be illustrated in fig. 3 shown below, the TSVs silicon substrate pinboard prepared for utilizing the novel process of this patent, figure (a) is vertical view, and (b) is TSVs keyset profile.As can be seen from the figure, the present invention except processing step simplify, preparation cost low except, prepared silica-based TSVs keyset, Pad is better shaping, copper in silicon through hole and be simultaneously electroforming between Pad, exists without interface, is conducive to the mechanical performance of raising keyset.
By the specific descriptions of above embodiment, further illustrate object of the present invention, technical scheme and implementation result.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (10)
1. a preparation method for silicon substrate pinboard, is characterized in that, said method comprising the steps of:
1) by positive for spin coating on Silicon Wafer more than 10 μm glue or more than 10 μm negative glue, with baking oven or hot plate drying glue, photoetching and development are carried out to the silicon chip having dried glue;
2) deep reaction ion etching technology is adopted through step 1) silicon chip that processes etches the silicon through hole TSV of different-diameter and the degree of depth;
3) through step 2) silicon chip surface that processes is oxidized, and the thickness be oxidized is more than 0.2 μm;
4) through step 3) Seed Layer of silicon chip surface sputtered with Ti/Cu that processes;
5) at silicon chip surface bonding dry film photoresist, then photoetching and development is carried out;
6) electroplating technology filling silicon through holes TSV is adopted;
7) by step 6) in the silicon through hole TSV silicon chip for preparing, remove photoresist with sodium hydroxide solution and use washed with de-ionized water, use the mixed liquor of ammoniacal liquor and hydrogen peroxide remove Cu Seed Layer and use washed with de-ionized water, Cu-TSV and the Cu-Pad of preparation has no time to connect.
2. method according to claim 1, is characterized in that, in the described step 3 of execution), adopt 800 DEG C of-1200 DEG C of high-temperature oxydations or chemical deposition technique to be oxidized silicon chip surface; Silicon dioxide thickness is 0.2-2 μm.
3. method according to claim 1, is characterized in that, in the described step 5 of execution) time, adopt heat pressing process at silicon face bonding dry film photoresist.
4. method according to claim 2, is characterized in that, in the described step 5 of execution) time, the thickness of dry film photoresist is 20-200 μm.
5. method according to claim 1, is characterized in that, in the described step 6 of execution) time, adopt two copper coins or phosphorous copperplate as anode.
6. method according to claim 4, is characterized in that, in the described step 6 of execution) time, Cu-TSV and TSV-Pad is electroforming simultaneously.
7. method according to claim 1, is characterized in that, in the described step 7 of execution) time, the mass concentration of sodium hydrate aqueous solution is 5% ~ 40%, and in the mixed liquor of ammoniacal liquor and hydrogen peroxide, ammoniacal liquor and hydrogen peroxide volume ratio are between 40:1 ~ 1:1.
8. the method according to any one of claim 1-7, is characterized in that, in the described step 1 of execution) time, the positive glue of spin coating is positive glue 5-30 μm or negative glue 10-60 μm.
9. the method according to any one of claim 1-7, is characterized in that, in the described step 4 of execution) time, adopt sputtering method depositing Ti/Cu Seed Layer.
10. the method according to any one of claim 1-7, is characterized in that, before plating, will speed up agent, inhibitor, poising agent add in plating solution, be used for control plating Cu speed, preparation without hole Cu-TSV, the depth-to-width ratio of the Cu-TSV of preparation is 0.5 ~ 30.
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| CN201510423748.7A CN105070682B (en) | 2015-07-17 | 2015-07-17 | A kind of method for efficiently preparing silicon pinboard |
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| CN201510423748.7A CN105070682B (en) | 2015-07-17 | 2015-07-17 | A kind of method for efficiently preparing silicon pinboard |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679701A (en) * | 2016-01-18 | 2016-06-15 | 上海交通大学 | Method for efficiently electroplating and filling silicon-based TSV |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN108511327A (en) * | 2018-05-09 | 2018-09-07 | 中国电子科技集团公司第三十八研究所 | A kind of production method without the ultra-thin silicon pinboard being bonded temporarily |
| CN112479153A (en) * | 2020-10-21 | 2021-03-12 | 武汉鲲鹏微纳光电有限公司 | Seed layer etching method, wafer-level packaging bonding ring and manufacturing method thereof |
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| CN102214621A (en) * | 2010-04-05 | 2011-10-12 | 台湾积体电路制造股份有限公司 | Semiconductor device package and method of manufacturing same |
| US20120161332A1 (en) * | 2010-12-23 | 2012-06-28 | Stmicroelectronics Pte Ltd. | Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050133930A1 (en) * | 2003-12-17 | 2005-06-23 | Sergey Savastisuk | Packaging substrates for integrated circuits and soldering methods |
| CN1783472A (en) * | 2004-11-08 | 2006-06-07 | 新光电气工业株式会社 | Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same |
| CN102214621A (en) * | 2010-04-05 | 2011-10-12 | 台湾积体电路制造股份有限公司 | Semiconductor device package and method of manufacturing same |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679701A (en) * | 2016-01-18 | 2016-06-15 | 上海交通大学 | Method for efficiently electroplating and filling silicon-based TSV |
| CN105679701B (en) * | 2016-01-18 | 2019-01-11 | 上海交通大学 | A kind of method of high-efficiency electroplating filling silicon substrate TSV |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN106252276B (en) * | 2016-08-08 | 2019-01-15 | 中国电子科技集团公司第五十四研究所 | Manufacturing method based on TSV technology switch matrix radio frequency unit |
| CN108511327A (en) * | 2018-05-09 | 2018-09-07 | 中国电子科技集团公司第三十八研究所 | A kind of production method without the ultra-thin silicon pinboard being bonded temporarily |
| CN108511327B (en) * | 2018-05-09 | 2020-05-22 | 中国电子科技集团公司第三十八研究所 | Manufacturing method of ultrathin silicon adapter plate without temporary bonding |
| CN112479153A (en) * | 2020-10-21 | 2021-03-12 | 武汉鲲鹏微纳光电有限公司 | Seed layer etching method, wafer-level packaging bonding ring and manufacturing method thereof |
| CN112479153B (en) * | 2020-10-21 | 2024-03-26 | 武汉鲲鹏微纳光电有限公司 | Etching method of seed layer, wafer-level packaging bonding ring and manufacturing method thereof |
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| CN105070682B (en) | 2018-05-29 |
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