CN109037149A - The preparation method of zero defect silicon through hole structure - Google Patents
The preparation method of zero defect silicon through hole structure Download PDFInfo
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- CN109037149A CN109037149A CN201811019338.6A CN201811019338A CN109037149A CN 109037149 A CN109037149 A CN 109037149A CN 201811019338 A CN201811019338 A CN 201811019338A CN 109037149 A CN109037149 A CN 109037149A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The present invention provides a kind of preparation method of zero defect silicon through hole structure, includes the following steps: 1) to provide the first wafer, in forming silicon through hole in the first wafer；2) in forming the first metal layer on the first surface of the first wafer；3) the second wafer is provided, forms second metal layer in a surface of the second wafer；4) the first wafer and the second wafer are posted together；5) the second wafer is rotated, to expose part the first metal layer；6) by the second wafer together with the first wafer bonding；7) exposed the first metal layer is connected via conducting medium with electroplating clamp, and electroplating clamp is placed in electroplate liquid；8) plating in silicon through hole to form the electroplated metal layer at least filling up silicon through hole；9) conducting medium and the second wafer are removed.The present invention can enable metal gradually bottom-up growth, until being fully filled with entire silicon through hole, available flawless silicon through hole structure.
Description
Technical field
The invention belongs to wafer level three-dimensional packaging technology fields, more particularly to a kind of system of zero defect silicon through hole structure
Preparation Method.
Background technique
In order to meet the needs of electronic device high-performance and miniaturization, the chip technology of mainstream follows always Moore's Law not
The disconnected minimum feature for reducing chip, constantly approaches atomic level however as minimum feature, the manufacturing cost of chip becomes very
It is high.By using the method that system-level (System-in-Package) is encapsulated, by various chips and passive device integration at one
In packaging body.By using the method for three-dimension packaging, the interconnection size between chip can be further decreased, realizes that high density is mutual
Connection, to add new approach to further reduce the size of electronic device.Silicon through hole (TSV) technology is three-dimension packaging
The three-dimension packaging of core technology, (Through silicon via, TSV) based on silicon through hole is the encapsulation skill in more forward position
Art, the technology are interconnected instead of traditional plane copper, can be stacked in the Z-direction chip, have interconnection apart from short, encapsulation volume
Small advantage, and the speed and power consumption characteristics of chip can be greatly improved.
It can be realized TSV manufacturing process there are many scheme at present, wherein well-known method has intermediate throughholes (via
Middle), rear through-hole (via last) and three kinds of process flows of intermediary layer (interposer).Wherein first two method is all
It needs to form TSV using deep silicon etching technology on active chip again, difference is that middle through-hole scheme makes between CMOS and BEOL
TSV, suitable for more complex BEOL technique, then through-hole refers to for TSV to be placed on after BEOL and manufacture, and advantage is not have to change to have
The design of source chip helps to reduce design cost.Unlike intermediate throughholes and rear through-hole, the use of intermediary layer can be kept away
Exempt to have manufactured TSV on active chip, so the design cost of active chip will decline to a great extent, simultaneously for active
Etch TSV on chip and fill the cross-interference issue that metal causes integrity problem and signal, intermediary layer technology be also one can
The solution of choosing.TSV is produced in the silicon substrate without containing any active circuit, the original design of chip can not changed
Under the premise of layout, High Density Integration is realized.The active chip to have completed can realize ultra-fine section on silicon intermediary layer
Away from electricity interconnection, and can will realize hybrid integrated, phase on the chip manufactured under different process level in the same block interlayer
It is a kind of envelope of following mainstream than cost can be greatly reduced while meeting High Density Integration in system on chip (SoC)
Dress mode.
Technology currently used for filling intermediary layer TSV is broadly divided into through-hole technology and blind hole technology.The advantages of blind hole technology
It is side wall and bottom of the seed layer continued presence in TSV, therefore electroplating time is shorter, is conducive to the production efficiency for improving TSV.But
The disadvantage is that the seed layer of side wall can make metal cross growth, fine allotment only is carried out to electroplate liquid and uses cyclicity
Good electroplating device is just able to achieve the filling of zero defect metal, so virtually increases the manufacturing cost of TSV again.And it is general
Although logical through-hole filling technique is capable of forming " bottom-up " growth of metal in TSV and can fill different pore size simultaneously
TSV, but still side-wall metallic cross growth bring bottom cavitation problem can not be avoided completely.
In consideration of it, needing the existing through-hole TSV filling technique of major tuneup, side-wall metallic cross growth bring is avoided to fill out
Defect is filled, yield and raising that raising TSV makes wear the reliability of silicon interconnection architecture.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of zero defect silicon through hole structures
Preparation method for solve prepare existing above problem when silicon through hole structure in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation side of zero defect silicon through hole structure
The preparation method of method, the zero defect silicon through hole structure includes the following steps:
1) the first wafer is provided, first wafer includes opposite first surface and second surface；It is brilliant in described first
Silicon through hole is formed in circle, the silicon through hole penetrates through the first surface and the second surface；
2) in forming the first metal layer on the first surface of first wafer；
3) the second wafer is provided, forms second metal layer in a surface of second wafer；
4) first wafer and second wafer are posted together, and the first metal layer is far from described first
The surface of the surface of wafer and the second metal layer far from second wafer is binding face；
5) second wafer is rotated, to expose the part the first metal layer；
6) by second wafer together with first wafer bonding, the binding face is bonding face；
7) the exposed the first metal layer is connected via conducting medium with electroplating clamp, and by the electroplating clamp
It is placed in electroplate liquid；
8) by after the electroplating clamp, bonding first wafer and second wafer be placed in vacuum in vacuum environment
It is electroplated after processing, to form the electroplated metal layer at least filling up the silicon through hole in the silicon through hole；
9) conducting medium and second wafer are removed.
Preferably, step 1) includes the following steps:
One first wafer 1-1) is provided；
1-2) the first silicon oxide layer is formed in the surface of first wafer；
1-3) graphical photoresist layer, shape in the graphical photoresist layer are formed in the surface of first silicon oxide layer
At there is opening, described be open defines the position shape of the silicon through hole；
First silicon oxide layer and first wafer 1-4) are etched according to the graphical photoresist layer, in described
The silicon through hole is formed in first wafer；
1-5) remove the graphical photoresist layer and first silicon oxide layer.
Preferably, step 2) includes the following steps:
2-1) the second silicon oxide layer is formed in the side wall of the surface of first wafer and the silicon through hole；
2-2) in second silicon oxide layer surface and the silicon through hole that are located on the first wafer first surface
Side wall forms metal material layer；
Photoresist layer 2-3) is formed in the metal material layer surface, the photoresist layer covering is located at second oxidation
The metal material layer of layer surface and the metal material layer positioned at the silicon through hole side wall；
2-4) removal is located at the photoresist layer in the silicon through hole；
2-5) removal is located at the metal material layer in the silicon through hole, remaines in the first table of first wafer
The metal material layer on face is the first metal layer.
Preferably, step 2-5) further include later following steps:
The step of 2-6) removing the photoresist layer.
Preferably, step 2-6) include the following steps:
It 2-6-1) is cleaned using first surface of the acetone to first wafer, to remove the photoresist layer, institute
After stating acetone cleaning, the first surface of first wafer remains the part photoresist layer；
2-6-2) the obtained structure of step 2-6-1) is placed in oxygen plasma or nitrogen plasma atmosphere and is handled,
To remove the remaining photoresist layer of the first wafer first surface.
Preferably, in step 5), second wafer is rotated by 90 ° around its center.
Preferably, in step 6), second wafer is placed under vacuum with the first wafer and is bonded, be bonded
Temperature between 300 DEG C~400 DEG C, bonding pressure between 2500mbar~3500mbar, bonding time between 1h~
Between 2h.
Preferably, electroplate liquid described in step 7) includes copper methanesulfonate basal liquid, accelerator and inhibitor, wherein
The concentration of the accelerator is between 1ml/L~3ml/L, and the concentration of the inhibitor is between 4ml/L~6ml/L.
Preferably, in step 8), the electroplated metal layer obtained after plating extends from the first wafer first surface
To the top of the first wafer second surface.
Preferably, step 9) includes the following steps:
The dielectric layer 9-1) is removed using wet corrosion technique；
9-2) surface from second wafer far from first wafer carries out reduction processing to second wafer；
Second wafer after 9-3) being thinned using wet corrosion technique removal.
As described above, a kind of preparation method of zero defect silicon through hole structure of the invention, has the advantages that
The preparation method of zero defect silicon through hole structure of the invention under the premise of remaining silicon through hole technical advantage,
Influence of traditional silicon through hole technology side wall seed layer metal to filling quality is effectively prevented, enables metal gradually the bottom of from
It grows up, until being fully filled with entire silicon through hole, available flawless silicon through hole structure.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the zero defect silicon through hole structure provided in the embodiment of the present invention one.
The preparation method that Fig. 2 to Figure 17 is shown as the zero defect silicon through hole structure provided in the embodiment of the present invention one respectively walks
The cross section structure schematic diagram of rapid resulting structures.
Component label instructions
10 first wafers
11 first silicon oxide layers
12 graphical photoresist layers
121 openings
13 second silicon oxide layers
14 the first metal layers
141 metal material layers
15 photoresist layers
16 second wafers
17 third silicon oxide layers
18 second metal layers
19 conducting mediums
20 electroplated metal layers
S1~S9 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 17.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
Referring to Fig. 1, the present invention provides a kind of preparation method of zero defect silicon through hole structure, it is logical that the zero defect wears silicon
The preparation method of pore structure includes the following steps:
1) the first wafer is provided, first wafer includes opposite first surface and second surface；It is brilliant in described first
Silicon through hole is formed in circle, the silicon through hole penetrates through the first surface and the second surface；
2) in forming the first metal layer on the first surface of first wafer；
3) the second wafer is provided, forms second metal layer in a surface of second wafer；
4) first wafer and second wafer are posted together, and the first metal layer is far from described first
The surface of the surface of wafer and the second metal layer far from second wafer is binding face；
5) second wafer is rotated, to expose the part the first metal layer；
6) by second wafer together with first wafer bonding, the binding face is bonding face；
7) the exposed the first metal layer is connected via conducting medium with electroplating clamp, and by the electroplating clamp
It is placed in electroplate liquid；
8) by after the electroplating clamp, bonding first wafer and second wafer be placed in vacuum in vacuum environment
It is electroplated after processing, to form the electroplated metal layer at least filling up the silicon through hole in the silicon through hole；
9) conducting medium and second wafer are removed.
In step 1), the S1 step and Fig. 2 to Fig. 6 in Fig. 1 are please referred to, the first wafer 10, first wafer are provided
10 include opposite first surface and second surface；In formation silicon through hole 101, the silicon through hole in first wafer 10
The first surface and the second surface of 101 perforation first wafers 10.
As an example, step 1) includes the following steps:
First wafer 10 1-1) is provided, as shown in Figure 2；First wafer 10 can be bare silicon wafer；Described
The crystal orientation of one wafer 10 can be but be not limited only to<110>crystal orientation；
The first silicon oxide layer 11 1-2) is formed in the surface of first wafer 10, as shown in Figure 3；Specifically, can adopt
With but be not limited only to thermal oxidation technology or physical deposition process forms first silicon oxide layer 11；First silicon oxide layer 11
Thickness can be set according to actual needs, it is preferable that in the present embodiment, the thickness of first silicon oxide layer 11 can be with
Between 1 μm~2 μm；It should be noted that " between 1 μm~2 μm " refer to including 1 μm and 2 μm two in the present embodiment
A endpoint, and the numberical range of all numerical value composition between 1 μm and 2 μm；First silicon oxide layer 11 can wrap
Include silicon dioxide layer；
1-3) graphical photoresist layer 12, the graphical photoresist layer are formed in the surface of first silicon oxide layer 11
Opening 121 is formed in 12, the opening 121 defines the position shape of the silicon through hole, as shown in Figure 4；Specifically, first
Prior to one layer photoresist of surface spin coating of first silicon oxide layer 11, the photoresist can be positive photoetching rubber, the institute of spin coating
Secondly the thickness for stating photoresist can carry out front baking, the front baking to the photoresist on hot plate between 7 μm~9 μm
Temperature can be between 100 DEG C~150 DEG C, preferably 110 DEG C, time of the front baking can between 50s~120s it
Between, preferably 90s forms the opening 121 after then carrying out photoetching development, finally post bake in an oven in the photoresist
To obtain the graphical photoresist layer 12, the temperature of the post bake can between 100 DEG C~150 DEG C, preferably 120
DEG C, the time of the post bake can be between 10min~50min, preferably 30min.
First silicon oxide layer 11 and first wafer 10 1-4) are etched according to the graphical photoresist layer 12, with
In forming the silicon through hole 101 in first wafer 10, as shown in Figure 5；Specifically, being first depending on the graphical photoetching
Glue-line 12 etches first silicon oxide layer 11, by pattern transfer to first silicon oxide layer 11, then again according to institute
State graphical photoresist layer 12 and it is graphical after first silicon oxide layer 11 institute is etched using deep reaction ion etching technique
The first wafer 10 is stated, in forming the silicon through hole 101 in first wafer 10；
The graphical photoresist layer 12 and first silicon oxide layer 11 1-5) are removed, as shown in Figure 6；Specifically, can
To remove the graphical photoresist layer 12 using hot concentrated sulfuric acid or acetone, the temperature of the hot sulfuric acid or the acetone can be with
Between 100 DEG C~150 DEG C, preferably 120 DEG C；First oxygen can be removed using buffered oxide etch liquid (BOE)
SiClx layer 11.
In step 2), the S2 step and Fig. 7 to Figure 13 in Fig. 1 are please referred to, in the first surface of first wafer 10
Upper formation the first metal layer 14.
As an example, step 2) includes the following steps:
The second silicon oxide layer 13 2-1) is formed in the side wall of the surface of first wafer 10 and the silicon through hole 101,
As shown in Figure 7；Specifically, second silicon oxide layer 13, second silicon oxide layer 13 can be formed using thermal oxidation technology
It may include silicon dioxide layer, the thickness of second silicon oxide layer 13 can be set according to actual needs, it is preferable that this
In embodiment, the thickness of second silicon oxide layer 13 can be between 1 μm~2 μm；Second silicon oxide layer 13 is used for
The first metal layer 14 being subsequently formed and first wafer 10 are kept apart；
2-2) in 13 surface of the second silicon oxide layer being located on 10 first surface of the first wafer and described wear silicon
101 side wall of through-hole forms metal material layer 141, as shown in Figure 8；Specifically, can be using magnetron sputtering technique prior to described the
The surface of silicon dioxide layer 13 sputters one layer of titanium tungsten (TiW) layer, then sputters one layer of metallic gold then at the titanium tungsten layer surface
(Au) layer, the titanium tungsten layer and the metal layer gold collectively form the metal material layer 141；The thickness of the titanium tungsten layer can be with
For but be not limited only to 500 angstroms, the thickness of the metal layer gold can be between 2000 angstroms~5000 angstroms；
Photoresist layer 15 2-3) is formed in 141 surface of metal material layer, the covering of photoresist layer 15 is located at described
The metal material layer 141 on 13 surface of the second oxide layer and the metal material layer positioned at 101 side wall of silicon through hole
141, as shown in Figure 9；Specifically, first in the one layer photoresist layer 15 of surface spin coating of the metal material layer 142, the photoetching
The material of glue-line 15 can be positive photoetching rubber, the thickness of the photoresist layer 15 of spin coating can between 2 μm~4 μm,
Secondary to carry out front baking to the photoresist layer 15 on hot plate, the temperature of the front baking can be excellent between 100 DEG C~150 DEG C
It is selected as 110 DEG C；
2-4) removal is located at the photoresist layer 15 in the silicon through hole 101, as shown in Figures 10 and 11；Specifically
, the second surface of the first wafer 10 described in structure that step 2-3) is obtained persistently is exposed towards litho machine light source, is exposed
Time can be between 200s~300s, as shown in Figure 10, and the arrow in Figure 10 indicates the direction of litho machine light source；It will exposure
The photoresist layer 15 afterwards develops, to remove the photoresist layer 15 being located in the silicon through hole 101, such as Figure 11
It is shown；
2-5) removal is located at the metal material layer 141 in the silicon through hole 101, remaines in first wafer 10
First surface on the metal material layer 141 be the first metal layer 14, as shown in figure 12；Specifically, can incite somebody to action
Step 2-4) obtained structure is placed in golden corrosive liquid, and concussion cleaning 2min~3min is located at the silicon through hole 101 with removal
Interior metal layer gold；Above structure is placed in titanium tungsten corrosive liquid again, concussion cleaning 2min~3min is located at described wear with removal
Titanium tungsten layer in through silicon via 101.
As an example, step 2-5) further include later following steps:
The step of 2-6) removing photoresist layer 15, as shown in figure 13.
As an example, step 2-6) include the following steps:
It 2-6-1) is cleaned using first surface of the acetone to first wafer 10, to remove the photoresist layer
15, after the acetone cleaning, the first surface of first wafer 10 remains the part photoresist layer 15；
The obtained structure of step 2-6-1) 2-6-2) is placed in oxygen plasma or nitrogen plasma atmosphere (plasma institute
Gas is needed, for example the gas flow of oxygen or nitrogen may include but be not limited only to 200ml/min, and power can be but not only limit
In 200W) in handled, to remove the remaining photoresist layer 15 of 10 first surface of the first wafer.Specifically, can
It is placed in oxygen plasma or nitrogen plasma atmosphere with the structure for obtaining step 2-6-1) and carries out multiplicating processing, for example
Three times, the time per treatment can be but be not limited only to 1min for processing.
In step 3), S3 step and Figure 14 in Fig. 1 are please referred to, the second wafer 16 is provided, in second wafer 16
A surface formed second metal layer 18.
As an example, second wafer 16 is as the support wafer for being used to support first wafer 10, described second
The surface of wafer 16 is formed with third silicon oxide layer 17, and the third silicon oxide layer 17 can be but be not limited only to silica
Layer.
As an example, the crystal orientation of second wafer 16 and the crystal orientation of first wafer 10 answer it is identical.
As an example, one layer of titanium tungsten can be sputtered prior to the surface of the third silicon oxide layer 17 using magnetron sputtering technique
(TiW) layer, then sputters one layer of metallic gold (Au) layer then at the titanium tungsten layer surface, and the titanium tungsten layer and the metal layer gold are total
With the composition second metal layer 18；The thickness of the titanium tungsten layer can be but be not limited only to 500 angstroms, the thickness of the metal layer gold
Degree can be between 2000 angstroms~5000 angstroms.
In step 4), S4 step and Figure 15 in Fig. 1 are please referred to, by first wafer 10 and second wafer 16
It posts together, and surface and the second metal layer 18 of the first metal layer 14 far from first wafer 10 are far from institute
The surface for stating the second wafer 16 is binding face, i.e., described after described first wafer 10 posts together with second wafer 16
The first metal layer 14 is in contact with the second metal layer 18, and the first metal layer 14 is located at the second metal layer 18
Between first wafer 10 and second wafer 16.
In step 5), S5 step and Figure 15 in Fig. 1 are please referred to, second wafer 16 is rotated, to expose portion
Divide the first metal layer 14.
As an example, second wafer 16 is rotated by 90 ° around its center.Since wafer has unfilled corner, and described
One wafer 10 is identical as the crystal orientation of second wafer 16, and first wafer 10 is being posted with second wafer 16 one
When playing place, the unfilled corner of first wafer 10 is corresponding up and down with the unfilled corner of second wafer 16, by second wafer 16
After rotation, the unfilled corner of first wafer 10 and the unfilled corner of second wafer 16 will misplace, at this point, part first gold medal
Belonging to layer 14 and the part second metal layer 18 can be exposed.
In step 6), the S6 step in Fig. 1 is please referred to, second wafer 16 and first wafer 10 are bonded in
Together, the binding face is bonding face.
As an example, after being fit together due to second wafer 16 with first wafer 10, first metal
Metal layer gold in layer 14 is in contact with the metal layer gold in the second metal layer 18, can use Jin-gold thermocompression bonding work
Skill completes being bonded for first wafer 10 and second wafer 16；Specifically, second wafer 16 and institute first is brilliant
Circle 10, which is placed under vacuum, to be bonded, and bonding temperature is between 300 DEG C~400 DEG C, and bonding pressure is between 2500mbar
Between~3500mbar, bonding time is between 1h~2h, it is preferable that in the present embodiment, bonding temperature is 300 DEG C, bonding
Pressure is 3000mbar, bonding time 2h.
In step 7), S7 step and Figure 16 in Fig. 1 are please referred to, by the exposed the first metal layer 14 via conduction
Medium 19 is connected with electroplating clamp, and the electroplating clamp is placed in electroplate liquid.
As an example, should first deploy the electroplate liquid to match with the silicon through hole 101, the electroplate liquid in the step
Including copper methanesulfonate basal liquid, accelerator and inhibitor, wherein the concentration of the accelerator between 1ml/L~3ml/L it
Between, the concentration of the inhibitor is between 4ml/L~6ml/L, it is preferable that in the present embodiment, the concentration of the accelerator is
3ml/L, the concentration of the inhibitor are 5ml/L.
As an example, the conducting medium 19 can be but be not limited only to copper conductive adhesive band.
In step 8), S8 step and Figure 16 in Fig. 1 are please referred to, by described first after the electroplating clamp, bonding
Wafer 10 and second wafer 16 are placed in vacuum environment and are electroplated after vacuum processing, in the silicon through hole 101
Form the electroplated metal layer 20 at least filling up the silicon through hole 101.
As an example, the obtained structure of step 7), which is integrally placed at vacuum degree, reaches predetermined vacuum degree (for example 28in mercury
Column) vacuum chamber in be vacuum-treated, the air in the silicon through hole 101 is excluded completely, so that described
Electrolyte can sufficiently infiltrate the silicon through hole 101 well into the silicon through hole 101.
It is carried out as an example, the structural portion after vacuum processing can be integrally placed in the electroplating bath for being placed with the electroplate liquid
Plating, until the electroplated metal layer 20 formed in the silicon through hole 101 fills up the silicon through hole 101.It is obtained after plating
The electroplated metal layer 20 extends to the top of 10 second surface of the first wafer from 10 first surface of the first wafer, i.e.,
The upper surface of the electroplated metal layer 20 is higher than the second surface of first wafer 10.Certainly, in other examples, the plating
Two opposite surfaces of metal layer 20 can also respectively with the first surface and second surface flush of first wafer 10.
In step 9), S9 step and Figure 17 in Fig. 1 are please referred to, removes the conducting medium 19 and second wafer
20。
As an example, step 9) includes the following steps:
The dielectric layer 19 9-1) is removed using wet corrosion technique；For example, the dielectric layer 19 is copper conductive adhesive
When band, the dielectric layer 19 is removed using copper corrosion liquid；
9-2) surface from second wafer 16 far from first wafer 10 carries out second wafer 16 thinned
Processing, specifically, reduction processing can be carried out to second wafer 16 using chemical mechanical milling tech, by described second
Wafer 16 is thinned to certain thickness；
Second wafer 16 after 9-3) being thinned using wet corrosion technique removal,；Specifically, can be molten using KOH
Remaining second wafer 16 after corrosion removal is thinned.
In conclusion the preparation method of zero defect silicon through hole structure of the present invention, the zero defect silicon through hole structure
Preparation method includes the following steps: 1) the first wafer of offer, and first wafer includes opposite first surface and second surface；
In forming silicon through hole in first wafer, the silicon through hole penetrates through the first surface and the second surface；2) in
The first metal layer is formed on the first surface of first wafer；3) the second wafer is provided, in a surface of second wafer
Form second metal layer；4) first wafer and second wafer are posted together, and the first metal layer is separate
The surface of surface and the second metal layer far from second wafer of first wafer is binding face；5) by described second
Wafer rotation, to expose the part the first metal layer；6) by second wafer together with first wafer bonding,
The binding face is bonding face；7) the exposed the first metal layer is connected via conducting medium with electroplating clamp, and will
The electroplating clamp is placed in electroplate liquid；8) by first wafer and second wafer after the electroplating clamp, bonding
It is placed in vacuum environment after being vacuum-treated and is electroplated, at least fill up the silicon through hole to be formed in the silicon through hole
Electroplated metal layer；9) conducting medium and second wafer are removed.The preparation of zero defect silicon through hole structure of the invention
Method effectively prevents traditional silicon through hole technology side wall seed layer metal under the premise of remaining silicon through hole technical advantage
Influence to filling quality enables metal gradually bottom-up growth that can obtain until being fully filled with entire silicon through hole
To flawless silicon through hole structure.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of preparation method of zero defect silicon through hole structure, which is characterized in that the system of the zero defect silicon through hole structure
Preparation Method includes the following steps:
1) the first wafer is provided, first wafer includes opposite first surface and second surface；In in first wafer
Silicon through hole is formed, the silicon through hole penetrates through the first surface and the second surface；
2) in forming the first metal layer on the first surface of first wafer；
3) the second wafer is provided, forms second metal layer in a surface of second wafer；
4) first wafer and second wafer are posted together, and the first metal layer is far from first wafer
Surface and the second metal layer far from second wafer surface be binding face；
5) second wafer is rotated, to expose the part the first metal layer；
6) by second wafer together with first wafer bonding, the binding face is bonding face；
7) the exposed the first metal layer is connected via conducting medium with electroplating clamp, and the electroplating clamp is placed in
In electroplate liquid；
8) by after the electroplating clamp, bonding first wafer and second wafer be placed in vacuum environment and be vacuum-treated
After be electroplated, to form the electroplated metal layer at least filling up the silicon through hole in the silicon through hole；
9) conducting medium and second wafer are removed.
2. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that step 1) includes such as
Lower step:
One first wafer 1-1) is provided；
1-2) the first silicon oxide layer is formed in the surface of first wafer；
Graphical photoresist layer 1-3) is formed in the surface of first silicon oxide layer, is formed in the graphical photoresist layer
Opening, described be open define the position shape of the silicon through hole；
First silicon oxide layer and first wafer 1-4) are etched according to the graphical photoresist layer, in described first
The silicon through hole is formed in wafer；
1-5) remove the graphical photoresist layer and first silicon oxide layer.
3. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that step 2) includes such as
Lower step:
2-1) the second silicon oxide layer is formed in the side wall of the surface of first wafer and the silicon through hole；
2-2) in second silicon oxide layer surface and the silicon through hole side wall that are located on the first wafer first surface
Form metal material layer；
Photoresist layer 2-3) is formed in the metal material layer surface, the photoresist layer covering is located at the second oxide layer table
The metal material layer in face and the metal material layer positioned at the silicon through hole side wall；
2-4) removal is located at the photoresist layer in the silicon through hole；
2-5) removal is located at the metal material layer in the silicon through hole, remaines on the first surface of first wafer
The metal material layer be the first metal layer.
4. the preparation method of zero defect silicon through hole structure according to claim 3, which is characterized in that step 2-5) after
Further include following steps:
The step of 2-6) removing the photoresist layer.
5. the preparation method of zero defect silicon through hole structure according to claim 4, which is characterized in that step 2-6) include
Following steps:
2-6-1) cleaned using first surface of the acetone to first wafer, to remove the photoresist layer, described third
After ketone cleaning, the first surface of first wafer remains the part photoresist layer；
2-6-2) the obtained structure of step 2-6-1) is placed in oxygen plasma or nitrogen plasma atmosphere and is handled, to go
Except the remaining photoresist layer of the first wafer first surface.
6. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that, will in step 5)
Second wafer is rotated by 90 ° around its center.
7. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that, will in step 6)
Second wafer is placed under vacuum with the first wafer to be bonded, bonding temperature between 300 DEG C~400 DEG C,
Bonding pressure is between 2500mbar~3500mbar, and bonding time is between 1h~2h.
8. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that described in step 7)
Electroplate liquid include copper methanesulfonate basal liquid, accelerator and inhibitor, wherein the concentration of the accelerator between 1ml/L~
Between 3ml/L, the concentration of the inhibitor is between 4ml/L~6ml/L.
9. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that in step 8), electricity
The electroplated metal layer obtained after plating extends to the upper of the first wafer second surface from the first wafer first surface
Side.
10. the preparation method of zero defect silicon through hole structure according to claim 1, which is characterized in that step 9) includes
Following steps:
The dielectric layer 9-1) is removed using wet corrosion technique；
9-2) surface from second wafer far from first wafer carries out reduction processing to second wafer；
Second wafer after 9-3) being thinned using wet corrosion technique removal.
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| CN111952185A (en) * | 2020-08-21 | 2020-11-17 | 中国科学院上海微***与信息技术研究所 | SOI device capable of reducing alignment difficulty and preparation method thereof |
| CN113078101A (en) * | 2021-03-23 | 2021-07-06 | 浙江集迈科微电子有限公司 | Electroplating process |
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| CN103199026A (en) * | 2012-01-10 | 2013-07-10 | 中国科学院上海微***与信息技术研究所 | Electroplating method adopting non-aligned bonding process to manufacture TSV |
| US20180047626A1 (en) * | 2015-06-08 | 2018-02-15 | Globalfoundries Inc. | Thru-silicon-via structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103199026A (en) * | 2012-01-10 | 2013-07-10 | 中国科学院上海微***与信息技术研究所 | Electroplating method adopting non-aligned bonding process to manufacture TSV |
| US20180047626A1 (en) * | 2015-06-08 | 2018-02-15 | Globalfoundries Inc. | Thru-silicon-via structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111952185A (en) * | 2020-08-21 | 2020-11-17 | 中国科学院上海微***与信息技术研究所 | SOI device capable of reducing alignment difficulty and preparation method thereof |
| CN111952185B (en) * | 2020-08-21 | 2024-03-29 | 中国科学院上海微***与信息技术研究所 | SOI device capable of reducing alignment difficulty and preparation method thereof |
| CN113078101A (en) * | 2021-03-23 | 2021-07-06 | 浙江集迈科微电子有限公司 | Electroplating process |
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