CN105047671B - 用于显示装置的阵列基板及其制造方法 - Google Patents
用于显示装置的阵列基板及其制造方法 Download PDFInfo
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- CN105047671B CN105047671B CN201510184664.2A CN201510184664A CN105047671B CN 105047671 B CN105047671 B CN 105047671B CN 201510184664 A CN201510184664 A CN 201510184664A CN 105047671 B CN105047671 B CN 105047671B
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Abstract
本公开提供了一种用于显示装置的阵列基板及其制造方法,并且在源极/漏极金属图案与位于源极/漏极金属图案上方的钝化层之间形成有透明电极图案(ITO),上述源极/漏极金属图案和钝化层形成在用于显示面板的阵列基板的非有源区的钝化孔区中。因此,可以防止由于在钝化孔区中金属层和钝化层之间粘合强度不足而产生的层离现象或钝化层的材料的剥离所引起的显示故障。
Description
相关申请的交叉引用
本申请要求2014年4月17日提交的韩国专利申请第10-2014-0046151号的优先权和权益,通过引用将其如在本文中完全阐述的那样并入本文以用于所有目的。
技术领域
本发明涉及一种用于显示装置的阵列基板及其制造方法。更具体地,本发明涉及用于显示装置的阵列基板及其制造方法,其能够防止由于在非有源区中形成在源极/漏极(S/D)金属图案上的钝化孔区中的钝化层的损伤而引起的问题。
背景技术
随着信息导向社会的进步,对用于显示图像的显示装置的需求以各种方式增加。近来,各种显示装置例如液晶显示(LCD)装置、等离子体显示面板(PDP)和有机发光二极管显示(OLED)装置已经投入使用。
在这些显示装置中,液晶显示(LCD)装置包括:包含薄膜晶体管(TFT)的阵列基板,TFT为控制各像素区的通/断的开关元件;包含滤色器和/或黑矩阵等的上基板;形成在阵列基板和上基板之间的包含液晶材料层的显示面板;以及用于控制TFT的驱动单元。在这样的LCD装置中,根据施加到设置在像素区中的像素(PXL)电极和公共电压(Vcom)电极之间的电场来控制液晶层的取向状态,由此对光的透过率进行调整以使得图像能够显示。
在阵列基板中,限定非有源区(NA)以及显示图像的包括一个或更多个像素的有源区(AA)。多个栅极线GL和多个数据线DL交叉以在阵列基板(通常称作“下基板”)的有源区的内表面上限定像素(P),并且栅极线和数据线之间的交叉部中的每个交叉部设置有与形成在各像素P中的透明像素电极(未示出)一对一连接的TFT。
在阵列基板上,形成多个层例如栅极金属层、半导体层、源极/漏极金属层、像素电极层、公共电极层等,以形成TFT和引线,并且可以形成用于层间绝缘的层间绝缘层或用于保护各层的保护层。
同时,存在扭曲向列(TN)模式,在TN模式中,其上形成有像素电极的阵列基板与其上形成有公共电压电极的上基板彼此隔开,在阵列基板与上基板之间注入有液晶材料,并且沿垂直于基板的方向驱动向列相的液晶分子。然而,上述TN模式的LCD装置由于其约90度的窄的视角而是不利的。
相比之下,存在面内开关(IPS)模式的LCD装置,在IPS模式中,沿平行于基板的方向驱动液晶分子,由此使视角提高到超过170度。基本上像素电极和公共电压电极同时形成在下基板或阵列基板上的IPS模式的LCD装置分为如下类型:像素电极和公共电压电极两者形成在同一层中的类型;以及边缘场开关(FFS)类型,在FFS类型中像素电极和公共电压电极两者在***一个或更多个绝缘层并且一个电极具有指状的状态下被形成为沿水平方向彼此隔开。
此外,在阵列基板中,可以在有源区外部的非有源区的一部分上形成用于与设置在阵列基板的内部或外部处的驱动单元连接的连接焊盘、用于施加参考电压或参考信号的信号施加焊盘、用于测量的各种焊盘等。
在非有源区中,可以通过使位于层叠在阵列基板上的S/D金属层上的绝缘层或钝化层的一部分开口来形成多个钝化孔或多个钝化接触孔。
钝化孔为由于移除层叠在S/D金属图案上的钝化层或绝缘层的一部分而使S/D金属图案露出的孔洞。为了保护露出的S/D金属图案,可以在钝化孔上形成另一附加钝化层。
在如上所述在S/D金属图案上形成钝化孔的情况下,钝化孔区中的S/D金属图案层与层叠在S/D金属图案层上的与S/D金属图案层接触的附加钝化层之间的粘合强度变弱,从而可在接触的S/D金属图案层和附加钝化层两者之间发生层离现象。此外,在附加过程期间可发生上钝化层的一部分剥离的异物剥离现象。
在钝化孔区中S/D金属层与位于S/D金属层上的附加钝化层之间发生层离现象的情况下,测量的精确度可降低。具体地,在通过异物剥离现象而从钝化层产生的异物到达有源区并且固定至有源区的情况下,可产生显示故障例如像素缺陷或燥点等。
发明内容
在该背景下,本发明的一方面旨在提供一种用于显示装置的阵列基板及其制造方法,其能够解决由于在显示面板的非有源区中形成在钝化孔区中的金属图案和位于金属图案上方的钝化层的粘合强度不足而引起的问题。
本发明的另一方面旨在提供一种用于显示装置的阵列基板及其制造方法,其能够通过在形成在钝化孔区中的S/D金属图案和位于S/D金属图案上方的钝化层之间形成透明电极图案(ITO)来防止在钝化孔区中钝化层的层离现象和异物剥离现象。
本发明的又一方面旨在提供一种用于显示装置的阵列基板及其制造方法,其在下透明电极和上透明电极全都设置在阵列基板上的显示面板中,能够通过在形成于非有源区的钝化孔区中的S/D金属图案上形成下透明电极层作为S/D盖层以及通过在下透明电极层上层叠钝化层来防止钝化孔区中的钝化层的层离现象和异物剥离现象。
为了解决上述技术问题,根据本发明的一个方面,提供了一种用于制造用于显示装置的阵列基板的方法。该方法包括:第一步骤,在设置在非有源区中的钝化孔区中形成栅极绝缘体(GI)、源极/漏极(S/D)金属图案和下钝化层;第二步骤,通过移除在钝化孔区中的下钝化层来露出S/D金属图案;第三步骤,在钝化孔区中露出的S/D金属图案上形成下透明电极图案作为S/D盖层;以及第四步骤,在钝化孔区中的下透明电极图案上形成上钝化层。
根据本发明的另一方面,提供了一种用于显示装置的阵列基板,该阵列基板具有有源区以及包括钝化孔区的非有源区。该阵列基板包括:包含薄膜晶体管(TFT)区的有源区,在TFT区中依次设置有栅极金属图案、栅极绝缘体(GI)、半导体层、源极/漏极(S/D)金属图案、下钝化层、下透明电极层、上钝化层和上透明电极层;以及包含钝化孔区的非有源区,在钝化孔区中依次设置有GI、源极/漏极(S/D)金属图案、作为S/D金属图案的盖层的下透明电极图案以及上钝化层。
根据本发明的又一方面,提供了一种用于制造用于显示装置的阵列基板的方法,该阵列基板具有有源区以及包括钝化孔区的非有源区。该方法包括:在阵列基板上形成栅极金属图案,并且在栅极金属图案上形成栅极绝缘体(GI);沉积半导体层和源极/漏极(S/D)层,并且使用一个或更多个掩模通过光刻工艺在有源区和非有源区两者中形成S/D金属图案;沉积下钝化层,并且通过移除下钝化层在钝化孔区中的一部分来形成钝化孔;沉积下透明电极层,并且通过使用下透明电极掩模来图案化下透明电极图案以在钝化孔区中的S/D金属图案上形成下透明电极图案;以及在阵列基板的整个表面上形成上钝化层。
根据本发明的一个实施方案,在形成在金属图案例如S/D金属层上的无机钝化孔(PAS孔)区或有机钝化孔(PAC孔)区中的S/D金属层和位于S/D金属层上方的钝化层之间形成有用于增加粘合强度的透明电极图案。因此,可以防止由于在钝化孔区中金属层和钝化层之间粘合强度不足而产生钝化层的材料的剥离或层离现象所引起的显示故障。
具体地,使用由有机材料例如光丙烯酸类物质等形成的有机绝缘层或有机钝化层(PAC)。在阵列基板上同时设置有像素透明电极或公共电压透明电极的显示面板中,在非有源区的钝化孔(PAC孔)区中在S/D金属层与位于S/D金属层上方的钝化层之间形成有透明电极图案。因此,可以解决在S/D金属层与位于S/D金属层上的钝化层之间的粘合强度变弱的情况下所产生的各种问题,所述粘合强度变弱由于在对有机钝化层进行干蚀刻的工艺中在包括于用于测量的焊盘中的S/D金属层中形成的氧化层而导致。因此,能够寻求提高液晶显示面板的良品率并降低其故障率。
附图说明
根据结合附图的如下详细描述,本发明的以上目的、特征和优点以及其他目的、特征和优点将更为明显,其中:
图1A和图1B分别为示出应用本发明的实施方案的液晶显示面板的阵列基板的平面图和截面图;
图2A为示出可应用本发明的实施方案的钝化孔区的放大平面图,图2B至图2D为各自示出可应用本发明的实施方案的钝化孔区的放大截面图;
图3和图4示出根据本发明的实施方案制造用于液晶显示面板的阵列基板的方法的整体流程,其中图3为示出重点在钝化孔区的过程的流程图并且图4为示出制造阵列基板的整体过程的流程图;
图5A至图5E为在根据本发明的实施方案的制造阵列基板的过程中的截面图;
图6A和图6B为示出根据本发明的实施方案制造的阵列基板的平面图,图6C和图6D为示出根据本发明的实施方案制造的阵列基板的截面图;以及
图7为示出根据本发明的另一实施方案的钝化孔区的截面图,并且示出了应用于像素在顶部(POT)型LCD装置的示例。
具体实施方式
在下文中,将参照附图详细描述本发明的实施方案。在下面的描述中,相同的元件将通过相同的附图标记来标记,即使相同的元件在不同图中示出也是如此。此外,在本发明的下面的描述中,在公知的功能和构造并入本文中可使本发明的主体变得相当不清楚的情况下,将省略其详细描述。
另外,在描述本发明的部件时,可以使用术语例如第一、第二、A、B、(a)、(b)等。这些术语中的每个术语不是用于限定对应部件的本质、次序或顺序,而是仅用于将对应的部件与其他部件进行区分。在描述特定结构元件“连接至”、“耦接至”另一结构元件或“与”另一结构元件“接触”时,应该理解的是,另一结构元件“可以连接至”、“耦接至”结构元件或“与”结构元件“接触”,以及特定结构元件直接连接至另一结构元件,或者与另一结构元件直接接触。
图1A和图1B分别为示出应用本发明的实施方案的液晶显示面板的阵列基板的平面图和截面图。
可应用本发明的实施方案的液晶显示装置的阵列基板包括:有源区(AA)11,其包括分别形成在多个栅极线13和多个数据线14交叉的区域中的像素15;以及在有源区外部的非有源区(NA)12。
各像素15具有形成在像素中的一个或更多个TFT,并且包括连接至包括在TFT中的漏电极的由透明导电材料形成的像素电极。
同时,如以上所简述的,根据调整液晶层的取向的方案,LCD装置的模式包括扭曲向列(TN)模式、垂直取向(VA)模式、面内开关(IPS)模式和边缘场开关(FFS)模式。在这些模式中的IPS模式和FFS模式中,像素电极和公共电极设置在下基板上并且液晶层的取向通过像素电极和公共电极之间的电压差所生成的电场来调整。
在IPS模式中,像素电极和公共电极交替平行排列,由此在像素电极和公共电极之间生成横向电场,并且调整液晶层的取向。在IPS模式中,在像素电极和公共电极上的上部中液晶层的取向未得到调整,从而在与上部对应的区域中光的透过率降低。
已经开发了FFS模式来解决IPS模式的缺点。在FFS模式中,像素电极和公共电极通过像素电极和公共电极之间的绝缘层而形成为彼此隔开,其中一个电极形成为板的形状或图案,另一电极形成为指状,由此通过两个电极之间生成的边缘场来调整液晶层的取向。
期望的是,根据本发明的实施方案的LCD装置具有以上所述的FFS模式LCD装置的结构。然而,本发明的实施方案不限于此。
此外,应用本发明的实施方案的LCD装置包括:阵列基板;以及给液晶面板提供光的背光单元和驱动电路单元。驱动电路单元包括时序控制器(T-con)、数据驱动器(D-IC)、栅极驱动器(G-IC)、背光驱动单元以及将驱动电力提供给驱动电路的电源。此外,驱动电路单元的全部或部分可以通过玻载芯片(COG)法或者柔性印刷电路载芯片或膜载芯片(COF)法而形成在液晶面板上,并且将省略背光单元、驱动电路单元等的详细构造的描述。
在图1B所示的截面图中,作为可应用本发明的实施方案的LCD装置,示出了FFS模式中的所谓的公共电压电极在顶部(VOT)的示例,其中公共电压电极或公共电极(Vcom)位于阵列基板或下基板的最上部处。
然而,本发明的实施方案不限于VOT型和FFS模式的LCD装置。下面将更详细地描述VOT型和FFS模式的LCD装置。
此外,在可应用本发明的实施方案的阵列基板的示例中,使用下部第一无机钝化层(PAS1)、在PAS1上的有机钝化层(PAC)、以及在PAC上的第二无机钝化层(PAS2)作为钝化层。
无机钝化层可以由无机绝缘材料例如氮化硅(SiNx)、氧化硅(SiO2)等形成,有机钝化层可以由例如光丙烯酸类物质、丙烯酸酯、聚酰胺等材料形成。然而,本发明的实施方案不限于此。
更详细地描述可应用本发明的实施方案的阵列基板的横截面。首先,在基板例如有机基板上形成栅极金属层,并且通过包括光刻工艺的图案化工艺并使用栅极掩模由栅极金属层形成包括栅电极182的栅极金属层或栅极金属图案。
在栅极金属层上形成栅极绝缘体(GI),在GI上形成用于形成TFT的沟道的半导体层184,并且在半导体层184上形成包括源电极185和漏电极186的S/D金属层或S/D金属图案。
同时,虽然如上所述,在有源区中的TFT部中形成栅极金属层、GI、半导体层184′和S/D金属层,但是在应用本发明实施方案的非有源区的钝化孔区(图1B的右部)中可以在基板上形成GI、半导体层184′和S/D金属图案185′。
在这种情况下,可以在S/D金属图案185′上依次层叠第一无机钝化层(PAS1)187和有机钝化层(PAC)188,并且通过使用钝化层掩模的光刻工艺等移除PAS1187的一部分以及PAC 188的一部分来形成孔。
具体地,在有源区的TFT区中形成用于将漏电极186连接至像素电极189的漏极接触孔200,并且通过同一工艺在非有源区中形成在本说明书中所限定的非有源区中的钝化孔300。
同时,在有源区中,通过在PAC 188上层叠/图案化由透明电极材料形成的像素电极层来形成像素电极189,并且通过上述漏极接触孔200将像素电极189电连接至漏电极186。
然而,在对像素电极层进行图案化的过程期间,在非有源区中,具体地在非有源区的钝化孔300的区域中,没有形成像素电极图案。因此,在钝化孔300的露出的S/D金属图案185′上层叠第二无机钝化层(PAS2)190以与露出的S/D金属图案185′接触。
图2A为示出可应用本发明的实施方案的钝化孔区的放大平面图,图2B至图2D为各自示出可应用本发明的实施方案的钝化孔区的放大截面图。
如平面图所示,在非有源区中形成有多个钝化孔16,并且可以将集合所述多个钝化孔16的区域定义为钝化孔集合区17。
如图2B所示,当从横截面观察各个钝化孔16时,从下部形成有机衬底181、GI 183、半导体层184′和S/D金属图案185′,并且在S/D金属图案185′上层叠PAS1 187和PAC 188。然后,通过移除PAS1 187和PAC188这两个钝化层的一部分来形成钝化孔300,并且在钝化孔300上层叠PAS2 190。如从该横截面结构可以看出的,在钝化孔300的区域中S/D金属图案185′与PAS2 190直接接触。S/D金属层通常由具有低电阻的金属材料例如铜(Cu)、铜合金、铝(Al)、铝合金(AlNd)等形成,PAS2通常由无机绝缘材料例如氮化硅(SiNx)、氧化硅(SiO2)等形成。因此,接触材料之间的粘合强度由于接触材料的异质性而变弱。
具体地,如图2C所示,为了形成钝化孔300,可以层叠PAS1 187和PAC,实施光刻工艺,并且实施干蚀刻以移除与钝化孔300对应的部分的钝化层。在通过干蚀刻工艺而露出的S/D金属图案185′暴露于等离子体时,可以形成预定厚度的金属氧化物层185″。
例如,在S/D金属层由铜(Cu)形成的情况下、可以在S/D金属层上形成作为氧化层的氧化铜(CuO)层。
由于金属氧化物层185″,所以金属氧化物层185″与沉积在金属氧化物层185″上的PAS2 190之间的粘合强度变弱。因此,如图2D所示,在钝化孔区中可出现S/D金属图案185′和位于S/D金属图案185′上方的PAS2 190之间的接合面的层离现象。由于接合面的层离现象,PAS2 190的一部分可作为钝化异物190′从PAS2 190剥离。
如上所述,由于在钝化孔区中S/D金属图案与位于S/D金属图案上方的钝化层的粘合强度不足而引起接合面的层离现象从而在钝化孔区中引起损伤。具体地,在此时所产生的钝化异物190′到达有源区并且固定于有源区的情况下,在实施后续工艺时,钝化异物190′在有源区引起燥点等。因此,整体上降低了阵列基板的良品率。
之所以在制造阵列基板的过程中出现上述现象,原因是:形成像素电极层,然后在对像素电极图案进行图案化的过程期间在非有源区的钝化孔区中没有产生像素电极图案。
具体地,这是因为通过使用PAC掩模非有源区的钝化孔区没有被图案化并且在非有源区的钝化孔区中没有形成像素电极图案,在PAS1和PAC中形成有钝化孔的情况下,在整个基板上沉积由透明导电材料形成的像素电极层,并且在将作为光敏材料的光致抗蚀剂涂覆在像素电极层上之后在该像素电极层中实施光刻工艺,通过使用PAC掩模将涂覆的光致抗蚀剂曝光,并进行显影。
在这方面,为了解决上述问题,本发明的实施方案提供了一种方法,该方法防止了由于在钝化孔区中S/D金属图案和钝化层的粘合强度不足而引起的层离现象,并且在包括在LCD面板中的阵列基板的非有源区的钝化孔区中通过在S/D金属图案和位于S/D金属图案上方的钝化层之间形成下透明电极图案作为S/D金属图案的盖层而防止了显示装置由于钝化异物而引起的故障。
图3和图4示出根据本发明的实施方案的制造用于液晶显示面板的阵列基板的方法的整体流程,其中图3为示出重点在钝化孔区的过程的流程图并且图4为示出制造阵列基板的整体过程的流程图。
参照图3,根据本发明的实施方案,制造显示面板的方法可以包括:第一步骤S310,在钝化孔区中形成GI、S/D金属图案和下钝化层;第二步骤S320,通过移除在钝化孔区中的下钝化层露出S/D金属图案;第三步骤S330,在钝化孔区中露出的S/D金属图案上形成下透明电极图案作为S/D盖层;以及第四步骤S340,在钝化孔区中在下透明电极图案上形成PAS2作为上钝化层;其中,所述显示面板包括有源区和包含钝化孔区的非有源区,并且具有依次形成在有源区的TFT区中的栅极金属图案、GI、半导体层、S/D金属层、下钝化层、下透明电极层、上钝化层和上透明电极层。
根据本发明的实施方案,下钝化层可以为包括PAS1和PAC的双钝化层。然而,本发明的实施方案不限于此。因此,下钝化层可以包括仅一个或更多个无机钝化层。
在下文中,将描述作为包括PAS1和PAC的下钝化层的示例的实例。
图5A至图5E为在制造如图3所示的阵列基板的过程中的截面图。在下文中,将通过图5A至图5E参照图3详细描述各过程的详细构成。
首先,在图3所示的过程S310中,如图5A所示,在玻璃基板510上形成包括栅电极515的栅极金属图案,在栅极金属图案上在整个基板表面上形成GI 520,并且在GI 520上形成半导体层图案530和S/D金属图案。
可以在有源区的TFT区(图5A至图5E中的各图中的左部)和非有源区的钝化孔区(图5A至图5E中的各图中的右部)两者中形成半导体层图案和S/D金属图案。形成在有源区中的S/D金属图案包括连接至数据线(未示出)的源电极542和漏电极544。
不言而喻,也可以在非有源区的钝化孔区中形成半导体层图案530和S/D金属图案540。根据情形,可以在非有源区的钝化孔区中不形成半导体层图案530。
下面将参照图4更加详细地描述图3所示的过程S310。
首先,作为形成栅极金属图案的过程,在步骤S405中,在整个玻璃基板510上沉积栅极金属层,然后通过使用栅极掩模的光刻工艺和蚀刻工艺等来图案化为包括栅电极515的栅极金属图案等。
光刻工艺用于将沉积的层图案化为预定形状的图案。在光刻工艺中,在沉积的层上涂覆具有光敏性的光致抗蚀剂,在将预定图案化的掩模设置在光致抗蚀剂上的情况下将光致抗蚀剂曝光(例如紫外射线等)(曝光工艺),并且对光致抗蚀剂进行显影。因此,只有与掩模图案对应的光致抗蚀剂层保留。在这种情况下,通过例如干蚀刻过程移除层的没有保留光致抗蚀剂的部分的材料,由此层的仅保留光致抗蚀剂的部分被保留。
通过上述过程可以在相关层上形成与相关掩模的图案对应的图案。通过掩模没有紫外射线曝光的部分形成为图案的类型为正型。相对地,曝光的部分(光穿透部分)形成为图案的类型为负型。
在下文中,通过光刻工艺在预定层上形成图案将被称为“沉积、曝光(光)和蚀刻的过程”。
在步骤S405中被图案化为栅极金属图案的示例可以包括TFT区中的栅电极515、有源区中的栅极线(未示出)、非有源区中的栅极焊盘、公共电极线(Vcom线)等。然而,在本说明书所限定的钝化孔区中没有形成在S405中被图案化的栅极金属图案。
栅极金属图案可以由选自具有低电阻的金属中的一种或更多种材料例如铜(Cu)、铜合金、铝(Al)、铝合金(AlNd)、钼(Mo)以及钼合金(MoTi)形成,但不限于此。
在如上所述形成栅极金属图案之后,在栅极金属图案上形成GI 520。在步骤S410中,GI 520可以由例如氮化硅(SiNx)、氧化硅(SiO2)等材料形成为几千的厚度,并且可以通过经由化学气相沉积(CVD)法沉积正硅酸四乙酯(TEOS)或中温氧化物(MTO)来形成。
在步骤S415中,在GI 520上沉积半导体层。半导体层用于在源电极542和漏电极544之间形成沟道,并且可以称为有源层。半导体层可以由非晶硅(a-Si)和N+掺杂层形成,或者可以由钼钛(MoTi)和N+掺杂层形成。
在步骤S420中,在半导体层上沉积S/D金属层,并且使用源极掩模通过光刻工艺和湿蚀刻工艺来形成具有预定图案的S/D金属图案。
如图5A至图5E所示,S/D金属图案可以包括在有源区中的源电极542和漏电极544,并且如图5A的右部所示,在非有源区的钝化孔区中S/D金属图案形成为S/D金属图案540。
与栅极金属层的情况一样,S/D金属层可以由选自具有低电阻的金属例如铜(Cu)、铜合金、铝(Al)、铝合金(AlNd)、钼(Mo)以及钼合金(MoTi)中的一种或更多种材料形成,但不限于此。
如图5A至图5E所示,S/D金属图案可包括在有源区中的源电极542和漏电极544以及在非有源区中的S/D金属图案540,并且,尽管未示出,S/D金属图案还可包括在有源区中的数据线、在非有源区中的数据焊盘等。
上述源极掩模可以为半色调掩模或衍射掩模。在使用半色调掩模的情况下,通过使用一个掩模、光刻工艺和两个蚀刻工艺,可以图案化为S/D金属图案并且可以在S/D金属图案下图案化为半导体层图案。
具体地,在步骤S425中,通过S/D金属层的上述沉积、曝光和湿蚀刻形成S/D金属图案之后,可以通过再次干蚀刻半导体层来形成图5A所示的半导体层图案。
通过图案化为S/D金属图案的过程S420以及图案化半导体层的过程,如图5A的右部所示,在非有源区的钝化孔区中还形成各自具有预定图案的半导体层图案530和S/D金属图案540。
然而,根据情形,在非有源区的钝化孔区中可以不形成半导体层图案530。
在步骤S430中,在基板的整个表面上沉积PAS1,并且在步骤435中在PAS1上沉积PAC。
PAS1 550可以由无机绝缘材料例如氮化硅(SiNx)形成为几千的厚度,并且根据情形,PAS1 550可以由包含硅(Si)、氧(O)和碳(C)的可溶材料或者例如硅化物、硅氧烷、聚硅氧烷等材料形成。
PAC 560由具有光硬化特性的有机绝缘材料(例如光丙烯酸类物质、苯并环丁烯(BCB)等)形成在PAS1 550上,并且可以具有约1μm至2μm的厚度,但不限于此。
通常,PAC比PAS1厚,并且PAS1的材料具有大电阻从而具有大的电容分量,例如通过上金属图案和下金属图案形成的寄生电容等,而作为PAC的材料的光丙烯酸类物质不能使大寄生电容生成。
具体地,使用PAC的原因是,有机绝缘材料例如光丙烯酸类物质具有相对小的电阻和相对大的介电常数,这使寄生电容的生成最小化从而在工艺方面是有利的,即使PAC由有机绝缘材料形成为比无机钝化层或无机绝缘膜(PAS)的厚度大的厚度也是如此。工艺方面的优点在于,有机绝缘材料具有光硬化特性从而可以直接使用有机绝缘膜作为有机钝化层,其中该有机绝缘膜在刚刚进行有机绝缘材料的曝光、显影和蚀刻之后保留,无需沉积单独的光致抗蚀剂,而对于图案化,只有在通过对保留的光致抗蚀剂等进行曝光、显影、蚀刻、移除来完全移除沉积在无机钝化层(PAS)上的光致抗蚀剂之后,无机钝化层(PAS)才能够行进至下一步骤。
然而,在PAC的情况下,PAS1 550用于防止在如下情况中可发生的沟道的污染和TFT的特性劣化:上述情况为金属层(即,S/D金属层)与位于PAC下方的半导体层之间的粘合强度降低以及有机绝缘材料与半导体层材料接触。
在上述情况中,可以将PAS1 550和PAC 560的双层结构作为一个元件定义成下钝化层。
然而,如上所述,本发明的实施方案不限于下钝化层包括PAS1和PAC的实施方案,而是还可以包括下钝化层包括仅一个或更多个无机钝化层的实施方案。
同时,在步骤S435中,沉积PAS1 550和PAC 560,并且使用PAC掩模等通过光刻工艺进行曝光。
由于作为PAC 560的材料的光丙烯酸类物质具有光硬化特性,所以PAC 560的材料的通过PAC掩模曝光的部分硬化,并且在步骤S440中,通过在该状态下实施干蚀刻来对PAC560和位于PAC 560下面的PAS1进行图案化。
已经描述了沉积PAS1和PAC并且然后通过使用一个掩模(即,PAC掩模)以及曝光和蚀刻工艺对PAS1和PAC同时进行图案化。然而,不言而喻,根据情形,在对PAS1和PAC进行图案化时,可以单独实施掩模工艺以及曝光和蚀刻工艺。具体地,可以单独实施通过沉积PAS1、使用PAS掩模的光刻工艺和蚀刻而进行的图案化PAS1的过程以及通过沉积PAC、使用PAC掩模的光刻工艺和蚀刻而进行的图案化PAC的过程。
如图5B所示,在经过图案化PAC的过程之后,在有源区的TFT区中的漏电极部处形成有用于漏极接触孔的第一孔洞565,同时,在非有源区中形成根据本发明的实施方案的用于钝化孔的第二孔洞565′。
在步骤S450中,在各第一孔洞565和各第二孔洞565′上沉积下透明电极层,然后进行图案化。
可以将本发明的实施方案应用于在作为下基板的阵列基板上形成有透明像素电极和透明公共电极的IPS型或FFS型的LCD装置。FFS型显示面板的示例包括在基板的最上部在***有一个层间绝缘层的情况下形成有透明像素电极的POT型显示面板以及在基板的最上部上形成有透明公共电压电极(Vcom)的VOT型显示面板。
在图5A至图5E中,示出了VOT型显示面板的示例,但本发明的实施方案不限于此。如图7等所示,本发明的实施方案还可应用于POT型显示面板等。
因此,在图5所示的实施方案中,在沉积并形成下透明电极(ITO)层之后,将下透明电极(ITO)图案化以在有源区中形成像素电极570′,并且在露出的S/D金属图案上形成下透明电极图案570以与非有源区的钝化孔区中的露出的S/D金属图案接触。
更具体地,在通过上述的图案化PAS1和图案化PAC的工艺来形成有源区中的漏极接触孔孔洞565以及钝化孔孔洞565′的情况下,在基板的整个表面上沉积下透明电极材料层。然后,在下透明电极材料层的整个表面上涂覆光致抗蚀剂,通过使用其中形成有预定图案的下透明电极掩模来使所涂覆的光致抗蚀剂曝光,并且实施湿蚀刻,由此形成下透明电极图案570、以及作为下透明电极图案的像素电极图案570′。具体地,在有源区中下透明电极图案形成为像素电极(PXL)图案,并且在非有源区的钝化孔区中下透明电极图案形成为作为覆盖S/D金属图案的S/D盖层的下透明电极图案570(步骤S450并且参照图5C)。
在本示例中,下透明电极材料可以为具有相对大的功函数值的透明导电材料,例如铟锡氧化物(ITO)或铟锌氧化物(IZO),但不限于此。
为了方便起见,在本说明书中,透明电极材料或透明电极层将代表性地描述为ITO。
如上所述,与图2A至图2D所示的情况不同,在VOT型显示面板中中的有源区中图案化为像素电极层的下透明电极图案时,在非有源区中的钝化孔区中也形成下透明电极图案。
在形成具有图2A至图2D所示的结构的钝化孔的过程中,用于图案化像素电极层的掩模在非有源区的钝化孔区中不具有形成在上述掩模中的特定图案,因而在钝化孔区中没有形成下透明电极图案。相对地,在图5A至图5E所示的实施方案中,在图案化下透明电极期间所使用的下透明电极掩模或像素电极掩模具有与甚至在非有源区的钝化孔区中的钝化孔对应的预定图案,因而使得图案化能够实施以在甚至非有源区的钝化孔区中形成作为覆盖露出的S/D金属图案540的盖层的下透明电极图案570。
在钝化孔区中如上形成的下透明电极图案570用作位于下透明电极图案下面的S/D金属图案540与位于S/D金属图案540上的上钝化层(PAS2)之间的接合层。因此,可以解决图2A至图2D中的由于S/D金属图案与位于S/D金属图案上方的上钝化层的粘合强度不足而引起的问题。
在图案化像素电极图案570′和下透明电极图案570的过程之后,在基板的整个表面上对作为上钝化层的PAS2 580进行图案化(步骤455并且参照图5D)。换言之,沉积由无机绝缘材料(例如氮化硅(SiNx))形成的层并且使用钝化层掩模通过光刻工艺和干蚀刻工艺来形成具有预定图案的PAS2图案。
在步骤S460中,在PAS2上形成作为上透明电极层的公共电极图案。具体地,在基板的整个表面上沉积由透明导电材料(例如铟锡氧化物(ITO)或铟锌氧化物(IZO))形成的层,然后使用上透明电极掩模或公共电极掩模通过曝光和湿蚀刻形成有源区中的公共电极(Vcom)图案590。如图5E所示,对于各像素,公共电极(Vcom)图案590可以具有指状。
同时,将本发明的实施方案所限定的钝化孔限定为包括通过移除钝化层的位于如下部分上的部分来开口的所有孔洞、所有孔和所有接触孔,该部分处于在阵列基板的非有源区中形成S/D金属图案的地方。可以在通过移除钝化层的一部分而开口的这样的区域中形成附加层例如另一钝化层等。
钝化孔的主要目的主要包括:测量尺寸的目的;测量S/D金属图案的电特性的目的;构造静电防护电路的一部分的目的等,但不限于此。
下面更详细的描述各个目的。形成漏极接触孔以用于露出包括在有源区中的TFT中的漏电极,并且必须精确测量漏极接触孔的尺寸。然而,漏极接触孔具有小尺寸,并且形成为用于大量像素中的各像素,因而难以精确测量所有漏极接触孔的尺寸。为此,可以使用钝化孔。如图5A至图5E所示,通过与在有源区中形成漏极接触孔的工艺相同的工艺形成非有源区的钝化孔,并且钝化接触孔具有比漏极接触孔的尺寸大的尺寸。因此,在测量针对钝化孔的目标尺寸的钝化孔的实际尺寸时,可以知道工艺的精确度。由于精确度与形成漏极接触孔的工艺的精确度相同,所以可以测量漏极接触孔的尺寸(临界尺寸)。
同时,在钝化孔区中形成S/D金属图案,并且如上所述在非有源区中需要S/D金属图案的部分是连接至栅极金属图案的部分。具体地,该部分的示例包括:将公共电极线(Vcom线)连接至有源区的部分;在有源区中将栅极焊盘连接至栅极线的部分;在有源区中将数据集成电路(IC)连接至数据线的部分等。如上所述,甚至在非有源区中,也存在需要在S/D金属图案上方形成孔洞的许多情况,并且孔洞能够实现S/D金属层的电特性的测量。
另外,钝化孔可以用于:用于测量电特性的虚拟图案(***除有源区和母玻璃基板之外的面板部分中);存在层交叠的区域(例如,S/D和PAC)的用于尺寸测量的图案等。
此外,例如以三个晶体管彼此连接的形式存在于非有源区中的静电防护电路需要用于使S/D金属图案露出外部的孔洞,因而在这种情况下可以使用根据本发明的实施方案钝化层孔洞。
同时,下面将总结如图4所示的根据本发明的实施方案的制造阵列基板的全部过程。
实施如下过程:S405和S410,在基板上形成栅极金属图案并且在栅极金属图案上形成GI;S415、S420和S425,沉积半导体层并且使用一个或更多个掩模通过光刻工艺在有源区和非有源区两者中形成S/D金属图案;以及S430、S435和S440,沉积作为下钝化层的PAS1和PAC并且通过移除下钝化层在钝化孔区中的一部分来形成钝化孔。
另外,全部过程可以包括:下透明电极图案化过程S450,沉积作为下透明电极层的像素电极层并且通过使用下透明电极掩模在钝化孔区中在S/D金属图案上形成下透明电极图案作为S/D盖层;以及在下透明电极图案的整个表面上形成作为上钝化层的PAS2的过程。
图6A和图6B为示出根据本发明的实施方案制造的阵列基板的平面图,图6C和图6D为示出根据本发明的实施方案制造的阵列基板的截面图。
如图6A所示,在阵列基板的非有源区中形成一个或更多个钝化孔600,并且如上所述在所述一个或更多个孔600的区域中形成有作为S/D盖层的下透明电极图案570。具体地,在钝化孔600的S/D金属图案与位于S/D金属图案上方的钝化层之间形成有通过与形成像素透明电极(PXL ITO)的工艺相同的工艺而形成的下透明电极图案570。因此,下透明电极图案570用于防止钝化层的层离现象和生成异物的现象。
此时,可以以如下方式对下透明电极图案570进行广泛图案化,该方式为如图6A所示完全覆盖包括多个钝化孔600的整个区域。可替代地,可以以如下方式对下透明电极图案570进行图案化,该方式为如图6B所示将各钝化孔600与另一钝化孔隔开。
同时,下面描述了存在于根据本发明的实施方案制造的阵列基板的非有源区中的钝化孔的横截面。参照图6C,定位形成在钝化孔下的S/D金属图案540,并且在通过移除形成在S/D金属图案540上的PAS1 550和PAC 560而露出的S/D金属图案540上形成下透明电极图案570,并且在下透明电极图案570上形成作为上钝化层的PAS2 580。
因此,如图6D所示,即使在通过干蚀刻有机钝化层等的工艺而露出的S/D金属图案540上形成氧化膜540′的情况下,形成在氧化膜540′上的由导电材料形成的下透明电极图案570用作一种接触媒介层。因此,可以提高S/D金属图案540与位于S/D金属图案540上方的PAS2 580的粘合强度。
因此,能够抑制通过图2A至2D所示的结构而引起的上钝化层的层离现象、由于发生层离现象导致的钝化异物而引起的故障生成等,其中图2A至图2D所示的结构也就是在钝化孔区中S/D金属图案与上钝化层直接接触的结构。
在上文中,已经将作为存在于显示面板的非有源区的钝化孔区中的S/D盖层的下透明电极图案描述成形成为像素透明电极层(PXL ITO)。可替代地,下透明电极图案可以形成为公共电极层(Vcom ITO)。
图7为示出根据本发明的另一实施方案的钝化孔区的截面图,并且示出了应用于POT型LCD装置的示例。
参照图7,在基板的最上部上形成有透明像素电极的POT型显示面板中,在PAS1和PAC上图案化为作为用于公共电压的透明电极的Vcom ITO图案670′,并且通过与上述工艺相同的工艺在钝化孔区中将公共电压透明电极670形成为下透明电极图案。作为Vcom ITO层的公共电压透明电极图案670用作S/D金属图案的盖层,因而可以提高如上所述的S/D金属图案和上钝化层(PAS2)的粘合强度。
同时,在图4至到图6A至图6D所示的VOT型阵列基板的情况下,在曝光之后实施干蚀刻以选择性移除PAS1和PAC。相对地,由于为了选择性移除PAS1和PAC,在曝光之后马上实施显影的工艺,图7所示的POT型阵列基板与VOT型阵列基板略有不同。
此时,与在显影工艺中相比,在干蚀刻工艺中暴露于等离子体的S/D金属图案的氧化可以更活跃。在这方面,与在图7所示的POT型像素面板中相比,在图5所示的VOT型像素面板中在钝化孔处的上钝化层(PAS2)的粘合强度可降低得更为严重。因此,可以更有效地使用本发明的实施方案。
然而,S/D金属图案的氧化不总是仅在干蚀刻工艺中产生,因而本发明的技术构思甚至可应用于图7所示的POT型显示面板。
此外,即使没有发生金属图案的氧化,S/D金属图案仍然直接接触与钝化孔区中的S/D金属图案在种类方面不同的PAS2,所以S/D金属图案与PAS2之间的粘合强度可降低。因此,根据图7所示的本发明的另一实施方案,在S/D金属图案与上钝化层(PAS2)之间设置有下透明电极图案(即,Vcom ITO层),由此可以提高层间粘合强度。
本发明的上述各个实施方案不一定应用于仅LCD装置的阵列基板,而是可应用于所有种类的用于显示装置的基板,其中位于预定金属图案上的无机钝化层直接接触钝化孔区中的预定金属图案或非有源区的接触孔区域,由此无机钝化层与预定金属图案之间的粘合强度可变弱。例如,本发明的上述各个实施方案可应用于OLED显示装置、PDP显示装置等的所有阵列基板。
如上所述,根据本发明的各种实施方案,在S/D金属图案与位于S/D金属图案上方的钝化层之间形成有透明电极图案(ITO),上述金属图案和钝化层形成在用于显示面板的阵列基板的非有源区的钝化孔区中。因此,可以防止在钝化孔区中钝化层的层离现象和钝化异物的剥离现象。
此外,在形成在S/D金属图案上的PAS孔或PAC孔的区域中,在S/D金属图案与位于S/D金属图案上方的钝化层之间形成有用于增强粘合强度的透明电极图案。因此,可以防止钝化层材料由于在钝化孔区中的金属层和钝化层之间粘合强度不足而产生层离现象或剥离所引起的显示故障。
具体地,在使用有机材料例如光丙烯酸类物质等的有机钝化层(PAC)并且像素透明电极或公共电压透明电极同时设置在阵列基板上的显示面板中,在存在于非有源区的钝化孔(PAC孔)区域在S/D金属层与位于S/D金属层上方的钝化层之间形成有透明电极图案。因此,可以解决在如下情况下发生的各种问题:上述情况为在干蚀刻PAC的工艺期间存在于用于测量的焊盘中的S/D金属层上形成氧化层,因而金属层与位于金属层上方的钝化层之间的粘合强度变弱。因此,可以寻求增加液晶显示面板的良品率并降低其故障率。
实际上,如下面的表1所示,根据在可应用本发明的实施方案的显示面板中的生成燥点的程度的测试结果,在如图2A至图2D所示的在钝化孔区中S/D金属图案直接接触位于S/D金属图案上的钝化层(PAS2)的结构中,在有源区中燥点的生成率达到9.08%。然而,在通过应用本发明的实施方案之中的图5A至图5E所示的构造在钝化孔区中在S/D金属图案与上钝化层PAS2之间形成像素透明电极(ITO)图案作为S/D盖层的情况下,完全没有生成燥点。
表1
虽然已经参照附图示例性描述了本发明的技术精神,但是本领域技术人员将理解的是,在未脱离本发明的范围的情况下,可以以各种形式对本发明进行改变和修改。因此,本发明中所公开的实施方案全然不进行界定,而是描述本发明的技术精神。此外,本发明的技术精神的范围不受实施方案限制。应该以如下方式基于所附权利要求理解本发明的范围,上述方式为包括在范围内的所有技术构思等同于属于本发明的权利要求。
附图标记的描述
510:基板
520:GI
540:S/D金属图案
550:PAS1
560:PAC
565&565′:第一孔洞&第二孔洞
570:下透明电极图案(PXL ITO)
570′:像素透明电极
580:PAS2
590:公共电极(Vcom)图案
670:下透明电极图案(Vcom ITO)
附记
本发明还涉及以下技术方案。
1.一种用于显示装置的阵列基板,所述阵列基板包括:
含有薄膜晶体管(TFT)区的有源区;以及
含有钝化孔区的非有源区,在所述钝化孔区中依次设置有栅极绝缘体(GI)、源极/漏极(S/D)金属图案、下透明电极图案以及上钝化层。
2.根据1所述的阵列基板,其中,在含有所述薄膜晶体管(TFT)区的所述有源区中,依次设置有栅极金属图案、栅极绝缘体(GI)、半导体层、源极/漏极(S/D)金属图案、下钝化层、下透明电极层、上钝化层和上透明电极层。
3.根据1所述的阵列基板,其中,在含有所述钝化孔区的所述非有源区中,所述下透明电极图案设置为所述S/D金属图案的盖层。
4.根据2所述的阵列基板,其中,所述下透明电极图案和所述下透明电极层由同一层形成。
5.根据1所述的阵列基板,还包括在所述钝化孔区中的源极/漏极(S/D)金属图案上的下钝化层,以及
其中,所述下钝化层包括一个或更多个有机钝化层、一个或更多个无机钝化层、或含有有机钝化层和无机钝化层的双钝化层。
6.根据2所述的阵列基板,其中,所述上钝化层和所述下钝化层中的每个由有机材料或无机材料形成,
其中,所述有机材料为光丙烯酸类物质、丙烯酸酯或聚酰胺,所述无机材料为氮化硅或氧化硅。
7.根据2所述的阵列基板,还包括设置在所述有源区中的所述下钝化层上的公共电压电极,以及
其中,所述公共电压电极和所述下透明电极图案由同一层形成。
8.根据2所述的阵列基板,其中,所述源极/漏极(S/D)金属图案和所述栅极金属图案中的每个由选自铜(Cu)、铜合金、铝(Al)、铝合金(AlNd)、钼(Mo)以及钼合金(MoTi)中的一种或更多种材料形成。
9.根据1所述的阵列基板,其中,在含有所述钝化孔区的非有源区中,在所述GI和所述源极/漏极(S/D)金属图案之间设置有半导体层。
10.根据2所述的阵列基板,其中,形成在所述有源区中的所述源极/漏极(S/D)金属图案包括源电极和漏电极。
11.根据10所述的阵列基板,其中,所述半导体层设置为用于在所述源电极与所述漏电极之间形成沟道。
12.根据5所述的阵列基板,其中,在所述双钝化层中,所述有机钝化层比所述无机钝化厚。
13.根据1所述的阵列基板,其中,在含有所述钝化孔区的所述非有源区中,所述下透明电极图案接触所述源极/漏极(S/D)金属图案。
14.根据2所述的阵列基板,其中,在含有所述薄膜晶体管(TFT)区的所述有源区中,所述下透明电极层被设置为用于形成像素电极。
15.一种制造用于显示装置的阵列基扳的方法,所述方法包括:
提供阵列基板,所述阵列基板包括含有薄膜晶体管(TFT)区的有源区和含有钝化孔区的非有源区;
在包含于所述非有源区中的所述钝化孔区中依次形成栅极绝缘体(GI)、源极/漏极(S/D)金属图案和下钝化层;
通过移除在所述钝化孔区中所述下钝化层的一部分来露出所述源极/漏极(S/D)金属图案;
在所述钝化孔区中露出的S/D金属图案上形成下透明电极图案;以及
在所述钝化孔区中的所述下透明电极图案上形成上钝化层。
16.一种制造用于显示装置的阵列基扳的方法,所述方法包括:
提供阵列基板,所述阵列基板包括含有薄膜晶体管(TFT)区的有源区和含有钝化孔区的非有源区;
在所述阵列基板上形成栅极金属图案;
在所述栅极金属图案上形成栅极绝缘体(GI);
沉积半导体层和源极/漏极(S/D)层;
在所述有源区和所述非有源区中均形成S/D金属图案;
沉积下钝化层;
通过移除在所述钝化孔区中所述下钝化层的一部分来形成所述钝化孔;
在所述有源区和所述非有源区中均沉积下透明电极层;
图案化所述下透明电极层以在所述钝化孔区中的所述S/D金属图案上形成下透明电极图案;以及
在所述阵列基板的所述有源区和所述非有源区中均形成上钝化层。
17.根据15或16所述的方法,其中,当在所述钝化孔区中形成所述下透明电极图案时,图案化在所述有源层中的所述下透明电极层以形成像素电极。
18.根据15或16所述的方法,其中,在所述钝化孔区中形成所述下透明电极图案作为在露出的S/D金属图案上的S/D盖层。
19.根据15或16所述的方法,还包括:
在所述有源区中的所述上钝化层上形成上透明电极层。
20.根据15或16所述的方法,
其中,通过采用一个或更多个有机钝化层、一个或更多个无机钝化层、或含有有机钝化层和无机钝化层的双钝化层来形成所述下钝化层。
21.根据15或16所述的方法,
其中,形成所述钝化孔包括:蚀刻所述下钝化层的与所述钝化孔对应的部分来露出所述S/D金属图案。
22.根据15或16所述的方法,其中,所述源极/漏极(S/D)金属图案形成源电极和漏电极。
23.根据16所述的方法,其中,形成在所述有源区中的所述源极/漏极(S/D)金属图案形成源电极和漏电极,以及
其中,沉积所述半导体层以用于在所述源电极与所述漏电极之间形成沟道。
24.根据15或16所述的方法,其中,在所述钝化孔区中,形成所述下透明电极图案以接触所述源极/漏极(S/D)金属图案。
25.一种显示装置,包括根据1至14中任一项所述的阵列基板。
26.根据25所述的显示装置,其中,所述显示装置选自液晶显示装置、有机发光装置、等离子显示面板或触摸装置。
Claims (25)
1.一种用于显示装置的阵列基板,所述阵列基板包括:
含有薄膜晶体管区的有源区;以及
含有钝化孔区的非有源区,在所述钝化孔区中依次设置有栅极绝缘体、源极/漏极金属图案、下透明电极图案以及上钝化层,
其中在含有所述薄膜晶体管区的所述有源区中,依次设置有栅极金属图案、栅极绝缘体、半导体层、源极/漏极金属图案、下钝化层、下透明电极层、上钝化层和上透明电极层,以及
其中在含有所述钝化孔区的所述非有源区中,所述下透明电极图案设置为完全覆盖所述源极/漏极金属图案的所述源极/漏极金属图案的盖层。
2.根据权利要求1所述的阵列基板,其中,所述下透明电极图案和所述下透明电极层由同一层形成。
3.根据权利要求1所述的阵列基板,还包括在所述钝化孔区中的源极/漏极金属图案上的下钝化层,以及
其中,所述下钝化层包括一个或更多个有机钝化层、一个或更多个无机钝化层、或含有有机钝化层和无机钝化层的双钝化层。
4.根据权利要求1所述的阵列基板,其中,所述上钝化层和所述下钝化层中的每个由有机材料或无机材料形成,
其中,所述有机材料为光丙烯酸类物质、丙烯酸酯或聚酰胺,所述无机材料为氮化硅或氧化硅。
5.根据权利要求1所述的阵列基板,还包括设置在所述有源区中的所述下钝化层上的公共电压电极,以及
其中,所述公共电压电极和所述下透明电极图案由同一层形成。
6.根据权利要求1所述的阵列基板,其中,所述源极/漏极金属图案和所述栅极金属图案中的每个由选自铜、铜合金、铝、铝合金、钼以及钼合金中的一种或更多种材料形成。
7.根据权利要求6所述的阵列基板,其中所述铝合金为AlNd,以及所述钼合金为MoTi。
8.根据权利要求1所述的阵列基板,其中,在含有所述钝化孔区的非有源区中,在所述栅极绝缘体和所述源极/漏极金属图案之间设置有半导体层。
9.根据权利要求1所述的阵列基板,其中,形成在所述有源区中的所述源极/漏极金属图案包括源电极和漏电极。
10.根据权利要求9所述的阵列基板,其中,所述半导体层设置为用于在所述源电极与所述漏电极之间形成沟道。
11.根据权利要求3所述的阵列基板,其中,在所述双钝化层中,所述有机钝化层比所述无机钝化厚。
12.根据权利要求1所述的阵列基板,其中,在含有所述钝化孔区的所述非有源区中,所述下透明电极图案接触所述源极/漏极金属图案。
13.根据权利要求1所述的阵列基板,其中,在含有所述薄膜晶体管区的所述有源区中,所述下透明电极层被设置为用于形成像素电极。
14.一种制造用于显示装置的阵列基板的方法,所述方法包括:
提供阵列基板,所述阵列基板包括含有薄膜晶体管区的有源区和含有钝化孔区的非有源区;
在包含于所述非有源区中的所述钝化孔区中依次形成栅极绝缘体、源极/漏极金属图案和下钝化层;
通过移除在所述钝化孔区中所述下钝化层的一部分来露出所述源极/漏极金属图案;
在所述钝化孔区中露出的源极/漏极金属图案上形成下透明电极图案;以及
在所述钝化孔区中的所述下透明电极图案上形成上钝化层,
其中在含有所述薄膜晶体管区的所述有源区中,依次设置有栅极金属图案、栅极绝缘体、半导体层、源极/漏极金属图案、下钝化层、下透明电极层、上钝化层和上透明电极层,以及
其中在含有所述钝化孔区的所述非有源区中,所述下透明电极图案设置为完全覆盖所述源极/漏极金属图案的所述源极/漏极金属图案的盖层。
15.一种制造用于显示装置的阵列基板的方法,所述方法包括:
提供阵列基板,所述阵列基板包括含有薄膜晶体管区的有源区和含有钝化孔区的非有源区;
在所述阵列基板上形成栅极金属图案;
在所述栅极金属图案上形成栅极绝缘体;
沉积半导体层和源极/漏极层;
在所述有源区和所述非有源区中均形成源极/漏极金属图案;
沉积下钝化层;
通过移除在所述钝化孔区中所述下钝化层的一部分来形成所述钝化孔;
在所述有源区和所述非有源区中均沉积下透明电极层;
图案化所述下透明电极层以在所述钝化孔区中的所述源极/漏极金属图案上形成下透明电极图案;以及
在所述阵列基板的所述有源区和所述非有源区中均形成上钝化层,
其中在含有所述薄膜晶体管区的所述有源区中,依次设置有栅极金属图案、栅极绝缘体、半导体层、源极/漏极金属图案、下钝化层、下透明电极层、上钝化层和上透明电极层,以及
其中在含有所述钝化孔区的所述非有源区中,所述下透明电极图案设置为完全覆盖所述源极/漏极金属图案的所述源极/漏极金属图案的盖层。
16.根据权利要求14或15所述的方法,其中,当在所述钝化孔区中形成所述下透明电极图案时,图案化在所述有源层中的所述下透明电极层以形成像素电极。
17.根据权利要求14或15所述的方法,其中,在所述钝化孔区中形成所述下透明电极图案作为在露出的源极/漏极金属图案上的源极/漏极盖层。
18.根据权利要求14或15所述的方法,还包括:
在所述有源区中的所述上钝化层上形成上透明电极层。
19.根据权利要求14或15所述的方法,
其中,通过采用一个或更多个有机钝化层、一个或更多个无机钝化层、或含有有机钝化层和无机钝化层的双钝化层来形成所述下钝化层。
20.根据权利要求14或15所述的方法,
其中,形成所述钝化孔包括:蚀刻所述下钝化层的与所述钝化孔对应的部分来露出所述源极/漏极金属图案。
21.根据权利要求14或15所述的方法,其中,所述源极/漏极金属图案形成源电极和漏电极。
22.根据权利要求15所述的方法,其中,形成在所述有源区中的所述源极/漏极金属图案形成源电极和漏电极,以及
其中,沉积所述半导体层以用于在所述源电极与所述漏电极之间形成沟道。
23.根据权利要求14或15所述的方法,其中,在所述钝化孔区中,形成所述下透明电极图案以接触所述源极/漏极金属图案。
24.一种显示装置,包括根据权利要求1至13中任一项所述的阵列基板。
25.根据权利要求24所述的显示装置,其中,所述显示装置选自液晶显示装置、有机发光装置、等离子显示面板或触摸装置。
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CN104752343B (zh) * | 2015-04-14 | 2017-07-28 | 深圳市华星光电技术有限公司 | 双栅极氧化物半导体tft基板的制作方法及其结构 |
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JP2017076010A (ja) * | 2015-10-13 | 2017-04-20 | パナソニック液晶ディスプレイ株式会社 | 表示装置 |
CN105319792B (zh) * | 2015-11-16 | 2019-01-04 | 深圳市华星光电技术有限公司 | 阵列基板及液晶显示面板 |
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CN108461403A (zh) * | 2018-03-26 | 2018-08-28 | 京东方科技集团股份有限公司 | 显示面板、阵列基板、薄膜晶体管及其制造方法 |
CN108987418A (zh) * | 2018-09-11 | 2018-12-11 | 惠科股份有限公司 | 阵列基板及其制备方法和显示器件 |
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