CN104992926B - Ltps阵列基板及其制造方法 - Google Patents

Ltps阵列基板及其制造方法 Download PDF

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CN104992926B
CN104992926B CN201510443670.5A CN201510443670A CN104992926B CN 104992926 B CN104992926 B CN 104992926B CN 201510443670 A CN201510443670 A CN 201510443670A CN 104992926 B CN104992926 B CN 104992926B
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area
polysilicon layer
drain electrode
electrode
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CN104992926A (zh
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王聪
杜鹏
王笑笑
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/779,089 priority patent/US9905590B2/en
Priority to PCT/CN2015/085660 priority patent/WO2017015970A1/zh
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Abstract

本发明提供一种LTPS阵列基板及其制造方法。该方法包括：在基体上形成源极和漏极；在包括源极和漏极的基体上形成第一区域和第二区域的多晶硅层，且第一区域的多晶硅层的厚度大于第二区域的，第一区域的多晶硅层部分覆盖源极和漏极；对多晶硅层的表面进行钝化处理，以将第二区域的多晶硅层以及第一区域的多晶硅层临近表面的部分变成绝缘层；在源极和漏极之间的绝缘层上形成栅极。本发明能够简化LTPS工艺制程并降低生产成本。

Description

LTPS阵列基板及其制造方法
技术领域
本发明涉及显示技术领域，具体涉及一种LTPS(Low Temperature Poly-silicon,低温多晶硅)阵列基板及其制造方法。
背景技术
采用LTPS工艺的液晶显示装置由于具有较高的电子迁移率，能够有效减小TFT(Thin Film Transistor，薄膜晶体管)的面积以提升像素的开口率，并且在增强显示亮度的同时能够降低功耗及生产成本，目前已成为液晶显示领域的研究热点。但LTPS工艺复杂，采用CVD(Chemical vapor deposition，化学气相沉积)工艺制备的阵列基板(Array基板)的层数较多，导致制造流程繁多，无法降低生产成本。因此如何简化LTPS工艺制程，实为目前企业需要努力的目标。
发明内容
有鉴于此，本发明实施例提供一种LTPS阵列基板及其制造方法，以简化LTPS工艺制程。
本发明一实施例提供一种LTPS阵列基板的制造方法，包括：在基体上形成LTPS阵列基板的TFT的源极和漏极；在包括源极和漏极的基体上形成第一区域和第二区域的多晶硅层，且第一区域的多晶硅层的厚度大于第二区域的，除第二区域之外的第一区域的多晶硅层部分覆盖源极和漏极；对多晶硅层的表面进行钝化处理，以将第二区域的多晶硅层以及第一区域的多晶硅层临近表面的部分变成绝缘层；在源极和漏极之间的绝缘层上形成所述TFT的栅极。
其中，基体包括衬底板材及形成于衬底板材上的缓冲层。
其中，形成第一区域和第二区域的多晶硅层的步骤包括：在包括源极和漏极的基体上依次形成多晶硅层、正性光阻层；利用半透式光罩且自基体朝向正性光阻层的一侧进行曝光，以形成厚度不同的第一区域和第二区域的正性光阻层；去除第二区域的正性光阻层；刻蚀第二区域的多晶硅层以使其具有预定厚度；去除第一区域的正性光阻层。
其中，钝化处理包括氧化处理和氮化处理中的至少一个。
其中，在位于源极和漏极之间的绝缘层上形成栅极之后，所述方法还包括：向第一区域的多晶硅层与源极和漏极直接接触的两端注入第一杂质离子；向对应于栅极与源极、栅极与漏极之间的第一区域的多晶硅层注入第二杂质离子，以形成LDD结构。
其中，第一杂质离子和第二杂质离子分别为N+、N－型杂质离子。
其中，在位于源极和漏极之间的绝缘层上形成栅极之后，所述方法还包括：向第一区域的多晶硅层与所述源极和所述漏极直接接触的两端注入P型杂质离子，以形成LDD结构。
其中，在形成LDD结构之后，所述方法还包括：在包括栅极的基体上形成平坦层，并在平坦层内形成接触孔以暴露漏极的表面；在除对应TFT之外的平坦层上形成LTPS阵列基板的公共电极层；在平坦层和公共电极层上形成钝化层，且钝化层未覆盖接触孔；在钝化层上形成像素电极，并且像素电极可通过接触孔与漏极电连接。
本发明另一实施例提供一种LTPS阵列基板，包括：基体；源极和漏极，位于基体上；多晶硅层，位于包括源极和漏极的基体上，且多晶硅层部分覆盖源极和漏极；绝缘层，位于多晶硅层以及源极和漏极上，且绝缘层由覆盖于包括源极和漏极的基体上的多晶硅层通过钝化处理得到；栅极，位于源极和漏极之间的绝缘层上；平坦层，位于包括栅极的基体上，且平坦层内形成有暴露漏极的表面的接触孔；公共电极层，位于除对应LTPS阵列基板的TFT之外的平坦层上；钝化层，位于平坦层和公共电极层上，且钝化层未覆盖接触孔；像素电极，位于钝化层上，且像素电极可通过接触孔与漏极电连接。
其中，钝化处理包括氧化处理和氮化处理中的至少一个。
本发明实施例的LTPS阵列基板及其制造方法，通过对多晶硅层的表面进行钝化处理，而无需采用CVD工艺，即可制得位于栅极与源极和漏极之间的绝缘层，相比较于CVD工艺，钝化处理的操作更加简单，从而能够简化LTPS工艺的制程并降低生产成本。
附图说明
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图；
图2是本发明的制造方法中形成源极和漏极的示意图；
图3是本发明的制造方法中形成多晶硅层的示意图；
图4是本发明的制造方法中形成绝缘层的示意图；
图5是本发明的制造方法中形成栅极的示意图；
图6是本发明的制造方法中形成像素电极的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明的LTPS阵列基板一实施例的制造方法的流程图。如图1所示，本实施例的制造方法包括以下步骤：
步骤11：在基体上形成LTPS阵列基板的TFT的源极和漏极。
所述基体用于形成液晶显示面板的LTPS阵列基板，可以为玻璃基体、塑料基体或可挠式基体。如图2所示，基体21也可以包括衬底板材211及形成于衬底板材211上的透明的缓冲层(Buffer layer)212。其中，缓冲层212为氮化硅(SiNx)层、氧化硅(SiOx)层或者两者的组合，所述缓冲层212用于防止衬底板材211内的杂质在后续工艺中向上扩散而影响之后形成的低温多晶硅薄膜的品质，所述氮化硅层和所述氧化硅层可采用CVD工艺、等离子化学气相沉积(Plasma Enhanced Chemical vapor deposition，PECVD)工艺形成，还可以采用溅射、真空蒸镀或低压化学气相沉积等方法，但不限于此。
本实施例可以利用第一光罩对形成于基体21上的第一金属层进行曝光，并在曝光后进行显影、刻蚀等图案化制程以得到形成源极S和漏极D，其中可利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对第一金属层进行蚀刻，当然也可以采用干法蚀刻。其中，所述第一金属层可以由金属，例如铝、钼、钛、铬、铜，或金属氧化物，例如氧化钛，或金属的合金或其它导电材料构成。
当然，本实施例也可以通过其他方式得到TFT的源极S和漏极D，例如采用CVD工艺、PECVD工艺、溅射、真空蒸镀或低压化学气相沉积等方法直接在基体21上形成具有预定图案的源极S和漏极D。
步骤12：在包括源极和漏极的基体上形成第一区域和第二区域的多晶硅层，且第一区域的多晶硅层的厚度大于第二区域的，除第二区域之外的第一区域的多晶硅层部分覆盖源极和漏极。
结合图3所示，形成所述第一区域Q1的多晶硅层22和所述第二区域Q2的多晶硅层22的具体过程，包括但不限于：
首先，在包括源极S和漏极D的基体21上形成一半导体层，该半导体层不仅覆盖源极S和漏极D、金属走线L，还覆盖基体21的整个上表面，而后对该半导体层采用准分子激光退火(Excimer laser annealing，ELA)工艺制得一整面的多晶硅层22，此时多晶硅层22不仅覆盖源极S和漏极D，还覆盖基体21的整个上表面，再在所述多晶硅层22上形成正性光阻层23。
然后，利用半透式光罩(Half-tone mask)且自基体21朝向正性光阻层23的一侧(图中箭头所示方向)进行曝光，对第一区域Q1的正性光阻层23的曝光强度大于对第二区域Q2的曝光强度，从而使得原本厚度均匀的正性光阻层23变为厚度不同的正性光阻层23。
接着，对曝光后的正性光阻层23进行显影处理。本实施例可在此步骤中将金属走线L上方一部分的正性光阻层23通过显影处理去除以暴露出其下方的多晶硅层22、将金属走线L上方一部分的多晶硅层22通过刻蚀处理去除以暴露出其下方的金属走线L，该金属走线L用于实现TFT与LTPS阵列基板的扫描线、数据线等讯号线的连接。
继而，通过灰化处理去除第二区域Q2的正性光阻层23，第一区域Q1的多晶硅层22在灰化处理之后的厚度小于在灰化处理之前的厚度。本步骤无需利用光罩进行曝光即可去除第二区域Q2的正性光阻层23，从而暴露出对应于第二区域Q2的多晶硅层22，相比较于现有技术，本实施例能够减少LTPS工艺使用光罩的数量。
进一步地，对暴露出的对应于第二区域Q2的多晶硅层22进行刻蚀处理，以使其厚度减少到生产所需的预定厚度。
最厚，去除第一区域Q1的正性光阻层23。
步骤13：对多晶硅层的表面进行钝化处理，以将第二区域的多晶硅层以及第一区域的多晶硅层临近表面的部分变成绝缘层。
结合图4所示，所述钝化处理可以为氧化处理，具体地，采用O2等离子体对第一区域Q1以及第二区域Q2的多晶硅层22表面进行氧化处理以产生SiOx，从而使得第一区域Q1的多晶硅层22全部变成SiOx，且使得第二区域Q2的多晶硅层22的上半层变成SiOx、下半层由于上半层的遮挡不会变成SiOx仍为多晶硅层22。SiOx作为绝缘层24，即通常所说的栅极绝缘层，相比较于传统的采用CVD工艺，钝化处理的操作更加简单，从而能够简化整个LTPS工艺的制程并降低生产成本。
所述钝化处理也可以为氮化处理，使得第一区域Q1的多晶硅层22全部变成SiNx，且使得第二区域Q2的多晶硅层22的上半层变成SiNx、下半层仍为多晶硅层22，氮化形成的SiNx作为绝缘层24。当然，所述钝化处理还可以为氧化处理和氮化处理的结合。
步骤14：在源极和漏极之间的绝缘层上形成TFT的栅极。
结合图5所示，本实施例可利用第二光罩对形成于源极S和漏极D之间的绝缘层24上的第二金属层进行曝光，并在曝光后进行显影、刻蚀等图案化制程以得到栅极G，其中可利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对第二金属层进行蚀刻，也可采用干法蚀刻，当然还可采用CVD工艺、PECVD工艺、溅射、真空蒸镀或低压化学气相沉积等方法直接在绝缘层24上形成具有预定图案的栅极G。
其中，在形成栅极G的同时也金属走线L的上方形成金属层，从而使得金属走线L可以与后续形成的例如公共电极电连接。
在形成TFT的栅极G之后，本实施例进一步对多晶硅层22进行掺杂处理以使得TFT具有LDD(Lightly Doped Drain，轻掺杂漏极)结构。具体而言，向第一区域Q1的多晶硅层22与源极S和漏极D直接接触的两端注入第一杂质离子，即对第一区域Q1的多晶硅层22进行传统意义上的重掺杂处理，从而可实现源极S和漏极D与第一区域Q1的多晶硅层22之间的欧姆接触，而后，刻蚀栅极G使其宽度减小以暴露出下方的对应于栅极G与源极S以及栅极G与漏极D之间的多晶硅层22，向对应于栅极G与源极S之间的、栅极G与漏极D之间的第一区域Q1的多晶硅层22注入第二杂质离子，即对第一区域Q1的多晶硅层22进行传统意义上的轻掺杂处理，从而形成LDD结构。
本实施例的第一杂质离子可以为N+型杂质离子，对应地第二杂质离子为N－型杂质离子，但是当第一杂质离子为P+型杂质离子时无需掺杂第二杂质离子，即省略了轻掺杂处理的步骤。
如图6所示，本发明实施例的制造方法还包括以下步骤：
在绝缘层24内开设接触孔O，以暴露漏极D的表面。
在包括栅极G的基体21上形成平坦层25，并在平坦层25内形成接触孔O以暴露漏极D的表面。其中，本实施例可以利用第三光罩经曝光、显影处理、刻蚀处理得到所述接触孔O。
在除对应TFT之外的平坦层25上形成LTPS阵列基板的公共电极层26。其中，本实施例可以利用第四光罩经曝光、显影处理、刻蚀处理得到具有预定图案的公共电极层26。
在平坦层25和公共电极层26上形成钝化层27，且钝化层27未覆盖接触孔O。其中，本实施例可以利用第五光罩经曝光、显影处理、刻蚀处理得到具有预定图案的钝化层27，当然，本实施例也可以采用化学气相沉积、等离子化学气相沉积形成、溅射、真空蒸镀或低压化学气相沉积等方法直接形成具有预定图案的钝化层27。
在钝化层27上形成像素电极28，并且像素电极28可通过接触孔O与漏极D电连接。其中，本实施例可以利用第六光罩经曝光、显影处理、刻蚀处理得到具有预定图案的像素电极28。另外，TFT的栅极G与形成于基体21(LTPS阵列基板)上的栅极线对应电连接，TFT的源极S与形成于LTPS阵列基板上的数据线对应电连接，栅极线和数据线垂直交叉形成像素电极28所在的像素显示区域。
本发明实施例进一步提供一种具有图6所示LTPS阵列面板的液晶显示面板以及液晶显示器，与其具有相同的有益效果。
在此基础上，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种低温多晶硅阵列基板的制造方法，其特征在于，包括：
在基体上形成所述低温多晶硅阵列基板的薄膜晶体管的源极和漏极；
在包括所述源极和所述漏极的所述基体上形成第一区域和第二区域的多晶硅层，且所述第一区域的多晶硅层的厚度大于所述第二区域的，除所述第二区域之外的所述第一区域的多晶硅层部分覆盖所述源极和所述漏极；
对所述多晶硅层的表面进行钝化处理，以将所述第二区域的多晶硅层以及所述第一区域的多晶硅层临近表面的部分变成绝缘层；
在所述源极和所述漏极之间的所述绝缘层上形成所述薄膜晶体管的栅极。
2.根据权利要求1所述的方法，其特征在于，所述基体包括衬底板材及形成于所述衬底板材上的缓冲层。
3.根据权利要求1所述的方法，其特征在于，所述在包括所述源极和所述漏极的所述基体上形成第一区域和第二区域的多晶硅层的步骤包括：
在包括所述源极和所述漏极的所述基体上依次形成多晶硅层、正性光阻层；
利用半透式光罩且自所述基体朝向所述正性光阻层的一侧进行曝光，以形成厚度不同的第一区域和第二区域的正性光阻层；
去除所述第二区域的正性光阻层；
刻蚀所述第二区域的多晶硅层以使其具有预定厚度；
去除所述第一区域的正性光阻层。
4.根据权利要求1所述的方法，其特征在于，所述钝化处理包括氧化处理和氮化处理中的至少一个。
5.根据权利要求1所述的方法，其特征在于，所述在位于所述源极和所述漏极之间的所述绝缘层上形成栅极之后，所述方法还包括：
向所述第一区域的多晶硅层与所述源极和所述漏极直接接触的两端注入第一杂质离子；
向对应于所述栅极与所述源极、所述栅极与所述漏极之间的所述第一区域的多晶硅层注入第二杂质离子，以形成轻掺杂漏极结构。
6.根据权利要求5所述的方法，其特征在于，所述第一杂质离子为N+型杂质离子，且所述第二杂质离子为N－型杂质离子。
7.根据权利要求1所述的方法，其特征在于，所述在位于所述源极和所述漏极之间的所述绝缘层上形成栅极之后，所述方法还包括：
向所述第一区域的多晶硅层与所述源极和所述漏极直接接触的两端注入P型杂质离子，以形成轻掺杂漏极结构。
8.根据权利要求5～7任意一项所述的方法，其特征在于，在形成轻掺杂漏极结构之后，所述方法还包括：
在包括所述栅极的所述基体上形成平坦层，并在所述平坦层内形成接触孔以暴露所述漏极的表面；
在除对应所述薄膜晶体管之外的所述平坦层上形成所述低温多晶硅阵列基板的公共电极层；
在所述平坦层和所述公共电极层上形成钝化层，且所述钝化层未覆盖所述接触孔；
在所述钝化层上形成像素电极，并且所述像素电极通过所述接触孔与所述漏极电连接。
9.一种低温多晶硅阵列基板，其特征在于，所述低温多晶硅阵列基板包括：
基体；
源极和漏极，位于所述基体上；
多晶硅层，位于包括所述源极和所述漏极的所述基体上，且所述多晶硅层部分覆盖所述源极和所述漏极；
绝缘层，位于所述多晶硅层以及所述源极和所述漏极上，且所述绝缘层由覆盖于包括所述源极和所述漏极的所述基体上的多晶硅层通过钝化处理得到；
栅极，位于所述源极和所述漏极之间的所述绝缘层上；
平坦层，位于包括所述栅极的所述基体上，且所述平坦层内形成有暴露所述漏极的表面的接触孔；
公共电极层，位于除对应所述低温多晶硅阵列基板的薄膜晶体管之外的所述平坦层上；
钝化层，位于所述平坦层和所述公共电极层上，且所述钝化层未覆盖所述接触孔；
像素电极，位于所述钝化层上，且所述像素电极通过所述接触孔与所述漏极电连接。
10.根据权利要求9所述的低温多晶硅阵列基板，其特征在于，所述钝化处理包括氧化处理和氮化处理中的至少一个。
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