CN104979394B - The formed method of semiconductor device - Google Patents
The formed method of semiconductor device Download PDFInfo
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- CN104979394B CN104979394B CN201410147865.0A CN201410147865A CN104979394B CN 104979394 B CN104979394 B CN 104979394B CN 201410147865 A CN201410147865 A CN 201410147865A CN 104979394 B CN104979394 B CN 104979394B
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Abstract
The formed method of semiconductor device provided by the invention, semiconductor device include that substrate and drain region, the source area and trap of the first conductive type are located in substrate.Trap between drain region and source area has the second conductive type, and the first conductive type is opposite with the second conductive type.This device further includes multiple doped regions in trap.Doped region horizontally with vertically mutually deviate.Each doped region includes the lower part point of the first conductive type, the upper part with the second conductive type in lower part point.The formed method of the semiconductor device provided through the invention, can be in the case where semiconductor device increases breakdown voltage, without will increase device surface product or opening resistor.
Description
Technical field
The present invention is about semiconductor device, also especially in regard to the formed side of semiconductor device with multiple doped region
Method.
Background technique
The power semiconductor arrangement of high voltage applications generallys use vertical double diffusion metal-oxide half field effect transistor
(VDMOSFET) or lateral diffusion metal-oxide half field effect transistor (LDMOSFET).In order to increase the breakdown of high-voltage semiconductor device
Voltage, the method generallyd use are as follows: reducing the doping concentration of deep trap (or drift region in the art), increase drift region
Depth or increase grid under isolation structure (or field oxide in the art) length.
Although the above method can increase the breakdown voltage of power semiconductor arrangement, also increase the size or unlatching of transistor
Resistance when state, and increase the efficiency reduction of semiconductor device or area.
In this way, need to develop semiconductor device at present to increase breakdown voltage, without will increase device surface product or open
Open resistance.
Summary of the invention
The object of the present invention is to provide a kind of formed methods of semiconductor device, increase breakdown to solve semiconductor device
Voltage, without will increase device surface product or the technical issues of opening resistor.
The technical solution of the present invention is to provide a kind of semiconductor device, comprising: substrate, have the first conductive type.This dress
Set further includes that drain region, source area and trap are located in substrate.For trap between source area and drain region, trap has the second conduction
Type, and the first conductive type is opposite with the second conductive type.This device further includes that multiple doped regions are located in trap.Doped region horizontally with
Vertically mutually deviate.Each doped region includes the lower part point of the first conductive type, second is led with what is be stacked in lower part point
The upper part of electric type.
The present invention also provides a kind of semiconductor devices, comprising: substrate has the first conductive type；And epitaxial structure, have
The first conductive type and be located at substrate on.This device further includes that drain region and source area are located in epitaxial structure；And trap, it is located at leakage
Between polar region and source area.Trap is located in substrate and epitaxial structure, and trap has the second conductive type, and the first conductive type is led with second
Electric type is opposite.This device further includes that the first doped region is located in the trap of substrate；And second doped region be located at the trap of epitaxial structure
In.First doped region and the second doped region horizontally with vertically mutually deviate.First doped region is respectively wrapped with the second doped region
Lower part containing the first conductive type point, the upper part with the second conductive type being stacked in lower part point.
The present invention provides a kind of semiconductor device again, comprising: substrate has the first conductive type；And multiple epitaxial layers, tool
There is the first conductive type and is located on substrate.This device further includes drain region and source area, in the top layer of epitaxial layer；And
Trap, between drain region and source area.Trap is located in substrate and epitaxial layer, and trap has the second conductive type, and the first conductive type
It is opposite with the second conductive type.This device further includes that multiple doped regions are located in epitaxial layer.At least two doped regions horizontally with hang down
Directly mutually deviate.Each doped region includes the lower part point of the first conductive type, with the second conduction being stacked in lower part point
The upper part of type.
The present invention provides a kind of forming method of semiconductor device again, comprising: prepares the substrate and shape of the first conductive type
At trap in substrate.Trap has the second conductive type, and the second conductive type is opposite with the first conductive type.The method further includes forming screening
Cap layer is on substrate.Mask layer includes multiple holes, and hole from mask layer surface it is downward depth it is different.The method is also wrapped
It includes after progress first is implanted through mask layer and enters trap, to form multiple first doped portions.At least two first doped portions
Horizontally with vertically mutually deviate.First doped portion has the first conductive type.The method further includes carrying out the second injection to wear
Enter trap after crossing mask layer, to form multiple second doped portions.At least two second doped portions horizontally with vertically mutually
It deviates.Second doped portion has the second conductive type and is stacked on the first doped portion.
The present invention also provides a kind of forming methods of semiconductor device, comprising: prepares the substrate of the first conductive type；And shape
At trap in substrate.Trap has the second conductive type, and the second conductive type is opposite with the first conductive type.The method further includes forming
One mask layer is on substrate.First mask layer includes the first hole.The method further includes carrying out the first injection to wear with the second injection
Enter trap after crossing the first mask layer, to form the first doped region.First doped region includes the lower part point of the first conductive type, with heap
It is laminated on the upper part of the second conductive type in lower part point.The method further includes that self-reference substrate removes the first mask layer and shape
At the second mask layer on substrate.Second mask layer includes the second hole.The method further includes carrying out the first injection and the second note
Enter and enter trap after the second mask layer, to form the second doped region, and the first doped region and the second doped region horizontally with it is vertical
Directly mutually deviate.Second doped region includes the lower part point of the first conductive type, with the second conduction being stacked in lower part point
The upper part of type.The method further includes that self-reference substrate removes the second mask layer.
The present invention provides a kind of forming method of semiconductor device again, comprising: prepares the substrate and shape of the first conductive type
At the first trap in substrate.First trap has the second conductive type, and the second conductive type is opposite with the first conductive type.The method is also wrapped
The first epitaxial layer to form the first conductive type is included on substrate；And the second trap is formed in the first epitaxial layer.Second trap has
The second conductive type.The method further includes forming the first mask layer on the first epitaxial layer.First mask layer includes the first hole.This
Method further includes carrying out entering the second trap after the first injection is implanted through the first mask layer with second, to form the first doped region.
First doped region includes the lower part point of the first conductive type, with the one of the second conductive type being stacked in lower part point compared with top
Point.The method further includes removing the first mask from the first epitaxial layer, forms the second epitaxial layer of the first conductive type in the first extension
On layer, and third trap is formed in the second epitaxial layer.Third trap has the second conductive type.First trap, the second trap and third trap
Form continuous trap.The method further includes forming the second mask layer on the second epitaxial layer.Second mask layer includes the second hole.Into
The injection of row first is implanted through after the second mask layer with second enters third trap, to form the second doped region, the first doped region with
Second doped region horizontally with vertically offset with one another.Second doped region includes a lower part point for the first conductive type, with stacking
In the upper part of the second conductive type in lower part point.The method further includes removing the second mask layer from the second epitaxial layer.
The formed method of the semiconductor device provided through the invention can increase breakdown voltage in semiconductor device
In the case of, without will increase device surface product or opening resistor.
Detailed description of the invention
Fig. 1 a and Fig. 1 b are the schemas of power semiconductor arrangement in certain embodiments of the invention.
Fig. 2 a and Fig. 2 b are the schemas of power semiconductor arrangement in certain embodiments of the invention.
Fig. 3 a and Fig. 3 b are the schemas of power semiconductor arrangement in certain embodiments of the invention.
Fig. 4 a and Fig. 4 b are the schemas of power semiconductor arrangement in certain embodiments of the invention.
Fig. 5 a to Fig. 5 e is the schema of the forming method of power semiconductor arrangement in certain embodiments of the invention.
Fig. 6 is the schema of the forming method of power semiconductor arrangement in certain embodiments of the invention.
Fig. 7 a to Fig. 7 d is the schema of the forming method of power semiconductor arrangement in certain embodiments of the invention.
Fig. 8 a to Fig. 8 c is the schema of other forming methods of power semiconductor arrangement in certain embodiments of the invention.
Fig. 9 a is the schema of another power semiconductor arrangement in certain embodiments of the invention.
Fig. 9 b is the schema of another power semiconductor arrangement in certain embodiments of the invention.
Fig. 9 c is the schema of another power semiconductor arrangement in certain embodiments of the invention.
Figure 10 is the schema of another power semiconductor arrangement in certain embodiments of the invention.
Figure 11 a to Figure 11 h is the schema of the forming method of power semiconductor arrangement in certain embodiments of the invention.
Main element symbol description
10,11,12,13 semiconductor device
102,900 substrate
104,904 trap
106,906 body region
108,908 p-type contact areas
110,910 N-shaped contact areas
111,911 source area
112,912 drain region
114,914 field insulating layer
116,916 gate structure
118,918 gate insulating layer
120,920 conductive source
122,922 conductive grid
124,924 conductive drain
126,926 interlayer dielectric layer
132,134,136,138,932,934,936 doped region
132a, 134a, 136a, 138a, 932a, 934a, 936a p-type lower part point
132b, 134b, 136b, 138b, 932b, 934b, 936b N-shaped upper part
150 sacrificial layers
152 injection protective layers
160,200,202,204 mask layer
162,173,175,177,179,181,183,185,201,203,205 hole
172,180 first mask layer
174,182 second mask layer
176,184 third mask layer
178 the 4th mask layers
90,91,92,93 power semiconductor arrangement
902,902a, 902b epitaxial layer
Specific embodiment
Following embodiment will arrange in pairs or groups, and details are as follows for schema.
Fig. 1 a is the schema of power semiconductor arrangement 10.Semiconductor device 10 is N-shaped device, and it includes p-type semiconductors
Substrate 102.Gate structure 116 and field insulating layer 114 are located on substrate 102.Gate insulating layer 118 be located at gate structure 116 with
Between substrate 102.Part of grid pole insulating layer 118 extends over part field insulating layer 114.In addition, the body region 106 of p-type and N-shaped
Trap 104 be located on 116 two sides of gate structure in substrate 102.Collectively as source area 111 p-type contact areas 108 with
Adjacent N-shaped contact areas 110 is located in body region 106, and is located in trap 104 as the N-shaped contact areas of drain region 112.
In addition, trap 104 of multiple doped regions 132,134,136 and 138 between source area 111 and drain region 112
In.Doped region 132 includes that p-type lower part divides 132a, with the N-shaped upper part for being stacked in p-type lower part and dividing on the top of 132a
132b.Similarly, doped region 134,136,138 be respectively provided with p-type lower part divide 134a, 136a and 138a and N-shaped relatively on
Part 134b, 136b and 138b.Although it is understood that being four doped regions, the doped region of some embodiments in Fig. 1 a
Number can be more or less than four.
Doped region 132,134,136, be arranged in trap 104 with 138, and at least horizontally with vertically mutually deviate.It lifts
Example for, doped region 132 and 134 horizontally with vertically separate.In addition, although doped region 134 and 136 is horizontally and vertically
It mutually deviates, N-shaped upper part 134b contact p-type lower part divides 136a.On the other hand, doped region 132,134,136 and 138
The downward depth in the surface (i.e. the interface of substrate 102 shown in Fig. 1 a and field insulation edge layer 114) of self-reference substrate 102, from source area
111 to drain region 112 direction be incremented by.
In certain embodiments, the depth of doped region 132,134,136 and 138 may depend on the field distribution wheel of trap 104
It is wide.Fig. 1 b show to be formed doped region 132,134,136, with 138 in trap 104 before, the field distribution wheel of the trap 104 of Fig. 1 a
It is wide.Based on above-mentioned electric field profile, doped region 132 is located at relatively depth in trap 104 and electric field is compared with strength, and doped region 138 is located at
The relatively close and weaker place of electric field with substrate surface.
In addition, conductive source 120 is electrically connected to p-type contact areas 108 and N-shaped contact areas 110.Conductive drain 124 is electrically connected
To drain region 112.Conductive grid 122 is electrically connected to gate structure 116.Interlayer dielectric layer 126 covers conductive source 120, conduction
Grid 122 and conductive drain 124.
The schema of the certain other embodiments of Fig. 2 a to Fig. 4 present invention, and omit the part similar with Fig. 1 a and said with simplification
It is bright.Fig. 2 b, Fig. 3 b and Fig. 4 b be respectively semiconductor device 11,12, with 13, formed doped region 132,134,136, with 138 in
Electric field profile before in trap 104.
After confirming electric field profile, doped region 132,134,136, the row with 138 can be determined according to electric field profile
Column mode.For example, the semiconductor device 11 in Fig. 2 a, doped region 132,134,136, the surface with 138 self-reference substrates 102
Downward depth, the direction from source area 111 to drain region 112 are successively decreased.Above content omits the part similar with Fig. 1 a with letter
Change explanation.
Fig. 3 a is the schema of another semiconductor device, and the doped region 134 between doped region 132 and 136 has most
Big depth, and doped region 138 is adjacent with the surface of substrate 102.The arrangement mode of above-mentioned doped region depends on electricity shown in Fig. 3 b
Field distribution profile.As best seen in figs. 3a and 3b, doped region 134 is located in trap 104 relatively depth and electric field is compared with strength, and doped region 138
Positioned at the relatively close and weaker place of electric field with substrate surface.
Fig. 4 a is the schema of another semiconductor device, and the doped region 134 between doped region 132 and 136 has most
Small depth, and the downward depth in surface of 138 self-reference substrate 102 of doped region is maximum.The arrangement mode of above-mentioned doped region depends on figure
Electric field profile shown in 4b.As shown in Fig. 4 a and Fig. 4 b, doped region 138 is located at relatively depth in trap 104 and electric field is compared with strength, and
Doped region 134 is located at and electric field weaker place relatively close with substrate surface.
It is understood that the position of doped region and depth are not limited to above-described embodiment.Furthermore, it is to be understood that doping
The position in area and depth may depend on the design parameter other than electric field profile.
Above structure can increase the breakdown voltage of power semiconductor arrangement, while reduce opening resistor.Further, since partly leading
Containing doped region 132,134,136 and 138 in body device 10,11,12 and 13, the overall dimensions of device can be reduced, therefore increase
Add the device number of unit area.
Following the description by arrange in pairs or groups schema explanatory diagram 1a semiconductor device 10 forming method.As shown in Figure 5 a, p-type is prepared
The substrate 102 of semiconductor is to be used for technique.The step of preparing substrate 102 includes cleaning or other processing, to provide appropriate surface
For subsequent technique.Substrate 102 has sacrificial layer 150 for being injected.The substrate 102 of semiconductor can for silicon substrate, absolutely
Silicon (SOI) substrate, sige substrate or other suitable semiconductor substrates in edge layer.For example, sacrificial layer 150 can be oxidation
Object, nitride or nitrogen oxides.The injection such as photoresist layer of protective layer 152 is formed on sacrificial layer 150.Protective layer 152 is injected to pass through
After patterning, can exposed portion region to be injected.Then it carries out N-shaped to be injected into substrate 102, to form trap 104.For
The N-shaped of trap 104 injects its doping concentration, higher than the doping concentration of substrate 102.For example, the doping concentration of trap 104 is 1e11
To 1e13 atom/cm2, the doping concentration of the trap 104 of one embodiment of the invention is 1e11 to 5e12 atom/cm2.It is injected in N-shaped
After substrate 102, step is as being tempered and removing sacrificial layer 150 and injection protective layer 152 after being injected.
As shown in Figure 5 b, such as hard mask of mask layer 160 is formed on substrate 102.Mask layer 160 may include oxide, nitrogen
Compound, nitrogen oxides or other organic materials.The forming method of mask layer 160 can for be physically or chemically vapor-deposited or other
Suitable coating process.Then patterning mask layer 160 is to form hole 162, and at least one of hole 162 passes through mask layer
160 and expose substrate 102 trap 104 surface.In addition, patterning some perforations 162 to form step structure.Such as Fig. 5 b
Shown, the upper surface of hole from mask layer 160 has downwards different depth.In another embodiment, with the mask of hole 162
Layer 160 can print on substrate 102.In one embodiment of this invention, thin sacrificial layer similar with the sacrificial layer 150 of Fig. 5 a,
It can be formed between mask layer 160 and substrate 102.In some embodiments, in patterning mask layer 160 to form hole 162
Before step, the electric field profile in trap can be first confirmed.After the depth of 160 Hole 162 of mask layer and position depend on confirmation
Electric field profile.
As shown in Figure 5 c, p-type is carried out to be implanted through after mask layer 160 to trap 104, to be formed simultaneously p-type lower part point
132a, 134a, 136a and 138a.To formed p-type lower part divide 132a, 134a, 136a, with the p-type Implantation Energy phase of 138a
Together.Be implanted through after mask layer 160 in addition, carrying out N-shaped to trap 104, be formed simultaneously N-shaped upper part 132b, 134b,
136b and 138b is stacked in p-type lower part respectively and divides on the top of 132a, 134a, 136a and 138a, to form doped region
132,134,136 and 138.To form N-shaped upper part 132b, 134b, 136b, identical as the N-shaped Implantation Energy of 138b.
However above-mentioned injection is not limited to particular order.In certain embodiments, it first carries out N-shaped and injects trap 104, then carry out p-type injection.
For example, to formed p-type lower part divide 132a, 134a, 136a, with its doping concentration of the p-type Implantation Energy of 138a, with
To form N-shaped upper part 132b, 134b, 136b, can be about 1e11 to 1e13 with its doping concentration of the N-shaped Implantation Energy of 138b
Atom/cm2 makes the doping concentration of doped region 132,134,136 and 138 be higher than the doping concentration of trap 104.In some embodiments
In, p-type lower part divides 132a, 134a, 136a, the doping concentration for being higher than with the p-type implantation concentration of 138a trap 104, and N-shaped relatively on
The N-shaped implantation concentration of part 132b, 134b, 136b and 138b are lower than the doping concentration of trap 104.
As fig 5d, it carries out p-type and is injected into substrate 102 to form body region 106.Although Fig. 5 d is not shown, injection
Sacrificial layer 150 and injection protective layer 152 in Fig. 5 a can be used in technique, to form body region 106.The p-type injection of body region
Doping concentration can be about 1e11 to 1e14 atom/cm2。
As fig 5d, trap 104, body region 106 and doped region 132,134,136 and 138 are being formed in substrate 102
Afterwards, field insulating layer 114 is formed on the surface of substrate 102.Field insulating layer 114 can be oxide, nitride or nitrogen oxides.
The forming method of insulating layer 114 can be oxidation and/or nitridation substrate or deposition oxide, nitride and/or nitrogen oxides material
Expect on substrate.As fig 5d, field insulating layer 114 is formed on substrate 102, and exposes substrate 102, trap 104 and body region
106 surface.
As fig 5d, gate insulating layer 118 is formed on substrate 102, with covering part field insulating layer 114, Yi Jiji
The surface of plate 102 and body region 106.For example, gate insulating layer 118 can be oxide, nitride or nitrogen oxides.This
Outside, gate structure 116 is formed on gate insulating layer 118.Gate structure 116 can for polysilicon, metal, metal silicide or
Other conductive materials.
As depicted in fig. 5e, the source area 111 comprising p-type contact areas 108 Yu adjacent N-shaped contact areas 110, and there is n
The drain region 112 of type contact areas is respectively formed in body region 106 and trap 104.The formation side of source area 111 and drain region 112
Method can be corresponding injection body region 106 and trap 104.For example, source area 111 and the doping concentration of drain region 112 can be about
1e11 to 1e16 atom/cm2, and the doping concentration of the source area 111 of other embodiments and drain region 112 can be about 1e14 extremely
1e15 atom/cm2.It forms conductive source 120 later to be electrically connected to p-type contact areas 108 and N-shaped contact areas 110, is formed conductive
Drain electrode 124 forms conductive grid 122 to be electrically connected to drain region 112 to be electrically connected to gate structure 116.Above-mentioned conductive electricity
Pole can sequentially form or be formed simultaneously.In addition, the material of above-mentioned conductive electrode can select from polysilicon, metal, metal silicide or
Other conductive materials.In certain embodiments, the material of conductive electrode can be identical as the material of gate structure.Interlayer dielectric layer
126 are deposited on substrate 102 to cover conductive electrode.Although non-schema, multiple layer inner connection line can be formed in semiconductor device 10
Substrate on.
As shown in Figure 5 c, the hole 162 in mask layer 160 can be used to be formed simultaneously p-type lower part divide 132a, 134a,
136a and 138a, or it is formed simultaneously N-shaped upper part 132b, 134b, 136b and 138b.P-type lower part divide 132a, 134a,
136a, with 138a can horizontally with vertically mutually deviate.N-shaped upper part 132b, 134b, 136b and 138b can be horizontally
With vertically mutually deviate.In certain embodiments, the hole profile in mask layer 160 can according in trap 104 doped region 132,
134,136, the arrangement mode adjustment with 138.It is illustrated with Fig. 6, another mask layer 160 has hole 162, may be used to form doping
Area 132,134,136 and 138 is in trap 104.Specifically from the maximum hole of the downward depth in the upper surface of mask layer 160
162, doped region 134 caused by the injection across this hole 162, the downward depth in the upper surface of self-reference substrate 102 is maximum.From
The smallest hole 162 of the downward depth in the upper surface of mask layer 160, doped region 138 caused by the injection across this hole 162,
It is adjacent with the upper surface of substrate 102.
Using single mask layer be formed simultaneously doped region 132,134,136, can have with 138 upper part or lower part point
There is process advantage, but the forming method of the doped region of some embodiments is not limited to the above method, and multiple mask layer can be used.
By taking Fig. 7 a as an example, after forming the substrate 102 with trap 104, the first mask layer 172 can be coated on substrate.First mask layer
172 have hole 173.P-type injection can be carried out respectively via hole 173 and is injected into trap with N-shaped, to form p-type lower part point
138a and N-shaped upper part 138b, and the two forms doped region 138.Then mask layer 172 is removed, the second mask layer is coated
174 in as shown in Figure 7b on substrate 102.
As shown in Figure 7b, the second mask layer 174 has hole 175.P-type is carried out respectively via hole 175 to be injected into N-shaped
Trap divides 136a and N-shaped upper part 136b to form p-type lower part, and the two forms doped region 136.It is worth noting that, trap
Doped region 136 in 104 is deeper than doped region 138, therefore the Implantation Energy to form doped region 136 can be higher than and form doped region
138 Implantation Energy.Then the second mask layer 174 is removed, and is coated with third mask layer 176 in as shown in Figure 7 c on substrate 102.
As shown in Figure 7 c, third mask layer 176 has hole 177.P-type is carried out respectively via hole 177 to be injected into N-shaped
Trap divides 134a and N-shaped upper part 134b to form p-type lower part, and the two forms doped region 134.Similarly, to be formed
The Implantation Energy of doped region 134 can be higher than the Implantation Energy for forming doped region 136 and 138.Then third mask layer 176 is removed,
And be coated with the 4th mask layer 178 on substrate 102 as shown in figure 7d.
As shown in figure 7d, the 4th mask layer 178 has hole 179.P-type is carried out respectively via hole 179 to be injected into N-shaped
Trap divides 132a and N-shaped upper part 132b to form p-type lower part, and the two forms doped region 132.Repeatable above-mentioned steps
Until forming all doped regions according to preassigned.
The another method of doped region is formed as shown in Fig. 8 a to Fig. 8 c using multiple mask layers.As shown in Figure 8 a, it is providing
After substrate 102 with trap 104, the first mask layer 180 is coated on substrate 102.First mask layer 180 has hole 181.Through
It carries out p-type respectively by hole 181 and N-shaped is injected into trap 104, divide 138a and N-shaped upper part 138b to form p-type lower part,
And the two forms doped region 138.Then the first mask layer 180 is removed, and is coated with the second mask layer 182 in such as figure on substrate 102
Shown in 8b.
As shown in Figure 8 b, the second mask layer 182 has two circular cavities 183.P-type, which is carried out, via hole 183 is injected into trap
104, divide 136a and 132a to form p-type lower part, then carry out N-shaped via hole 183 and be injected into trap 104, with formed N-shaped relatively on
Part 136b and 132b.In this way, which single mask layer, which can be used, forms two doped regions 132 and 136.It is worth noting that,
Doped region 132 and 136 in trap 104 is deeper than doped region 138, therefore the Implantation Energy to form doped region 132 and 136 can be high
In the Implantation Energy for forming doped region 138.Then the second mask layer 182 is removed, and is coated with third mask layer 184 in substrate 102
It is upper as shown in Figure 8 c.
As shown in Figure 8 c, third mask layer 184 has hole 185.P-type is carried out respectively via hole 185 to be injected into N-shaped
Trap 104 divides 134a and N-shaped upper part 134b to form p-type lower part, and the two forms doped region 134.Similarly, to
The Implantation Energy for forming doped region 134 can be higher than the Implantation Energy for forming doped region 132,136 and 138.
Some embodiments are identical as the embodiment of Fig. 1 to Fig. 4, and the forming method of above-mentioned semiconductor device can optionally include
Other steps, for example, confirmation trap in electric field profile, then according to electric field profile determine mask layer in hole location with
Depth.
Although above-mentioned power semiconductor arrangement is N-shaped, the power semiconductor arrangement of other embodiments can be p-type.P-type power
The structure of semiconductor device can be similar with the structure of aforementioned N-shaped power semiconductor arrangement, and difference is p-type power semiconductor arrangement
In materials conductive type it is opposite with the materials conductive type in N-shaped power semiconductor arrangement.
Fig. 9 a is the schema of another power semiconductor arrangement 90 in the embodiment of the present invention.Power semiconductor arrangement 90 is n
Type device, the substrate 900 with p-type, with the epitaxial layer 902 being located on substrate 900.Gate structure 916 and field insulating layer 914
On epitaxial layer 902.Gate insulating layer 918 is between gate structure 916 and epitaxial layer 902.Part of grid pole insulating layer 918
Extend over part field insulating layer 914.
In addition, the body region 906 of p-type is located in epitaxial layer 902.The trap 904 of N-shaped is located at substrate 900 and epitaxial layer 902
In.P-type contact areas 908 and adjacent N-shaped contact areas 910 form source area 911, are located in body region 906.N-shaped contact areas
The drain region 912 of composition is located in the trap 904 in epitaxial layer 902.Doped region 932 is located in the trap 904 of substrate 900.Doped region
932 divide 932a comprising p-type lower part, with the N-shaped upper part 932b for being stacked in p-type lower part and dividing on the top 932a.In addition, mixing
Miscellaneous area 934 is located in the trap 904 of epitaxial layer 902.Doped region 934 includes that p-type lower part divides 934a, and is stacked in p-type lower part
Divide the N-shaped upper part 934b on the top 934a.Doped region 932 and 934 is between source area 911 and drain region 912.It can be with
Understand, although a doped region is located in substrate 900 in Fig. 9 a, and another doped region is located in epitaxial layer 902, the present invention
An embodiment substrate 900 and epitaxial layer 902 can respectively contain multiple doped regions.As shown in figure 9b, power semiconductor arrangement
91 epitaxial layer 902 includes two doped regions 934 and 936 being separated.
In addition, conductive source 920 is electrically connected to p-type contact areas 908 and N-shaped contact areas 910.Conductive drain 924 electrically connects
It is connected to the drain region 912 of N-shaped contact areas composition.Conductive grid 922 is electrically connected to gate structure 916.Interlayer dielectric layer 926 covers
Lid conductive source 920, conductive grid 922 and conductive drain 924.
Doped region 932 and 934 in trap 904 at least horizontally with vertically offset with one another.In fig. 9 a, doped region 932
With 934 horizontally with vertically offset with one another.However in one embodiment of the invention, although doped region 932 and 934 horizontally with
It vertically offsets from, but the power semiconductor arrangement 91 that doped region 932 and 934 can partially overlap as is shown in fig. 9 c.
In certain embodiments, multiple epitaxial layers can be formed on the substrate 900 in power semiconductor arrangement.Each extension
Layer can have a trap and an at least doped region.As shown in Figure 10, power semiconductor arrangement 93 is N-shaped device, and the base containing p-type
Two epitaxial layer 902a and 902b (assembly epitaxial layer 902) on plate 900, with substrate 900.Gate structure 916 and field insulating layer
914 are located on epitaxial layer 902b.Gate insulating layer 917 is between gate structure 916 and epitaxial layer 902b.Part of grid pole insulation
Layer 918 extends over part field insulating layer 914.Although power semiconductor arrangement 92 has two layers of epitaxial layer, the number of epitaxial layer
Mesh is not limited to this and can be more than two.
As shown in Figure 10, the body region 906 of p-type is located in epitaxial layer 902b.The trap 904 of N-type is located at substrate 900 and extension
In layer 902a and 902b, therefore above-mentioned trap forms continuous trap.The source that p-type contact areas 908 and adjacent N-shaped contact areas 910 form
Polar region 911 is located in body region 906.The drain region 912 of N-shaped contact areas composition is located in the trap 904 in epitaxial layer 902b.Doping
Area 932 is located in the trap 904 of substrate 900.Doped region 932 includes that p-type lower part divides 932a, is divided with p-type lower part is stacked in
N-shaped upper part 932b on the top of 932a.In addition, doped region 934 and 936 is located at the trap of epitaxial layer 902a and 902b
In 904.Doped region 934 includes that p-type lower part divides 934a, divides the N-shaped on the top of 934a compared with top with p-type lower part is stacked in
Divide 934b.Doped region 936 include p-type lower part divide 936a, be stacked in p-type lower part divide the N-shaped on the top of 936a relatively on
Part 936b.Doped region 932,934 and 936 is between source area 911 and drain region 912.Although it is understood that figure
Doped region in 10 is each located in substrate 900 and epitaxial layer 902a and 902b, but the substrate 900 of one embodiment of the invention with
Epitaxial layer 902a and 902b may include multiple doped regions.In addition, the epitaxial layer of Figure 10 can be omitted in one embodiment of the invention
The doped region 934 of 902a or the doped region 932 of substrate 900.
In addition, conductive source 920 is electrically connected to p-type contact 908 and N-shaped contact 910.Conductive drain 924 is electrically connected to N-shaped
The drain region 912 of contact composition.Conductive grid 922 is electrically connected to gate structure 916.Interlayer dielectric layer 926 covers conductive source
920, conductive grid 922 and conductive drain 924.
Doped region 932 in trap 904,934, with 936 at least horizontally with vertically mutually deviate.It must be noted that
The trap 904 or doped region 932 in the substrate 900 of Figure 10 can be omitted.
Following the description by arrange in pairs or groups schema explanatory diagram 10 in power semiconductor arrangement 92 forming method.As shown in fig. 11a,
The substrate 902 of p-type semiconductor is prepared to be used for subsequent technique.Substrate 900 has sacrificial layer 150 to be injected.Semiconductor
Substrate 900 can be silicon (SOI) substrate, sige substrate or other suitable semiconductor substrates on silicon substrate, insulating layer.Citing comes
It says, sacrificial layer 150 can be oxide, nitride or nitrogen oxides.Injection protective layer 152 such as photoresist layer is located at sacrificial layer 150
On.After injection protective layer 152 is patterned, expose the region that injection carries out.Then it carries out N-shaped and is injected into substrate 900 to be formed
Trap 904.The doping concentration that N-shaped for trap 904 injects is higher than the doping concentration of substrate 900, for example is about 1e11 to 1e13 original
Son/cm2.The doping concentration of N-shaped injection in one embodiment of the invention is about 1e11 to 5e12 atom/cm2Between.It is infused in N-shaped
Enter to substrate 900, it can the removal sacrificial layer 150 of self-reference substrate 900 and injection protective layer 152.
As shown in figure 11b, such as hard mask of mask layer 200 is formed on substrate 900.Mask layer 200 may include oxide, nitrogen
Compound, nitrogen oxides or other organic materials.The forming method of mask layer 200 can for be physically or chemically vapor-deposited or other
Suitable coating process.Then mask layer 200 is patterned, hole 201 is formed and passes through mask layer 200 to expose the trap 904 of substrate 900
Surface.In another embodiment, the mask layer 200 with multiple holes 201 can print on substrate 900.In certain implementations
In example, the thin sacrificial layer similar with the sacrificial layer 150 in Figure 11 a can be formed between mask layer 200 and substrate 900.
As shown in figure 11b, p-type is carried out via hole 201 and be injected into trap 904, divide 932a to form p-type lower part.In addition,
N-shaped is carried out via hole 201 and is injected into trap 904, and the N-shaped lower part that p-type lower part is divided on 932a is stacked in formation and divides 932b,
Form doped region 932.However above-mentioned injection sequence is not limited to particular order.In certain embodiments, N-shaped injection is first carried out
To trap, then carries out p-type and be injected into trap.For the doping concentration that p-type lower part divides the p-type of 932a to inject, or for N-shaped compared with top
The doping concentration of the N-shaped injection of point 932b (for example is 1e11 to 1e13 atom/cm2), it is higher than the doping concentration of doped region 932
The doping concentration of trap 904.In certain embodiments, the doping that p-type lower part divides the p-type doping concentration of 932a to be higher than trap 904 is dense
Degree, and the n-type doping concentration of N-shaped upper part 932b is lower than the doping concentration of trap 904.
As shown in fig. 11c, the epitaxial layer 902 for p-type of growing up is on substrate 900.The material that epitaxial layer 902a includes can be with base
Plate 900 is identical or different.Sacrificial layer 150 and sacrificial layer 150 and injection 152 class of protective layer in injection protective layer 152 and Figure 11 a
Seemingly, it is used for injection epitaxial layer 902a.N-shaped, which is injected into epitaxial layer 902a, can form trap 904 in wherein.N for trap 904
The doping concentration of type injection is higher than the doping concentration of epitaxial layer 902a.For example, the doping for the N-shaped injection of trap 904 is dense
Degree is about 1e11 to 1e13 atom/cm2, it is about 1e11 to 5e12 atom/cm in one embodiment of the invention2.It is injected into N-shaped
After epitaxial layer 902a, sacrificial layer 150 and injection protective layer 152 are removed from epitaxial layer 902a.
As illustrated in fig. 11d, another mask layer 202 such as hard mask is formed on epitaxial layer 902a.Pattern mask layer 202 with
Form the surface that hole 203 passes through mask layer 202 and exposes the trap 904 of epitaxial layer 902a.In another embodiment, there is hole
203 mask layer 202 can print on epitaxial layer 902a.In certain embodiments, similar with the sacrificial layer 150 of Figure 11 a thin
Sacrificial layer can be formed between mask layer 202 and epitaxial layer 902a.
As illustrated in fig. 11d, the trap 904 of p-type injection and N-shaped implantation to epitaxial layer 902a is carried out respectively via mask layer 202,
Divide 934a to form p-type lower part, divides the N-shaped upper part 934b on 934a with p-type lower part is located at, that is, form doped region
934.For example, the doping concentration for dividing the p-type of 934a to inject to form p-type lower part, or to form N-shaped upper part
The doping concentration of the N-shaped injection of 934b is about 1e11 to 1e13 atom/cm2, therefore the doping concentration in doped region 934 is higher than outer
Prolong the doping concentration of the trap 904 of layer 902a.In certain embodiments, p-type lower part divides the p-type doping concentration of 934a to be higher than trap
904 doping concentration, and the n-type doping concentration of N-shaped upper part 934b is lower than the doping concentration of trap 904.
As illustrated in fig. 11e, the epitaxial layer 902b for p-type of growing up is on epitaxial layer 902a.With the sacrificial layer 150 and note of Figure 11 a
Enter protective layer 152 to be used to inject similar to sacrificial layer 150 and injection protective layer 152, be formed on epitaxial layer 902b.N-shaped is injected into
Epitaxial layer 902b is to form trap 904 in wherein.The doping concentration that N-shaped for trap 904 injects is higher than the doping of epitaxial layer 902a
Concentration.The doping concentration that N-shaped for trap 904 injects is about 1e11 to 1e13 atom/cm2, it is about 1e11 in some embodiments
To 5e12 atom/cm2.After N-shaped is injected into epitaxial layer 902b, sacrificial layer 150 and injection protective layer are removed from epitaxial layer 902b
152。
As shown in figure 11f, such as hard mask of mask layer 204 is formed on epitaxial layer 902b.Mask layer 204 is patterned to be formed
Hole 205 passes through mask layer 204 and exposes the upper surface of the trap 904 of epitaxial layer 902b.In another embodiment, there is hole
205 mask layer 204 can print on epitaxial layer 902b.In certain embodiments, similar with the sacrificial layer 150 of Figure 11 a thin
Sacrificial layer can be formed between mask layer 204 and epitaxial layer 902b.
As shown in figure 11f, the trap 904 that p-type injection is injected into epitaxial layer 902b with N-shaped is carried out respectively via mask layer 204,
Divide 936a to form p-type lower part, divides the N-shaped upper part 936b on 936a with p-type lower part, that is, form doped region 936.It lifts
For example, the N-shaped for the doping concentration that p-type lower part divides the p-type of 936a to inject, or for N-shaped upper part 936b injects
Doping concentration be about 1e11 to 1e13 atom/cm2, therefore the doping concentration of doped region 936 is higher than the trap 904 of epitaxial layer 902b
Doping concentration.In certain embodiments, the doping concentration that p-type lower part divides the p-type doping concentration of 936a to be higher than trap 904, and n
The n-type doping concentration of type upper part 936b is lower than the doping concentration of trap 904.
As shown in Figure 11 g, carries out p-type and be injected into epitaxial layer 902b to form body region 906.Although Figure 11 g is not shown,
The sacrificial layer 150 and injection protective layer 152 similar with Figure 11 a may be used to form body region 906.For example, it is used for body region
P-type injection doping concentration be about 1e11 to 1e14 atom/cm2。
As shown in Figure 11 g, after forming trap 904, body region 906 and doped region 932,934 and 936, insulating layer is formed
914 on the surface of epitaxial layer 902b.Insulating layer 914 can be oxide, nitride or nitrogen oxides.The formation of insulating layer 914
Method can be oxidation and/or nitridation epitaxial layer 902b or deposition oxide, nitride and/or nitrogen oxides in epitaxial layer 902b
On.As shown in Figure 11 g, insulating layer 914 is formed on epitaxial layer 902b, and exposes trap 904, body region 906 and and body region
The surface of 906 adjacent epitaxial layer 902b.
As shown in Figure 11 g, gate insulating layer 918 is formed on epitaxial layer 902b with covering part insulating layer 914, with extension
The surface of layer 902b and body region 906.For example, gate insulating layer 918 can be oxide, nitride or nitrogen oxides.This
Outside, gate structure 916 is formed on gate insulating layer 918.Gate structure 916 can for polysilicon, metal, metal silication or its
His conductive material.
As shown in Figure 11 h, the source area 911 comprising p-type contact areas 908 Yu adjacent 910 source area of N-shaped contact areas, with
And drain region 912 is respectively formed in body region 906 and trap 904.The forming method of source area 911 and drain region 912 can be note
Enter corresponding admixture into body region 906 and trap 904.For example, the doping concentration of source area 911 and drain region 912 is about
1e11 to 1e16 atom/cm2.It in one embodiment of this invention, can be 1e13 for the doping concentration of source area and drain region
To 1e16 atom/cm2, and the doping concentration in other embodiments can be 1e14 to 1e16 atom/cm2.It is subsequently formed conductive source
920 are electrically connected to p-type contact areas 908 and N-shaped contact areas 910.Conductive drain 924 is electrically connected to the drain electrode of N-shaped contact areas composition
Area 912.Conductive grid 922 is electrically connected to gate structure 916.These conductive electrodes can be sequentially formed or are formed simultaneously.In addition, this
The material of a little electrodes can be selected from polysilicon, metal, metal silicide or other conductive materials.In certain embodiments, electrode material
Material can be identical with the material of gate structure.Interlayer dielectric layer 926 is deposited on epitaxial layer 902b to cover above-mentioned electrode.Although not
Diagram, but multiple layer inner connection line can be formed on the electrode of power semiconductor arrangement.
Although power semiconductor arrangement of the Fig. 9 into Figure 11 is N-shaped, the power semiconductor arrangement of other embodiments can be p
Type.The structure of p-type power semiconductor arrangement can be similar with the structure of aforementioned N-shaped power semiconductor arrangement, and difference is p-type power
Materials conductive type in semiconductor device is opposite with the materials conductive type in N-shaped power semiconductor arrangement.
The embodiment of the present invention can be adjusted, therefore above-described embodiment is only to illustrate rather than limits to the present invention.
Claims (45)
1. a kind of semiconductor device characterized by comprising
One substrate has a first conductive type；
One drain region, source region are located in the substrate with a trap, which is located between the source area and the drain region, the trap
With a second conductive type, and the first conductive type is opposite with the second conductive type；And
Multiple doped regions are located in the trap, the doped region horizontally with do not overlap completely vertically, each doped region packet
The lower part point for including the first conductive type, the upper part with the second conductive type being stacked in the lower part point.
2. semiconductor device as described in claim 1, which is characterized in that the downward depth in the surface of the doped region from the substrate
Degree, by the direction increasing or decreasing of the source area to the drain region.
3. semiconductor device as described in claim 1, which is characterized in that the doped region between two doped regions,
With the depth capacity that the surface from the substrate is downward.
4. semiconductor device as described in claim 1, which is characterized in that the doped region between two doped regions,
With the minimum-depth that the surface from the substrate is downward.
5. semiconductor device as described in claim 1, which is characterized in that the trap doped with one first doping concentration, this relatively under
Part is doped with one second doping concentration, and the upper part is doped with a third doping concentration；And
Second doping concentration and the third doping concentration are above first doping concentration.
6. semiconductor device as described in claim 1, which is characterized in that
The trap is doped with one first doping concentration, and the lower part point is doped with one second doping concentration, and the upper part is adulterated
There is a third doping concentration；
And second doping concentration is higher than first doping concentration, and first doping concentration is higher than the third doping concentration.
7. semiconductor device as claimed in claim 5, which is characterized in that first doping concentration is 1e11 atom/cm2Extremely
1e13 atom/cm2。
8. semiconductor device as claimed in claim 6, which is characterized in that first doping concentration is 1e11 atom/cm2Extremely
1e13 atom/cm2。
9. a kind of semiconductor device characterized by comprising
One substrate has a first conductive type；
One epitaxial structure has the first conductive type and is located on the substrate；
One drain region and source region are located in the epitaxial structure；
One trap, between the drain region and the source area, which is located in the substrate and the epitaxial structure, which has one the
Two conductivity types, and the first conductive type is opposite with the second conductive type；
One first doped region, in the trap of the substrate；And
One second doped region, in the trap of the epitaxial structure,
Wherein first doped region and second doped region horizontally with do not overlap completely vertically；And
Wherein first doped region and second doped region respectively contain a lower part point for the first conductive type, and are stacked in this
One upper part of the second conductive type in lower part point.
10. semiconductor device as claimed in claim 9, which is characterized in that the epitaxial structure is made of multiple epitaxial layers, and should
Second doped region is located in the top layer of the epitaxial layer.
11. semiconductor device as claimed in claim 10, which is characterized in that each epitaxial layer includes at least one doping
Area, and the doped region vertically with horizontally mutually deviate.
12. semiconductor device as claimed in claim 9, which is characterized in that the doped region between two doped regions,
With the depth capacity that the surface from the substrate is downward.
13. semiconductor device as claimed in claim 9, which is characterized in that the doped region between two doped regions,
With the minimum-depth that the surface from the substrate is downward.
14. semiconductor device as claimed in claim 9, which is characterized in that
The trap is doped with one first doping concentration, and the lower part point is doped with one second doping concentration, and the upper part is adulterated
There is a third doping concentration；And
Second doping concentration and the third doping concentration are above first doping concentration.
15. semiconductor device as claimed in claim 9, which is characterized in that
The trap is doped with one first doping concentration, and the lower part point is doped with one second doping concentration, and the upper part is adulterated
There is a third doping concentration；And
Second doping concentration is higher than first doping concentration, and first doping concentration is higher than the third doping concentration.
16. semiconductor device as claimed in claim 14, which is characterized in that first doping concentration is 1e11 atom/cm2Extremely
1e13 atom/cm2。
17. semiconductor device as claimed in claim 15, which is characterized in that first doping concentration is 1e11 atom/cm2Extremely
1e13 atom/cm2。
18. a kind of semiconductor device characterized by comprising
One substrate has a first conductive type；
Multiple epitaxial layers have the first conductive type and are located on the substrate；
One drain region and source region, in the top layer of the epitaxial layer；
One trap, between the drain region and the source area, which is located in the substrate and the epitaxial layer, which has one the
Two conductivity types, and the first conductive type is opposite with the second conductive type；And
Multiple doped regions, be located at the epitaxial layer in, and at least two doped regions horizontally with do not overlap completely vertically；
Wherein each doped region includes a lower part point for the first conductive type, be stacked in the lower part point this
One upper part of two conductivity types.
19. semiconductor device as claimed in claim 18, which is characterized in that each epitaxial layer has a doped region, and
The doped region horizontally with vertically mutually deviate.
20. semiconductor device as claimed in claim 18, which is characterized in that at least one epitaxial layer includes multiple doping
Area, and the doped region of at least one epitaxial layer is horizontally mutually mutually separated, and has phase at least one epitaxial layer
Same vertical height.
21. semiconductor device as claimed in claim 18, which is characterized in that
The trap is doped with one first doping concentration, and the lower part point is doped with one second doping concentration, and the upper part is adulterated
There is a third doping concentration；And
Second doping concentration and the third doping concentration are above first doping concentration.
22. semiconductor device as claimed in claim 18, which is characterized in that
The trap is doped with one first doping concentration, and the lower part point is doped with one second doping concentration, and the upper part is adulterated
There is a third doping concentration；And
Second doping concentration is higher than first doping concentration, and first doping concentration is higher than the third doping concentration.
23. semiconductor device as claimed in claim 21, which is characterized in that first doping concentration is 1e11 atom/cm2Extremely
1e13 atom/cm2。
24. semiconductor device as claimed in claim 22, which is characterized in that first doping concentration is 1e11 atom/cm2Extremely
1e13 atom/cm2。
25. a kind of forming method of semiconductor device characterized by comprising
Prepare a substrate of a first conductive type；
A trap is formed in the substrate, which has a second conductive type, and the second conductive type is opposite with the first conductive type；
A mask layer is formed on the substrate, which includes multiple holes, and described hole from the surface of the mask layer to
Under depth it is different；And
One first is carried out to be implanted through after the mask layer into the trap, to form multiple first doped portions, described at least two
First doped portion horizontally with do not overlap completely vertically, and first doped portion have the first conductive type；And
One second is carried out to be implanted through after the mask layer into the trap, to form multiple second doped portions, described at least two
Second doped portion horizontally with do not overlap completely vertically, and second doped portion has and the second conductive type and stacks
In on first doped portion.
26. the forming method of semiconductor device as claimed in claim 25, which is characterized in that the step of forming mask layer packet
It includes:
A material layer is coated on the substrate；And
The material layer is patterned, one of described hole is made to pass through the material layer.
27. the forming method of semiconductor device as claimed in claim 25, which is characterized in that first doped portion or institute
The second doped portion is stated to be formed simultaneously.
28. the forming method of semiconductor device as claimed in claim 25, which is characterized in that first doped portion or institute
The forming method of the second doped portion is stated using fixed Implantation Energy.
29. the forming method of semiconductor device as claimed in claim 25, which is characterized in that further include:
Confirm the electric field profile in the trap；And
The depth of described hole is determined according to the electric field profile.
30. the forming method of semiconductor device as claimed in claim 25, which is characterized in that further include:
The trap is adulterated, makes the trap that there is one first doping concentration；
First doped portion is adulterated, makes first doped portion that there is one second doping concentration；And
Second doped portion is adulterated, makes second doped portion that there is a third doping concentration,
Wherein second doping concentration and the third doping concentration are higher than first doping concentration.
31. the forming method of semiconductor device as claimed in claim 25, which is characterized in that further include:
The trap is adulterated, makes the trap that there is one first doping concentration；
First doped portion is adulterated, makes first doped portion that there is one second doping concentration；And
Second doped portion is adulterated, makes second doped portion that there is a third doping concentration,
Wherein second doping concentration is higher than first doping concentration, and first doping concentration is higher than the third doping concentration.
32. a kind of forming method of semiconductor device characterized by comprising
Prepare a substrate of a first conductive type；
A trap is formed in the substrate, which has a second conductive type, and the second conductive type is opposite with the first conductive type；
One first mask layer is formed on the substrate, and first mask layer includes one first hole；
It carries out entering the trap after one first injection is implanted through first mask layer with one second, to form one first doped region,
First doped region includes a lower part point for the first conductive type, with the second conductive type that is stacked in the lower part point
One upper part；
First mask layer is removed from the substrate；
One second mask layer is formed on the substrate, and second mask layer includes one second hole；
First injection is carried out second to be implanted through after second mask layer with this and enter the trap, to form one second doped region,
First doped region and second doped region horizontally with do not overlap completely vertically, wherein second doped region include this first
One lower part of conductivity type point, the upper part with the second conductive type being stacked in the lower part point；And
Second mask layer is removed from the substrate.
33. the forming method of semiconductor device as claimed in claim 32, which is characterized in that first mask layer or this second
Mask layer has multiple holes.
34. the forming method of semiconductor device as claimed in claim 32, which is characterized in that form first doped region
This first injection energy, different to formed second doped region this first injection energy.
35. the forming method of semiconductor device as claimed in claim 32, which is characterized in that further include:
Confirm the electric field profile in the trap；And
The position of first hole and second hole is determined according to the electric field profile.
36. the forming method of semiconductor device as claimed in claim 32, which is characterized in that further include:
A body region of the first conductive type is formed in the substrate；
An insulating layer is formed on the trap；
A gate insulating layer is formed, which is connected to the insulating layer and the covering part body region；
A grid is formed on the insulating layer and the gate insulating layer；
A drain region is formed in the trap；And
Source region is formed in the body region, and the drain region and the source area be located at the insulating layer it is not ipsilateral on.
37. the forming method of semiconductor device as claimed in claim 32, which is characterized in that further include:
The trap is adulterated, makes the trap that there is one first doping concentration；
The lower part point for adulterating first doped region makes the lower part point of first doped region have one second doping concentration；With
And
The upper part for adulterating first doped region makes the upper part of first doped region have a third doping concentration,
The lower part point for adulterating second doped region makes the lower part point of second doped region have one the 4th doping concentration；With
And
The upper part for adulterating second doped region makes the upper part of second doped region have one the 5th doping concentration,
Wherein second doping concentration, the third doping concentration, the 4th doping concentration and the 5th doping concentration are above this
First doping concentration.
38. the forming method of semiconductor device as claimed in claim 32, which is characterized in that further include:
The trap is adulterated, makes the trap that there is one first doping concentration；
The lower part point for adulterating first doped region makes the lower part point of first doped region have one second doping concentration；With
And
The upper part for adulterating first doped region makes the upper part of first doped region have a third doping concentration,
The lower part point for adulterating second doped region makes the lower part point of second doped region have one the 4th doping concentration；With
And
The upper part for adulterating second doped region makes the upper part of second doped region have one the 5th doping concentration,
Wherein second doping concentration and the 4th doping concentration are higher than first doping concentration, and first doping concentration is higher than
The third doping concentration and the 5th doping concentration.
39. a kind of forming method of semiconductor device characterized by comprising
Prepare a substrate of a first conductive type；
One first trap is formed in the substrate, which has a second conductive type, and the second conductive type first is led with this
Electric type is opposite；
One first epitaxial layer of the first conductive type is formed on the substrate；
One second trap is formed in first epitaxial layer, and second trap has the second conductive type；
One first mask layer is formed on first epitaxial layer, and first mask layer includes one first hole；
It carries out entering second trap after one first injection is implanted through first mask layer with one second, to form one first doping
Area, first doped region include a lower part point for the first conductive type, with second conduction being stacked in the lower part point
One upper part of type；
First mask layer is removed from first epitaxial layer；
One second epitaxial layer of the first conductive type is formed on first epitaxial layer；
A third trap is formed in second epitaxial layer, the third trap have the second conductive type, and first trap, this second
Trap forms a continuous trap with the third trap；
One second mask layer is formed on second epitaxial layer, and second mask layer includes one second hole；
It carries out first injection second to be implanted through after second mask layer with this and enter the third trap, to form one second doping
Area, first doped region and second doped region horizontally with do not overlap completely vertically, second doped region include this first
One lower part of conductivity type point, the upper part with the second conductive type being stacked in the lower part point；And
Second mask layer is removed from second epitaxial layer.
40. the forming method of semiconductor device as claimed in claim 39, which is characterized in that first mask layer or this second
Mask layer includes multiple holes.
41. the forming method of semiconductor device as claimed in claim 39, which is characterized in that form first doped region and be somebody's turn to do
The Implantation Energy of second doped region is identical.
42. the forming method of semiconductor device as claimed in claim 39, which is characterized in that further include:
Confirm the electric field profile in second trap and the third trap；And
The position of first hole and second hole is determined according to the electric field profile.
43. the forming method of semiconductor device as claimed in claim 39, which is characterized in that further include:
A body region of the first conductive type is formed in second epitaxial layer；
An insulating layer is formed on the third trap；
A gate insulating layer is formed, which is connected to the insulating layer and the covering part body region；
A grid is formed on the insulating layer and the gate insulating layer；
A drain region is formed in the third trap；And
Source region is formed in the body region, and the drain region and the source area be located at the insulating layer it is not ipsilateral on.
44. the forming method of semiconductor device as claimed in claim 39, which is characterized in that further include:
Second trap is adulterated, makes second trap that there is one first doping concentration；
The lower part point for adulterating first doped region makes the lower part point of first doped region have one second doping concentration；With
And
The upper part for adulterating first doped region makes the upper part of first doped region have a third doping concentration,
The lower part point for adulterating second doped region makes the lower part point of second doped region have one the 4th doping concentration；With
And
The upper part for adulterating second doped region makes the upper part of second doped region have one the 5th doping concentration,
Wherein second doping concentration, the third doping concentration, the 4th doping concentration and the 5th doping concentration are above this
First doping concentration.
45. the forming method of semiconductor device as claimed in claim 39, which is characterized in that further include:
Second trap is adulterated, makes second trap that there is one first doping concentration；
The lower part point for adulterating first doped region makes the lower part point of first doped region have one second doping concentration；With
And
The upper part for adulterating first doped region makes the upper part of first doped region have a third doping concentration,
The lower part point for adulterating second doped region makes the lower part point of second doped region have one the 4th doping concentration；With
And
The upper part for adulterating second doped region makes the upper part of second doped region have one the 5th doping concentration,
Wherein second doping concentration and the 4th doping concentration are higher than first doping concentration, and first doping concentration is higher than
The third doping concentration and the 5th doping concentration.
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