CN104952729A - Manufacturing method for finned field effect transistor - Google Patents
Manufacturing method for finned field effect transistor Download PDFInfo
- Publication number
- CN104952729A CN104952729A CN201410111464.XA CN201410111464A CN104952729A CN 104952729 A CN104952729 A CN 104952729A CN 201410111464 A CN201410111464 A CN 201410111464A CN 104952729 A CN104952729 A CN 104952729A
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- China
- Prior art keywords
- opening
- present
- inside wall
- field effect
- effect transistor
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000005669 field effect Effects 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 23
- 239000003989 dielectric material Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a manufacturing method for a finned field effect transistor. The manufacturing method comprises the following steps: providing a substrate on which fins, a gate dielectric layer and a pseudo-gate electrode are formed; removing the pseudo-gate electrode to form an opening; forming an inner side wall on the inner wall of the opening; filling the opening to form an alternative gate. The method is applied to an undergate manufacturing process for the finned field effect transistor, after the pseudo-gate electrode is removed, the inner side wall is formed on the inner wall of the opening, and a small gate length is obtained in case of the same physical gate length, thus reducing requirements on photoetching.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of manufacture method of fin formula field effect transistor.
Background technology
Along with the height of semiconductor device is integrated, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more remarkable, even become the leading factor affecting device performance, this phenomenon is referred to as short-channel effect.The electric property of short-channel effect meeting deterioration of device, as caused, threshold voltage of the grid declines, power consumption increases and degradation problem under signal to noise ratio.
In order to solve the problem of short-channel effect, propose the three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-FET is the transistor with fin channel structure, it utilizes several surfaces of thin fin as raceway groove, can operating current be increased, thus the short-channel effect in conventional transistor can be prevented.
Along with the continuous reduction of device size, the requirement of photoetching is also improved constantly.And in rear grid technique, dummy grid needs enough thickness, CMP(cmp during to avoid follow-up formation alternative gate) the overground loss causing grid high, and the high increase that can cause parasitic capacitance of lower grid, but, along with the continuous reduction of grid size, blocked up pseudo-grid can cause alternative gate to fill the problem of difficulty.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of manufacture method of fin formula field effect transistor is provided.
For achieving the above object, technical scheme of the present invention is:
A manufacture method for fin formula field effect transistor, is characterized in that, comprising:
Substrate is provided, described substrate is formed with fin and gate dielectric layer, dummy grid;
Remove dummy grid, to form opening;
The inwall of described opening forms inside wall;
Fill described opening to form alternative gate.
Alternatively, form alternative gate after formation inside wall before, also step is comprised: remove pseudo-gate dielectric layer and again formed.
Alternatively, described inside wall is silica or silicon nitride.
Alternatively, the width of described inside wall is 1-20nm.
Optionally, the width of described inside wall is 5-10nm.
The manufacture method of fin formula field effect transistor of the present invention, is applied in rear grid manufacturing process, after the pseudo-grid of removal, the inwall of opening forms inside wall, when identical physical gate is long, obtains less grid long, reduces the requirement to photoetching.Meanwhile, when the long grid of identical grid are high, be more conducive to the filling of alternative gate, and larger process window can be provided for subsequent CMP process, and then avoid, due to the excessive problem of the high too low parasitic capacitance caused of grid, improving the performance of device.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the invention process, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 shows the flow chart of the manufacture method of fin formula field effect transistor of the present invention;
Fig. 2-Fig. 7 is the schematic cross-section along fin direction manufacturing fin formula field effect transistor according to the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
In order to understand the present invention better, the schematic diagram below with reference to flow chart and the embodiment of the present invention is described in detail manufacture method of the present invention.All schematic cross-sections are all the schematic cross-sections along fin direction below.
First, provide substrate, shown in figure 2.
In the present embodiment, described substrate is SOI substrate 200, and SOI substrate 200 comprises 200-1 at the bottom of backing, oxygen buried layer 200-2 and top layer silicon (scheming not shown).In other embodiments, described substrate can also be other substrat structures comprising semiconductor layer.
Then, in described substrate 200, fin 210 is formed.
In the present embodiment, particularly, cap layers (scheming not shown) can be formed in top layer silicon, then graphical described cap layers, and be hard mask with cap layers, utilize lithographic technique, such as RIE(reactive ion etching) method, etching top layer silicon, thus forms fin 210 in top layer silicon, then, hard mask is removed further.In other embodiments, this cap layers can be retained.
Then, described fin 210 forms gate dielectric layer 220 and dummy grid 230, as shown in Figure 2.
Particularly, form gate dielectric material, pseudo-gate dielectric material and hard mask material first respectively, gate dielectric layer can be thermal oxide layer or high K medium material etc., can be silicon dioxide in the present embodiment, can be formed by the method for thermal oxidation.Described dummy grid can be amorphous silicon, polysilicon etc., in the present embodiment, is amorphous silicon.Then, form the hard mask 240 of patterning, under the covering of hard mask 240, continue etching, form the gate dielectric layer 220 and the dummy grid 230 that stride across fin.
Then, form side wall 2250 at the sidewall of described dummy grid, and cover substrate to form interlayer dielectric layer 260, as shown in Figure 3.
Described side wall can have single or multiple lift structure, can by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low k dielectric material and combination thereof, and/or other suitable materials are formed.
Can by suitable deposition process deposit dielectric material, such as unadulterated silica (SiO
2), doping silica (as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si
3n
4) or other low k dielectric materials, then carry out planarization, such as CMP(chemico-mechanical polishing), until expose dummy grid, form described interlayer dielectric layer (ILD) 260, as shown in Figure 3.
Then, dummy grid 230 is removed, as shown in Figure 4.
Dummy grid can use wet etching to remove, and in the present embodiment, removes amorphous silicon by Tetramethylammonium hydroxide (TMAH), thus, form opening 242 in the region of original dummy grid, as shown in Figure 4.
Then, the inwall of opening forms inside wall 280, as shown in Figure 6.
Particularly, first deposits dielectric materials 270, as shown in Figure 5, usually can be oxide or nitride, be silicon nitride in the present embodiment, then, etch, such as carry out RIE(reactive ion etching), only on the inwall of opening, retain dielectric material, namely on the inwall of opening, form inside wall 280, as shown in Figure 6, the width of described inside wall can be 1-20nm, and more preferably, the width of this inside wall is 5-10nm.
In common grid etch technique, it is basic the same or top narrow lower portion is wide that the pattern of the grid of formation is generally upper and lower width, and this pattern is unfavorable for filling after formation of the opening.In the present invention by forming inside wall on the inwall of opening, normally top narrow lower portion is wide for the pattern of side wall, the pattern of opening is made to change into wide bottom, top narrow, be conducive to the filling of alternative gate like this, and larger process window can be provided for subsequent CMP process, and then avoid, due to the excessive problem of the high too low parasitic capacitance caused of grid, improving the performance of device.
Then, the gate dielectric layer 220 exposed is removed, as shown in Figure 7.
In the present embodiment, the gate dielectric layer of silicon dioxide can be removed by the HF of dilution, like this, just define the opening that width is less, to form the long alternative gate of less grid in subsequent step.
Then, fill described opening and form alternative gate dielectric layer and alternative gate (scheming not shown).
Alternative gate dielectric layer can be high K medium material (such as, compare with silica, have the material of high-k) or other suitable dielectric materials, and high K medium material is hafnium base oxide such as, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc.
Described alternative gate can be metal-gate structures, can be one or more layers structure, such as Ti, TiAlx, TiN, TaN
x, HfN, TiC
x, TaC
xor polysilicon or their combination.
Then, as required, for further processing to above-mentioned device, such as form contact, interconnection structure etc.
To the semiconductor device which form method constructed in accordance.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (5)
1. a manufacture method for fin formula field effect transistor, is characterized in that, comprising:
Substrate is provided, described substrate is formed with fin and gate dielectric layer, dummy grid;
Remove dummy grid, to form opening;
The inwall of described opening forms inside wall;
Fill described opening to form alternative gate.
2. manufacture method according to claim 1, is characterized in that, before forming alternative gate, also comprises step: remove the gate dielectric layer exposed, and again forms alternative gate dielectric layer after formation inside wall.
3. manufacture method according to claim 1, is characterized in that, described inside wall is silica or silicon nitride.
4. manufacture method according to claim 1, is characterized in that, the width of described inside wall is 1-20nm.
5. manufacture method according to claim 1, is characterized in that, the width of described inside wall is 5-10nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410111464.XA CN104952729A (en) | 2014-03-24 | 2014-03-24 | Manufacturing method for finned field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410111464.XA CN104952729A (en) | 2014-03-24 | 2014-03-24 | Manufacturing method for finned field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104952729A true CN104952729A (en) | 2015-09-30 |
Family
ID=54167300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410111464.XA Pending CN104952729A (en) | 2014-03-24 | 2014-03-24 | Manufacturing method for finned field effect transistor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348385B1 (en) * | 2000-11-30 | 2002-02-19 | Chartered Semiconductor Manufacturing Ltd. | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant |
| US6673683B1 (en) * | 2002-11-07 | 2004-01-06 | Taiwan Semiconductor Manufacturing Co., Ltd | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions |
| WO2006087381A1 (en) * | 2005-02-18 | 2006-08-24 | Infineon Technologies Ag | Trench-gate electrode for finfet device |
| CN103177951A (en) * | 2011-12-22 | 2013-06-26 | 台湾积体电路制造股份有限公司 | Gate structure for semiconductor device |
-
2014
- 2014-03-24 CN CN201410111464.XA patent/CN104952729A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348385B1 (en) * | 2000-11-30 | 2002-02-19 | Chartered Semiconductor Manufacturing Ltd. | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant |
| US6673683B1 (en) * | 2002-11-07 | 2004-01-06 | Taiwan Semiconductor Manufacturing Co., Ltd | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions |
| WO2006087381A1 (en) * | 2005-02-18 | 2006-08-24 | Infineon Technologies Ag | Trench-gate electrode for finfet device |
| CN103177951A (en) * | 2011-12-22 | 2013-06-26 | 台湾积体电路制造股份有限公司 | Gate structure for semiconductor device |
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Application publication date: 20150930 |
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