CN104952421B - A kind of method and system for generating the MIPI signals for being used for the detection of MIPI modules - Google Patents
A kind of method and system for generating the MIPI signals for being used for the detection of MIPI modules Download PDFInfo
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Abstract
The invention discloses a kind of method and system for the MIPI signals for generating and being used for the detection of MIPI modules, rgb image data is obtained by link vision signal, then obtaining MIPI signals by rgb image data specifically includes following steps：Before rgb signal is converted into MIPI signals, the rgb image data being converted into by vision signal is cached；Local RGB image pixel clock is obtained further according to the image time sequence parameter needed for MIPI module displays；According to described image time sequence parameter, under RGB image pixel clock, stable local image sequential is produced, forms the picture synchronization signal for meeting MIPI module testing requirements；Under picture synchronization signal control, the rgb image data of caching is subjected to MIPI conversions, obtain the MIPI signals for meeting MIPI module testing requirements, it can realize there is that easy to implement, cost is relatively low, easy to operate, working stability, reliability are high, easy to operate in a piece of fpga chip provided by the present invention for the MIPI signal generating systems of MIPI modules detection.
Description
Technical field
The invention belongs to signal processing technology field, is used for the detection of MIPI modules more particularly, to a kind of generate
The method and system of MIPI signals.
Background technology
Mobile industry processor interface (Mobile Industry Processor Interface, MIPI) Display Technique
And MIPI liquid crystal display die sets have been widely used in various portable mobile products；In grinding for MIPI liquid crystal display die sets
, it is necessary to carry out multinomial test to the MIPI liquid crystal display die sets of output in hair and production process.
In the prior art, the original test image of different resolution is produced using independent image signal source more, and is passed through
Cable is connected to MIPI conversion equipments, by low-voltage differential signal (Low-Voltage Differential Signaling,
LVDS) signal is converted into MIPI signals, to test the module of different qualities；Since image signal source is of low quality, precision
It is poor with stability, and production environment electromagnetic interference is larger, connection cables are longer to cause signal distortion and decay so that converted
The MIPI jitters of generation, are there is the problems such as flicker, offset, snow or bright line on the picture of module displays；Due to
It is unstable in the MIPI signal sources of test, therefore, when the picture that MIPI liquid crystal display die sets are shown occurs abnormal, it can not judge
It is due to the extremely caused exception of signal source, is also due to abnormal caused by the failure of MIPI liquid crystal display die sets, causes pair
The test accuracy of MIPI liquid crystal display die sets is not high.
The content of the invention
For the disadvantages described above or Improvement requirement of the prior art, it is used for MIPI modules the present invention provides one kind generation and detects
MIPI signals method and system, its object is to the timing information in locally-regenerated MIPI modules, according to the data of reception
Rgb video signal locally is being regenerated, and is carrying out MIPI conversions, stable MIPI signals is being formed, solves prior art point
The problem of MIPI screens are unstable, display flicker, bright line, snow.
To achieve the above object, one side according to the invention, there is provided a kind of generate is used for the detection of MIPI modules
The method of MIPI signals, comprises the following steps：
(1) recovery shaping is carried out to vision signal, electrical characteristic is transmitted to adjust it；The vision signal includes link transmission
Clock and link serially-transmitted data；
(2) link transmission clock and link serially-transmitted data are calibrated, is eliminated between clock and data-signal
Relative delay so that transmission data and clock alignment；
The LVDS signals of each link are demodulated respectively according to transmission clock, carry out serioparallel exchange, serially-transmitted data warp
Serioparallel exchange operates, and is demodulated to parallel video data；
(3) according to LVDS transmit VESA (Video Electronics Standards Association) agreement,
JEIDA (Japan Electronic Industry Development Association) agreements and 6bit, 8bit, 10bit
Color range is decoded, and each link signal is reduced into RGB image；And combine the RGB image of each link, formed complete
Rgb image data, RGB synchronizing signals, rgb pixel clock；
(4) the image time sequence parameter according to needed for MIPI module displays, the MIPI that rgb signal is converted into whole screen form scheme
The image of picture or split screen form,
(5) the MIPI images to whole screen form or the image of split screen form carry out MIPI signal conversions, are changed into difference
The MIPI signals of the number of channel.
Especially point is for it, and before rgb signal is converted into MIPI signals, the rgb image data received is cached；Again
Image time sequence parameter according to needed for MIPI module displays obtains local RGB image pixel clock；Then, joined according to image sequential
Number, under RGB image pixel clock, produces stable local image sequential, is consequently formed and meets MIPI module testing requirements
Picture synchronization signal；Under picture synchronization signal control, the rgb image data of caching is subjected to MIPI conversions,
Obtain the MIPI signals for meeting MIPI module testing requirements；
Due to RGB image signal may be subject in transmitting procedure external disturbance, transmission cable delay it is asynchronous, with
And the more low influence of image signal source stability itself, cause the rgb image data that local reception is arrived to there are shake, timing variations
Or delay is larger；If by local reception to rgb image data be directly changed into MIPI signals and be sent into module, shown on module
The image shown is likely to occur the problems such as film flicker, picture moving, fuzzy pictures；And the RGB image number that the present invention will receive
Locally-regenerated according to being cached to, then reconvert, eliminates the shake and delay of view data, realizes that sequential is alignd, there is provided be used for
The MIPI signal qualities of MIPI modules detection；
Wherein, image time sequence parameter includes：Row crop, row back porch, row are effective, row pulsewidth, frame crop, frame back porch, frame have
Effect, frame pulsewidth and display brush frequency；
Wherein, RGB image pixel clock is local clock, has clock frequency stabilization, reliably and from external disturbance
Advantage.
Preferably, when rgb image data starts caching, whether current RGB image frame is judged according to local image sequential
For complete frame, if so, then current RGB image frame is stored in since first data of the first row in caching；If it is not, then abandon
Current RGB image frame, receives new RGB image frame；The new RGB image frame is stored in since first data of the first row
In caching；
And whether have data deposit caching according to local image time-series rules when each RGB image frame starts, when having
When data are stored in, the RGB image number in starting to take out caching when first pixel sequential of the first row of RGB image frame arrives
According to；Since deposit data are synchronous with reading data so that the rgb image data of output is the view data of stable localization.
Preferably, the method calibrated in above-mentioned steps (2) to link transmission clock, link serially-transmitted data, tool
Body is as follows：Using the clock of 4~8 times of frequency domain signal transfer rates come data detection signal and the edge transition of clock signal, obtain
The time delay of data-signal and clock signal, and reversely delay does data-signal and clock signal according to time delay and adjusts, so that when
It is synchronous each other between clock and each data-signal；
Then first bit of parallel byte is obtained, with alignment transmission clock and data, will be gone here and there according to transmission clock
Row transmission data are operated through serioparallel exchange, are demodulated to parallel data；
Wherein, reversely delay adjustment is by controlling High Speed I/O Delay Elements, adjusting the signal of clock and each link
Delay, makes synchronous between clock and each data-signal；Reversely delay adjustment action, solves because vision signal is in transmitting procedure
Since the clock that is received caused by length of cable, material, transmission characteristic volume difference, opposite between each data-signal are prolonged
Late.
Preferably, before the rgb signal locally produced is converted into the conversion of MIPI signals, according to MIPI signal transfer rates,
Frequency dividing frequency multiplication operation is carried out to RGB image pixel clock, obtains synchronous MIPI change over clock, MIPI is changed according to above-mentioned MIPI
Change over clock carries out；
Wherein, MIPI change over clock includes the byte group packet clock of MIPI operations and the string signal clock of output MIPI.
Preferably, after the step of rgb signal changes MIPI signals, further include and school is carried out to the MIPI signals got
Accurate step；
MIPI signals include the MIPI clock signals of stringization and each channel MIPI data-signals；Calibrate MIPI clock signals
And the phase between each Channel Data Signal so that MIPI signals when being output to the connector of MIPI modules, clock and
The center alignment of each Channel Data Signal, meets MIPI DPHY agreements；So as to ensure that the MIPI signals that MIPI modules receive are steady
It is fixed errorless；The clock because of MIPI signal sources, data are avoided to show bright line caused by not aliging, dodge the problems such as line；Wherein,
MIPI DPHY agreements are one of MIPI agreements, and D-PHY is provided to DSI (series display interface) and CSI (serial cameras
Interface) definition on a physical layer.
Preferably, between MIPI signal output parts and MIPI module receiving terminals, using controlled delay component adjustment output
MIPI signals clock signal and data-signal between mutual delay so that the edge of MIPI clock signals is in data-signal
The centre of UI is transmitted, keeps fully synchronized between each MIPI data-signals.
Preferably, after the step of rgb signal changes MIPI signals, the transmission in MIPI signal transmissions to MIPI modules
During, further include compensation of delay and signal fine setting；
Specifically, compensation of delay is by comparing the first original circuit not being delayed and the circuit of delay, obtaining relative time delay value,
The circuit of delay is repaid according to the relative time delay value complement using the Reverse Turning Control component that is delayed, adaptive adjustment because operating temperature,
Delay time error caused by environmental change；
Signal fine setting includes high speed (high speed, the HS) state to MIPI signals and low-power consumption (low power, LP)
The electrical characteristic of state is configured, including level magnitude, drives intensity, preemphasis, rising edge trailing edge, differential signal zero
Value adjusts so that the clock and data-signal of the received MIPI signals of MIPI modules are fully synchronized.
To achieve the object of the present invention, examined it is another aspect of this invention to provide that providing a kind of generation and being used for MIPI modules
The system of the MIPI signals of survey, including MIPI control modules, video data cache module, local RGB generation modules, local video
Clock generation module, local RGB synchronizing signals generation module and MIPI modular converters；
Wherein, control signal interface of the input terminal of MIPI control modules as the system, for receiving exterior arrangement；
The input terminal of video data cache module is used to receive the rgb image data being converted into through LVDS signals；
Wherein, the first input end of local RGB generation modules connects the output terminal of the video data cache module；Second
Input terminal connects the output terminal of the local RGB synchronizing signal generation modules；3rd input terminal connects the local video clock
First output terminal of generation module, receives RGB image clock；
Wherein, the first input end of local video clock generation module connects the 4th output of the MIPI control modules
End, receives MIPI changeover control signals；Second input terminal connects the 3rd output terminal of MIPI control modules, receives MIPI module figures
As sequential；
Wherein, the first input end of local RGB synchronizing signals generation module also connects the 3rd output of MIPI control modules
End, receives MIPI module image sequential；Second input terminal also connects the first output terminal of local video clock generation module, receives
RGB image clock；
Wherein, the output terminal of the first input end connection local RGB generation modules of MIPI modular converters, receives by caching
Regenerated local rgb signal afterwards；Second input terminal connects the second output terminal of local video clock generation module, receives MIPI and turns
Change clock；3rd input terminal connects the 4th output terminal of MIPI control modules, receives MIPI changeover control signals；
Wherein, video data cache module is used to cache the rgb image data received；Local video clock generation module is used
According to configuration generation image pixel clock；Image pixel clock is at the local that local video clock generation module produces
Clock, clock frequency is steady, from external disturbance；
Wherein, local RGB synchronizing signals generation module is used to generate local image sequential；Local RGB generation modules according to
The rgb image data of the local image sequential and video data cache module caching, in locally-regenerated rgb signal；MIPI
Modular converter meets the MIPI signals of MIPI module displays demands according to the generation of local rgb signal.
Preferably, above-mentioned generation is used for the system of the MIPI signals of MIPI modules detection, further includes LVDS signals and schemes to RGB
As the converting unit of data, the LVDS interface of the input terminal of the unit as system, for connecting LVDS signal sources, receives each chain
Transmission clock signal and transmission data-signal on road；Output terminal is as rgb image data delivery outlet, for connecting the video
Data cache module；
The unit is used to adjust LVDS signal transmission electrical characteristics, and the clock and data of LVDS signals are calibrated,
And demodulate the LVDS signals of each link respectively, serioparallel exchange is carried out, RGB image number is converted into after being demodulated to parallel data
According to.
Preferably, above-mentioned generation is used for the system of the MIPI signals of MIPI modules detection, its LVDS signal to RGB image number
Include video input module, transmission demodulation module, transmission clock data calibration module and video conversion module according to converting unit；
Wherein, clock interface of the first input end of video input module as system, for receiving the biography on each link
Defeated clock signal, data-interface of second input terminal as system, for receiving the transmission data-signal on each link；3rd is defeated
Enter the first output terminal of end connection MIPI control modules, receive video input control signal；
Wherein, the first output terminal of the first input end connection video input module of demodulation module is transmitted, receives link passes
Defeated clock；Second input terminal connects the second output terminal of video input module, receives link transmission data；3rd input terminal connects
The output terminal of the transmission clock data calibration module；The input terminal of first output terminal connection transmission clock data calibration module；
Wherein, the second output terminal of the first input end connection transmission demodulation module of video conversion module, when receiving image
Clock；3rd output terminal of the second input terminal connection transmission demodulation module, receives view data；The connection MIPI controls of 3rd input terminal
Second output terminal of module, receives Video Quality Metric control signal；Output terminal is as LVDS signals to rgb image data converting unit
Delivery outlet；
Wherein, video input module docks received LVDS signals and carries out recovery shaping, adjusts it and transmits electrical characteristic；It is logical
Cross it is described transmission clock data calibration module link transmission clock and link serially-transmitted data are calibrated, eliminate clock with
Relative delay between data-signal so that transmission data and clock alignment；The transmission demodulation module will according to transmission clock
The LVDS signals of each link demodulate respectively, carry out serioparallel exchange, are demodulated to parallel data；The video conversion module is according to institute
Parallel data is stated, obtains rgb image data.
Preferably, above-mentioned generation is used for the system of the MIPI signals of MIPI modules detection, further includes MIPI clock datas school
Quasi-mode block and MIPI output modules；
Wherein, the first output terminal of MIPI modular converters is stated in the first input end connection of MIPI clock datas calibration module,
Receive MIPI clock signals；Second input terminal connects the second output terminal of MIPI modular converters, receives MIPI data-signals；3rd
Input terminal connects the 5th output terminal of MIPI control modules, receives MIPI transmission delays adjustment signal；
Wherein, the first output terminal of the first input end connection MIPI clock data calibration modules of MIPI output modules, connects
Receive MIPI output clocks；Second input terminal connects the second output terminal of MIPI clock data calibration modules, receives MIPI output numbers
According to；3rd input terminal connects the 6th output terminal of MIPI control modules, receives MIPI output control signals；The MIPI exports mould
The output terminal of block, as the output interface of system, for connecting MIPI modules to be measured；
MIPI clock datas calibration module is used to calibrate the phase between MIPI clocks and each Channel Data Signal so that
It can ensure that clock and each data-signal can accomplish clock and each number of channel according to MIPI DPHY agreements when being output to connector
It is believed that number center alignment；MIPI output modules are then used to carry out electricity to the MIPI signals of MIPI clock datas calibration module output
Gas characteristic, transmission characteristic and impedance operator adjustment, so that module, which terminates received MIPI signals, has optimum signal quality.
Said system can use fpga chip realize, have it is easy to implement, cost is low, work stability and reliability is high, behaviour
Make the characteristics of easy.
In general, by the contemplated above technical scheme of the present invention compared with prior art, it can obtain down and show
Beneficial effect：
(1) due to picture signal may be subject in transmitting procedure external disturbance, transmission cable delay it is asynchronous, with
And the more low reason of image signal source stability itself, can cause the view data that receives shake or image timing variations or
Postpone larger；By regeneration method after first cache image signal source provided by the invention, avoid by received picture signal
When source is directly changed into MIPI signals and is sent into module displays, there are film flicker, picture moving, fuzzy pictures etc. in display image
The problem of display cannot be stablized；
(2) MIPI signal creating methods provided by the invention and system, input adjustment is carried out to link video transfer signal
And calibration so that data receiver is correct, avoids demodulation mistake；
(3) MIPI signal creating methods provided by the invention and system, by locally regenerating the sequential of MIPI modules
Information, is re-converted into reliable and stable rgb video signal by the link video data of input, then carries out MIPI conversions again；
So that output MIPI signaling points screen is stablized, non-jitter, flicker free, without snow.
(4) MIPI signal creating methods provided by the invention and system, after MIPI is converted, adjustment output MIPI letters
Number delay, electrical characteristic, it is ensured that the transmitting of MIPI signals.
Brief description of the drawings
Fig. 1 is the block diagram of the system for the MIPI signals that a kind of generation provided by embodiment 1 is used for the detection of MIPI modules；
Fig. 2 is the flow chart of the method for the MIPI signals that generation provided by the invention is used for the detection of MIPI modules；
In all of the figs, identical reference numeral is used for representing identical element or structure：
1-MIPI control modules, 2- video input modules, 3- transmit demodulation module, 4- transmits clock data calibration module,
5- video conversion modules, 6- video datas cache module, 7- locals RGB generation modules, 8- local video clocks generation module, 9-
Local RGB synchronizing signals generation module, 10-MIPI modular converters, 11-MIPI clock datas calibration module, 12-MIPI output moulds
Block.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, it is right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Not forming conflict each other can be mutually combined.
As shown in Figure 1, a kind of generation that embodiment 1 provides is used for the system of the MIPI signals of MIPI modules detection, including
MIPI control modules 1, video input module 2, transmission demodulation module 3, transmission clock data calibration module 4, video conversion module
5th, video data cache module 6, local RGB generation modules 7, local video clock generation module 8, the production of local RGB synchronizing signals
Raw module 9, MIPI modular converters 10, MIPI clock datas calibration module 11 and MIPI output modules 12；
Wherein, video input module 2, transmission demodulation module 3, video conversion module 5, video data cache module 6, local
RGB generation modules 7, MIPI modular converters 10, MIPI clock datas calibration module 11 and MIPI output modules 12 are sequentially connected in series；
And transmit demodulation module 3 and be also connected with transmission clock data calibration module 4；Video input module, video conversion module
5th, local video clock generation module 9, local RGB synchronizing signals generation module 8, MIPI modular converters 10, MIPI clock datas
Calibration module 11 and MIPI output modules 12 are connected with MIPI control modules 1, and each module receives respectively controls mould from MIPI
All kinds of control signals of block 1；
And local RGB generation modules 7 are also connected with local RGB synchronizing signals generation module 9；Local RGB synchronizing signals production
Raw module 9 and MIPI modular converters 19 are also connected with local video clock generation module 8.
It is the flow chart for the method that the generation that embodiment 1 provides is used for the MIPI signals of MIPI modules detection shown in Fig. 2；
A kind of 1 generation provided is used for the converting system of the MIPI signals of MIPI modules detection with reference to embodiments, is specifically described this
A kind of generation that invention provides is used for the process of the MIPI signals of MIPI modules detection：
(1) according to MIPI module displays parameter requirements configure video input control parameter, including transmission termination matching properties,
Transmission termination equalization characteristic, transmission signal decision level, transmission signal benchmark, Video Quality Metric parameter, MIPI module displays images
Sequential, MIPI conversion parameters and MIPI output parameters；
Wherein, Video Quality Metric parameter includes transmission decoding process, view data bit wide, chain way；MIPI modules are shown
Diagram includes row, the pulsewidth of field, crop, back porch and virtual value as sequential；MIPI conversion parameters include MIPI transmission time sequences, MIPI
Transmission rate, the MIPI numbers of channel and MIPI operating modes；MIPI output parameters include output preemphasis, output voltage values, output
Drive intensity and output termination impedance；
(2) above-mentioned parameter is configured to each module by MIPI control modules 1：It is defeated that video input control parameter is configured to video
Enter module 2, Video Quality Metric parameter configuration to video conversion module 5, it is synchronous that MIPI module displays image sequential is configured to local RGB
Signal generator module 9 and local video clock generation module 8, MIPI conversion parameters are configured to local video clock generation module 8
With MIPI modular converters 10, MIPI output parameters are configured to MIPI output modules 12；Start video input module 2 to receive from figure
As the video transfer signal of signal source；
(3) video input module 2 is according to the configurations of MIPI control modules 1, to input transmission termination matching, input uniform,
The characteristic of transmission signal decision level is adjusted, and is received video transfer signal with accurate, stable, is avoided vision signal from existing
It is subject to the electromagnetic interference in the external world and vision signal to transmit caused distortion and decay at a distance via cable during transmission；
The transmission signal benchmark configured according to MIPI control modules 1, docks received signal and is recovered and shaping, with up to
To best transmission electrical characteristic so that subsequent module can receive data, the signal electrically correctly stablized；
(4) transmit demodulation module 3 and link transmission clock, link serially-transmitted data are sent into transmission clock data calibrating die
Block 4 is calibrated；Vision signal is in transmission, because of each length of cable, material, the difference of transmission characteristic, cause to receive clock,
There is relative delay between each data-signal, calibrate to eliminate the delay；Transmission clock data calibration module 4 passes through 4~8 times
Edge of the detection clock ratio to each signal of clock is frequency domain transmitted, and the time delayed difference value of each signal is fed back into transmission demodulation
Module 3；Transmission demodulation module 3 does each signal according to time delayed difference value reversely delay adjustment, it is kept synchronous input；
4 alignment of controlling transmission demodulation module 3 transmission clock of clock data calibration module and data are transmitted, that is, find out parallel word
The bit0 of section, transmits demodulation module 3 and operates serially-transmitted data through serioparallel exchange further according to transmission clock, to be demodulated to afterwards
Parallel data exports；
Transmission clock data calibration module 4 has the function of to monitor in real time, once monitor delay or serioparallel exchange is inclined
Difference, then controlling transmission demodulation module 3 readjusts demodulation operation, so that can reliably produce data under various circumstances；With
The drift that transmission line postpones and inside modules circuit devcie occurs can be caused by compensating extraneous interference or high/low temperature change；
(5) video conversion module 5 according to the Video Quality Metric parameter that MIPI control modules 1 configure by the data conversion of input into
Rgb image data is sent into video data cache module 6；
(6) view data is cached in video data cache module 6, the configuration further according to MIPI control modules 1 generates
Image sequential needed for MIPI module displays, including row crop, row back porch, row are effective, row pulsewidth；Frame crop, frame back porch, frame have
Effect, frame pulsewidth and display brush frequency；Image sequential of the module 8 according to needed for the MIPI module displays received from MIPI control modules 1
Acquisition of information image pixel clock frequency, and produce image pixel clock and be sent into local RGB synchronizing signals generation module 9 and local
RGB generation modules 7；Due to image pixel clock be local video clock generation module 8 produce local clock, therefore with when
Clock frequency can stablize, is reliable, is unchanged, from external disturbance the advantages of；
Due to picture signal may be subject in transmitting procedure external disturbance, transmission cable delay it is asynchronous and
The more low reason of image signal source stability itself, the view data shake that can cause to receive or image timing variations are prolonged
Larger late, if be so directly changed into MIPI signals and be sent into module displays, film flicker, picture occurs in display image
Movement, fuzzy pictures etc. cannot stablize the problem of display；This step is slowly deposited and regenerated to view data, then is steady in order to obtain
Fixed MIPI signals；
(7) local RGB synchronizing signals generation module 9 is produced according to image time sequence parameter, and RGB image pixel clock
Stable local image sequential, thus form the new picture synchronization signal for meeting MIPI displays and requiring, including field synchronization letter
Number VSYNC, line synchronising signal HSYNC and valid data gating signal DE；And above-mentioned picture synchronization signal is sent into module 7；Mould
The view data cached into is then coupled to the synchronizing signal under the control of above-mentioned picture synchronization signal and is output to together by block 7
Module MIPI modular converters 10 carry out MIPI conversions so that what view data can be reliable and stable meets the requirement of MIPI module displays；
(8) the MIPI signal transfer rates that MIPI control modules 1 are configured upper strata are sent into local video clock generation module
8, module 8 proceeds through frequency dividing and frequency multiplication to image pixel clock, produces synchronous MIPI change over clock and is sent into MIPI moduluss of conversion
Block 10 is to carry out MIPI conversion operations；In 10 transfer process of MIPI modular converters, MIPI control modules 1 are changed by MIPI to be controlled
Signal processed carries out it MIPI sequential, transmission, group bag, data channel assignment manipulation；
Wherein, MIPI change over clock includes the byte group packet clock of MIPI operations and the string signal clock of output MIPI；
(9) MIPI modular converters 10 give transformed MIPI signals to MIPI clock datas calibration module 11；Module 11
Then calibrate the phase between MIPI clocks and each Channel Data Signal so that can ensure clock and respectively when being output to connector
A data-signal can accomplish the center alignment of clock and each Channel Data Signal according to MIPI DPHY agreements, so that MIPI modules
Correct data is received to show；Avoid showing bright line caused by clock, data are not alignd, dodge the problems such as line；Wherein, turn
MIPI signals after changing include the MIPI clock signals of stringization and each MIPI data channel signals；
In transmitting procedure, the compensation of 10 one side adjust automatically of MIPI modular converters is led because of operating temperature, environmental change
The delay time error of cause；On the other hand, according to the transmission characteristic of connection cables, transmission delay is produced by MIPI control modules 1 and is believed
Number module MIPI clock datas calibration module 11 is finely adjusted, so that it is guaranteed that in the perfectly aligned of module end MIPI signals；
(10) MIPI output modules 12 by the output control signal of MIPI control modules 1 to from MIPI clock datas school
The MIPI signals of quasi-mode block 11 carry out electrical characteristic, transmission characteristic and impedance operator adjustment, so that module termination is received
MIPI signals have optimum signal quality, are then output to MIPI modules to be measured.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of method for generating the MIPI signals for being used for the detection of MIPI modules, RGB image number is obtained by link vision signal
According to according to rgb image data acquisition MIPI signals；
It is characterized in that, before MIPI signals are obtained by rgb image data, the RGB being converted into by link vision signal is schemed
As data buffer storage；And the image time sequence parameter according to needed for MIPI module displays obtains local RGB image pixel clock；
According to described image time sequence parameter, local image sequential is produced under RGB image pixel clock, formation meets MIPI modules
The picture synchronization signal of testing requirements；Under the control of described image synchronizing signal, the rgb image data of caching is subjected to MIPI and is turned
Change, obtain the MIPI signals for meeting MIPI module testing requirements；
According to MIPI signal transfer rates, frequency dividing process of frequency multiplication is carried out to the local RGB image pixel clock, is obtained synchronous
MIPI change over clock；It is described that the transfer process of MIPI signals is obtained using the MIPI change over clock as reference by rgb image data
Clock.
2. the method as described in claim 1, it is characterised in that when rgb image data starts caching, during according to local image
Sequence judges whether current RGB image frame is complete frame, if so, then opening current RGB image frame from first data of the first row
Begin to be stored in caching；If it is not, then abandoning current RGB image frame, new RGB image frame is received；By the new RGB image frame from
First data of the first row start in deposit caching；
And whether have data deposit caching according to local image time-series rules when each RGB image frame starts, when there is data
During deposit, the rgb image data in starting to take out caching when first pixel sequential of the first row of RGB image frame arrives；By
It is synchronous with reading data in deposit data so that the rgb image data of output is the view data of stable localization.
3. method as claimed in claim 1 or 2, it is characterised in that link vision signal be converted into rgb image data it
Before, first the link transmission clock to link vision signal, link serially-transmitted data are calibrated, specific as follows：
(1) obtained using the clock of 4~8 times of frequency domain signal transfer rates come data detection signal and the edge transition of clock signal
The time delay of data-signal and clock signal, and reversely delay does data-signal and clock signal according to the time delay and adjusts, with
Make to keep synchronous between clock and each data-signal；
(2) first bit of parallel byte is obtained, with alignment transmission clock and data；
(3) serially-transmitted data is operated through serioparallel exchange according to transmission clock, is demodulated to parallel data；The reversely delay is adjusted
The whole relative delay for eliminating link vision signal in transmitting procedure.
4. such as claims 1 to 3 any one of them method, it is characterised in that by rgb signal be converted into MIPI signals it
Afterwards, the step of being calibrated to the MIPI signals got is further included, is specially：
Calibrate the phase between MIPI clock signals and each channel MIPI data-signals so that the MIPI that MIPI modules receive
The center alignment of the clock of signal and each Channel Data Signal, matches with MIPI DPHY agreements.
5. method as claimed in claim 4, it is characterised in that between MIPI signal output parts and MIPI module receiving terminals,
Using the mutual delay between the clock signal and data-signal of the MIPI signals of controlled delay component adjustment output so that MIPI
The edge of clock signal keeps fully synchronized between the centre of data signal transmission UI, each MIPI data-signals.
6. method as claimed in claim 5, it is characterised in that in MIPI signals transmissions, by comparing what is be not delayed
First original circuit and the circuit of delay, obtain relative time delay value, and component is delayed according to the relative time delay value complement using Reverse Turning Control
Repay the circuit of delay, adaptive adjustment delay time error caused by operating temperature, environmental change.
7. a kind of system for generating the MIPI signals for being used for the detection of MIPI modules, it is characterised in that including MIPI control modules, regard
Frequency data cache module, local RGB generation modules, local video clock generation module, local RGB synchronizing signals generation module and
MIPI modular converters；
Control signal interface of the input terminal of the MIPI control modules as the system, for receiving exterior arrangement；It is described
The input terminal of video data cache module is used to receive the rgb image data being converted into through LVDS signals；
The first input end of the local RGB generation modules connects the output terminal of the video data cache module；Second input
End connects the output terminal of the local RGB synchronizing signal generation modules；3rd input terminal connects the local video clock and produces
First output terminal of module, receives RGB image clock；
The first input end of the local video clock generation module connects the 4th output terminal of the MIPI control modules, receives
MIPI changeover control signals；Second input terminal connects the 3rd output terminal of MIPI control modules, receives MIPI module image sequential；
The first input end of the local RGB synchronizing signal generation modules also connects the 3rd output terminal of MIPI control modules, connects
Receive MIPI module image sequential；Second input terminal also connects the first output terminal of local video clock generation module, receives RGB figures
As clock；
The output terminal of the first input end connection local RGB generation modules of the MIPI modular converters, receives after caching again
Raw local rgb signal；Second input terminal connects the second output terminal of the local video clock generation module, receives MIPI and turns
Change clock；3rd input terminal connects the 4th output terminal of MIPI control modules, receives MIPI changeover control signals；
The video data cache module is used to cache the rgb image data received；The local video clock generation module is used
According to configuration generation image pixel clock；Described image pixel clock is in the local that local video clock generation module produces
Clock, clock frequency is steady, from external disturbance；
The local RGB synchronizing signals generation module is used to generate local image sequential；The local RGB generation modules are according to institute
The rgb image data of local image sequential and video data cache module caching is stated, in locally-regenerated rgb signal；It is described
MIPI modular converters generate MIPI signals according to local rgb signal.
8. the system that generation as claimed in claim 7 is used for the MIPI signals of MIPI modules detection, it is characterised in that further include
LVDS signals are to the converting unit of rgb image data, the input terminal conduct of the LVDS signals to rgb image data converting unit
The LVDS interface of the system, for connecting LVDS signal sources, receives transmission clock signal and transmission data letter on each link
Number；Output terminal is as rgb image data delivery outlet, for connecting the video data cache module；
The LVDS signals to rgb image data converting unit, for adjusting LVDS signal transmission electrical characteristics, and to LVDS
The clock and data of signal are calibrated, and the LVDS signals of each link are demodulated respectively, are carried out serioparallel exchange, are demodulated to simultaneously
Rgb image data is converted into after row data.
9. the system that generation as claimed in claim 8 is used for the MIPI signals of MIPI modules detection, it is characterised in that described
The converting unit of LVDS signals to rgb image data includes video input module, transmission demodulation module, transmission clock data calibration
Module and video conversion module；
Clock interface of the first input end of the video input module as the system, for receiving the transmission on each link
Clock signal, data-interface of second input terminal as the system, for receiving the transmission data-signal on each link；3rd
Input terminal connects the first output terminal of MIPI control modules, receives video input control signal；
First output terminal of the first input end connection video input module of the transmission demodulation module, when receives link is transmitted
Clock；Second input terminal connects the second output terminal of video input module, receives link transmission data；Described in the connection of 3rd input terminal
Transmit the output terminal of clock data calibration module；The input terminal of first output terminal connection transmission clock data calibration module；
Second output terminal of the first input end connection transmission demodulation module of the video conversion module, receives image clock；The
3rd output terminal of two input terminals connection transmission demodulation module, receives view data；3rd input terminal connects the MIPI controls
Second output terminal of module, receives Video Quality Metric control signal；Output terminal is as LVDS signals to rgb image data converting unit
Delivery outlet；
The video input module docks received LVDS signals and carries out recovery shaping, adjusts it and transmits electrical characteristic；Pass through institute
State transmission clock data calibration module to calibrate link transmission clock and link serially-transmitted data, eliminate clock and data
Relative delay between signal so that transmission data and clock alignment；The transmission demodulation module will be each according to transmission clock
The LVDS signals of link demodulate respectively, carry out serioparallel exchange, are demodulated to parallel data；The video conversion module according to it is described simultaneously
Row data, obtain rgb image data.
10. as the generation of claim 7 to 9 any one of them is used for the system of the MIPI signals of MIPI modules detection, its feature
It is, further includes MIPI clock datas calibration module and MIPI output modules；
The first input end of the MIPI clock datas calibration module connects the first output terminal of the MIPI modular converters, receives
MIPI clock signals；Second input terminal connects the second output terminal of the MIPI modular converters, receives MIPI data-signals；3rd
Input terminal connects the 5th output terminal of MIPI control modules, receives MIPI transmission delays adjustment signal；
The first input end of the MIPI output modules connects the first output terminal of the MIPI clock datas calibration module, receives
MIPI exports clock；Second input terminal connects the second output terminal of the MIPI clock datas calibration module, receives MIPI outputs
Data；3rd input terminal connects the 6th output terminal of MIPI control modules, receives MIPI output control signals；The MIPI outputs
The output terminal of module, as the output interface of the system, for connecting MIPI modules to be measured；
The MIPI clock datas calibration module is used to calibrate the phase between MIPI clocks and each Channel Data Signal so that
It can ensure that clock and each data-signal can accomplish clock and each number of channel according to MIPI DPHY agreements when being output to connector
It is believed that number center alignment；
The MIPI output modules are then used to carry out electrical characteristic to the MIPI signals of MIPI clock datas calibration module output, pass
Defeated characteristic and impedance operator adjustment.
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| CN105472287B (en) * | 2015-12-05 | 2019-03-08 | 武汉精测电子集团股份有限公司 | A kind of single channel HDMI video signal single channel turns the device and method of multichannel |
| CN106250342A (en) * | 2016-08-23 | 2016-12-21 | 广东高云半导体科技股份有限公司 | A kind of MIPI interface circuit based on FPGA True LVDS interface and operation method thereof |
| CN109639380B (en) * | 2018-11-29 | 2020-11-06 | 海信视像科技股份有限公司 | MIPI signal processing method, device, equipment and storage medium |
| CN109660746B (en) * | 2018-11-30 | 2021-08-13 | 瀚湄信息科技(上海)有限公司 | MIPI signal distance transmission device and method |
| CN109656863B (en) * | 2018-12-24 | 2022-07-01 | 上海微阱电子科技有限公司 | High-bandwidth MIPI data processing interface circuit |
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| CN110381483B (en) * | 2019-03-21 | 2020-05-01 | 重庆工程职业技术学院 | Data communication device based on image processing |
| CN111163311B (en) * | 2020-02-13 | 2022-05-24 | 维沃移动通信有限公司 | Phase calibration method and electronic device |
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| CN111736576B (en) * | 2020-08-03 | 2020-11-20 | 天津美腾科技股份有限公司 | Image time synchronization controller testing tool and testing method thereof |
| CN112365830B (en) * | 2020-11-13 | 2022-11-15 | 苏州华兴源创科技股份有限公司 | Signal driving board |
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