CN104916674A - Current enhanced type lateral insulated gate bipolar transistor - Google Patents
Current enhanced type lateral insulated gate bipolar transistor Download PDFInfo
- Publication number
- CN104916674A CN104916674A CN201510181744.2A CN201510181744A CN104916674A CN 104916674 A CN104916674 A CN 104916674A CN 201510181744 A CN201510181744 A CN 201510181744A CN 104916674 A CN104916674 A CN 104916674A
- Authority
- CN
- China
- Prior art keywords
- type
- emitter region
- region
- type emitter
- square groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 27
- 229910052760 oxygen Inorganic materials 0.000 claims description 27
- 239000001301 oxygen Substances 0.000 claims description 27
- 238000009413 insulation Methods 0.000 claims description 14
- 235000019994 cava Nutrition 0.000 claims description 13
- 230000003139 buffering effect Effects 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
A current enhanced type lateral insulated gate bipolar transistor improves current density and the turn-off speed on the premise that a latching ability is maintained to be unchanged. The semiconductor is provided with buried oxide disposed on a P-type substrate and an N-drift region disposed on the buried oxide, a P-body region and an N-buffer region are disposed on the N-drift region, a P-type collecting electrode region is disposed in the N-buffer region, an anode metal is connected to the P-type collecting electrode region, a field oxide layer is disposed on the N-drift region, a P-well region is disposed in the P-body region, a P-type emitting electrode region and an emitting electrode region are disposed in the P-well region, the inner-side boundaries of the four regions, i.e., the P-body region, the P-well region, the P-type emitting electrode region and the emitting electrode region are synchronously recessed inwardly to form a square groove, the emitting electrode region surrounding the groove is successively defined as a first P-type emitting electrode region, second, third and fourth N-type emitting electrode regions and a fifth P-type emitting electrode region, the N-drift region protrudes outwardly and fills the square groove, a surface of the P-body region is provided with a gate oxide layer, a surface of the gate oxide layer is provided with a polysilicon layer, and a gate metal is connected to the polysilicon layer.
Description
Technical field
The present invention relates generally to power semiconductor device technology field, is a kind of intensifying current type landscape insulation bar double-pole-type transistor, is specially adapted in high pressure three-phase single-chip inverter integrated circuit, is used for driving DC brushless motor.
Background technology
Insulated gate bipolar transistor IGBT is that mos gate device architecture combines with bipolar transistor structure the compound power device of evolving, possess the feature of metal-oxide-semiconductor and bipolar transistor simultaneously, there is the tradeoff between good on state current and switching loss.Silicon-on-insulator lateral insulated gate bipolar transistor (SOI-Lateral Insulated Gate Bipolar Transistor, SOI-LIGBT) be a kind of typically based on the device of SOI technology, there is advantages such as being easy to integrated, withstand voltage height, current drive capability is strong, switching speed is fast, be widely applied in power integrated circuit.
Because SOI-LIGBT is used as the power switch pipe in power integrated circuit, its power loss determines the loss of whole system, power loss comprises conduction loss and turn-off power loss, in order to reduce the conduction loss of SOI-LIGBT, just must improve the conducting current density of device; In order to reduce the turn-off power loss of SOI-LIGBT, the turn-off speed of device just must be improved.In order to improve the conducting current density of device, be currently suggested some devices, such as many raceway grooves LIGBT, three-dimensional raceway groove LIGBT and E
2lIGBT.But while these devices improve conducting current density, again can with serving new problem, for many raceway grooves LIGBT, the charge carrier quantity turning off the storage of front drift region is more, and there is no the emptying passage of special holoe carrier, add the turn-off time of device, other technology improving conducting current density also can bring device withstand voltage to decline or degradation problem under anti-breech lock ability.Withstand voltage decline, reduces the maximum operating voltage of device, and the utilization of device is restricted; Turn-off time increases, and causes the switching loss of device significantly to increase; Latch-up can make gate signal lose control to device, and device architecture may experience destructive failure, the decline of breech lock rejection ability, and the reliability of device is reduced.
Therefore, the basis of withstand voltage, the breech lock rejection ability that do not reduce SOI-LIGBT of retainer member is improved the conducting current density of SOI-LIGBT and reduced the main development direction that the turn-off time is SOI-LIGBT, the design tool of power integrated circuit is of great significance.
Summary of the invention
The present invention is directed to the problems referred to above, propose a kind of intensifying current type landscape insulation bar double-pole-type transistor.Under the prerequisite that this structure is withstand voltage in retainer member, suppress breech lock ability not reduce, significantly improve the current density of device, also improve the shutoff speed of device simultaneously.
A kind of intensifying current type landscape insulation bar double-pole-type transistor, comprise: P type substrate, P type substrate is provided with and buries oxygen, be provided with N-type drift region burying on oxygen, P type tagma and N-type buffering area is respectively equipped with in the both sides of N-type drift region, heavily doped P type collector area is provided with in N-type buffering area, heavily doped P type collector area is connected with anode metal, an oxygen layer is provided with above N-type drift region, one lateral boundaries of described field oxygen layer drops on above N-type buffering area, opposite side border connects with P type tagma and is straight flange circle, P type trap zone is provided with in P type tagma, heavily doped P type emitter region and emitter region is provided with in P type trap zone, cathodic metal is connected with in heavily doped P type emitter region and emitter region, it is characterized in that, described P type tagma, P type trap zone, the inner side boundary synchronisation of heavily doped P type emitter region and emitter region caves in formation one square groove, the bottom of the square groove that caves in of emitter region is defined as the 3rd N-type emitter region, the both sides of the square groove that caves in of emitter region are defined as the second N-type emitter region and the 4th N-type emitter region respectively, the emitter region part be connected with the summit, both sides of the square groove that caves in of emitter region is respectively defined as a P type emitter region and the 5th P type emitter region respectively, described N-type drift region evagination is also full of square groove, P type body surface beyond P type trap zone is provided with gate oxide, described gate oxide extends to field oxygen layer and terminates in the border of an oxygen layer, polysilicon layer is provided with and described polysilicon layer extends to above an oxygen layer on gate oxide surface, be connected with grid metal on the polysilicon layer.
Described intensifying current type landscape insulation bar double-pole-type transistor, is characterized in that a P type emitter region, the 5th P type emitter region can become N-type heavy doping entirely.
Described intensifying current type landscape insulation bar double-pole-type transistor, is characterized in that a P type emitter region, the second N-type emitter region, the 3rd N-type emitter region, the 4th N-type emitter region, the 5th P type emitter region length range are 0.5um ~ 100um.
Compared with prior art, tool of the present invention has the following advantages:
The invention provides a kind of intensifying current type landscape insulation bar double-pole-type transistor, after the inner side boundary synchronisation of P type tagma, P type trap zone, heavily doped P type emitter region and emitter region caves in, define the emitter region of U-shaped, compared to traditional single raceway groove LIGBT, considerably increase the channel length of equivalence.When device is opened, the efficiency that electronics injects from channel region significantly promotes, thus drift region carrier concentration is raised; So when drain terminal PN junction is opened, more hole will be impelled to inject from drain terminal, form stronger conductivity modulation effect, greatly improve the On current ability of device.
For traditional devices, holoe carrier by N-type emitter region, must enter source; And the first, the 5th emitter region of the present invention is the heavy doping of P type, holoe carrier is then enter source by the first, the 5th P type emitter region, P type emitter region itself absorbs a large amount of holoe carriers, inhibit the unlatching of parasitic NPN transistor on the one hand, improve the anti-latching feature of device; Improve the turn-off speed of device on the other hand, reduce turn-off power loss.
Meanwhile, first, second, third, fourth, the length ratio of the 5th emitter region is adjustable, one P type emitter region and the 5th P type emitter region also can all replace to N-type heavily doped region, so in actual applications can be more flexible, compromise in increase conducting current density and improving between anti-breech lock ability.
Therefore device of the present invention can not only significantly improve the conducting current density of device, and improve the turn-off speed of device, improve the breech lock rejection ability of device.
Accompanying drawing explanation
Figure 1 shows that the device profile structure chart of common landscape insulation bar double-pole-type transistor.
Figure 2 shows that the structure three-dimensional figure of U-shaped channel laterally insulated gate bipolar transistor of the present invention.
Figure 3 shows that structure of the present invention remove metal electrode and half polysilicon after graphics.
Figure 4 shows that structure of the present invention is removed after metal electrode and the graphics of grid oxide layer.
Figure 5 shows that structure of the present invention remove metal electrode and field oxygen layer after vertical view.
Figure 6 shows that the vertical view that structure of the present invention is removed metal electrode and field oxygen layer post tensioned unbonded prestressed concrete and added malleation.
Figure 7 shows that structure of the present invention remove metal electrode and field oxygen layer after the first, the 5th P type emitter region change into full N-type doping vertical view.
Figure 8 shows that the vertical view changing the 3rd N-type emitter region length after structure of the present invention removes metal electrode and field oxygen layer.
Figure 9 shows that the vertical view changing second, four N-type emitter region length after structure of the present invention removes metal electrode and field oxygen layer.
Figure 10 shows that the vertical view changing the first, the 5th P type emitter region length after structure of the present invention removes metal electrode and field oxygen layer.
Figure 11 shows that structure of the present invention second, third, the 4th N-type emitter region different length time conducting current density figure.
Conducting current density when Figure 12 shows that structure of the present invention one P type emitter region different length and breech lock voltage pattern.
Figure 13 shows that the I-V curve comparison figure of structure of the present invention and traditional structure.
Figure 14 shows that the breech lock voltage compare figure of structure of the present invention and traditional structure.
Figure 15 shows that the turn-off time comparison diagram of structure of the present invention and traditional structure.
Figure 16 shows that the withstand voltage comparison diagram of structure of the present invention and traditional structure.
Embodiment
Below in conjunction with Fig. 2, Fig. 3, the present invention is elaborated, a kind of intensifying current type landscape insulation bar double-pole-type transistor, comprise: P type substrate 1, P type substrate 1 is provided with and buries oxygen 2, be provided with N-type drift region 3 burying on oxygen 2, P type tagma 4 and N-type buffering area 9 is respectively equipped with in the both sides of N-type drift region 3, heavily doped P type collector area 8 is provided with in N-type buffering area 9, heavily doped P type collector area 8 is connected with anode metal 10, an oxygen layer 16 is provided with above N-type drift region 3, one lateral boundaries of described field oxygen layer 16 drops on above N-type buffering area 9, opposite side border connects with P type tagma 4 and is straight flange circle, P type trap zone 5 is provided with in P type tagma 4, heavily doped P type emitter region 6 and emitter region 7 is provided with in P type trap zone 5, cathodic metal 11 is connected with in heavily doped P type emitter region 6 and emitter region 7, it is characterized in that, described P type tagma 4, P type trap zone 5, the inner side boundary synchronisation of heavily doped P type emitter region 6 and emitter region 7 caves in formation one square groove 17, the width of emitter region 7 is definite value, the border, inner side in P type tagma 4 is definite value to the distance on the border, inner side of P type trap zone 5, the bottom of the square groove 17 that caves in of emitter region 7 is defined as the 3rd N-type emitter region 7c, the both sides of the square groove 17 that caves in of emitter region 7 are defined as the second N-type emitter region 7b and the 4th N-type emitter region 7d respectively, the emitter region part be connected with the summit, both sides of the square groove 17 that caves in of emitter region 7 is respectively defined as a P type emitter region 7a and the 5th P type emitter region 7e respectively, one P type emitter region 7a is identical with the length of the 5th P type emitter region 7e, described N-type drift region 3 evagination is also full of square groove 17, surface, P type tagma 4 beyond P type trap zone 5 is provided with gate oxide 13, described gate oxide 13 extends to field oxygen layer 16 and terminates in the border of an oxygen layer 16, polysilicon layer 15 is provided with and described polysilicon layer 15 extends to above an oxygen layer 16 on gate oxide 13 surface, polysilicon layer 15 is connected with grid metal 14.
Described intensifying current type landscape insulation bar double-pole-type transistor, is characterized in that a P type emitter region 7a, the 5th P type emitter region 7e can become N-type heavy doping entirely.
Described intensifying current type landscape insulation bar double-pole-type transistor, is characterized in that a P type emitter region 7a, the second N-type emitter region 7b, the 3rd N-type emitter region 7c, the 4th N-type emitter region 7d, the 5th P type emitter region 7e length range is 0.5um ~ 100um.
Below in conjunction with accompanying drawing, the present invention is further described.
Operation principle of the present invention:
The gate electrode of device adds malleation, as Fig. 6, defines the raceway groove that connects heavily doped N-type emitter region and N-type drift region below grid.When collector electrode adds malleation, electronic current is sent to N-type drift region from N-type emitter region.Electron amount through raceway groove is relevant to the length of raceway groove, and raceway groove is longer, and electron amount is more.Described device is compared to traditional device, and the channel length of equivalence is longer, and the efficiency that electronics injects from channel region significantly promotes.Electronic current is as the ideal base drive current of PNP transistor, and impel hole to inject N-type drift region from heavily doped P type collector region, injected holes defines the emitter current of PNP transistor.Traditional devices compared by described device, because the relation that electronic current increases, ideal base drive current increases, and more hole can be attracted to inject N-type drift region, increase the emitter current of PNP transistor.Electric current from collector electrode to emitter is made up of two parts, and comprise the patch portion through MOSFET region raceway groove and the bipolar portion flowing through PNP pipe, described device makes this two-part electric current all increase, and the total current of device significantly rises.When electric current flows through N-type drift region, it is in large injection state, because described device current is larger than traditional devices electric current, the carrier concentration of N-type drift region is higher, and conductivity modulation effect is also stronger, greatly improves the On current ability of device.
Alternately be made up of 4 layers of N-type and territory, p type island region in LIGBT structure, this generates parasitic thyristor.When LIGBT electric current is too large, make the part conducting of thyristor NPN, then parasitic thyristor latch, now in device, electric current continues to increase, and gate signal is by the shutoff of uncontrollable LIGBT, makes LIGBT structure experience destructive failure.The conducting current density of increased device, device enters into latch mode by lower voltage, reduces the reliability of device.For described device, hole flows into through N-type drift region from collector electrode, flow to emitter, and the first, the 5th P type emitter region, hole is directly absorbed, reduce the hole current flow through below N-type emitter region, thus inhibit the unlatching of parasitic NPN transistor, improve the anti-breech lock ability of device.
When device is in conducting state, N-type drift region is in large injection state, a large amount of non equilibrium carriers is had in N-type drift region, when gate signal adds zero potential, raceway groove turns off, and the hole that in N-type drift region, part is superfluous is through P type tagma, absorbed by the first, the 5th P type emitter region, the first, the 5th P type emitter region is that in device, non-equilibrium hole provides extra path to emitter, accelerates the speed that device turns off, thus reduces the shutoff power consumption of device.
Can all become N-type heavy doping for a P type emitter region of described device, the 5th P type emitter region, as Fig. 7, now the conducting current density of device will arrive maximum, but the latching feature of device also can be degenerated.
Adjustable respectively for the length between a P type emitter region of described device, the second N-type emitter region, the 3rd N-type emitter region, the 4th N-type emitter region, the 5th P type emitter region, adjustable scope is 0.5um ~ 100um.Second N-type emitter region, the 3rd N-type emitter region, the 4th N-type emitter region define a JFET region, 17 regions in Fig. 5, and JEFT district creates extra resistance R
jEFT, but in the ordinary course of things, drift resistance is main (R
drain>>R
jEFT), JEFT district resistance can be ignored.When changing each interval emitter region length, the shape in JEFT region also changes, and the resistance in JEFT district also just changes.Length when the 3rd N-type emitter region reduces, as Fig. 8, R
jEFTto increase, the length of the 3rd N-type emitter region little to a certain extent time, R
jEFTcannot ignore, now total conducting resistance increases, and conducting current density reduces, and therefore will ensure that the length of the 3rd N-type emitter region can not be too little.
And when change second N-type emitter region and the 4th N-type emitter region length, as Fig. 9, the length of the second N-type emitter region is longer, equivalent channel length is longer, and the injection efficiency of electronics is also higher, and conducting current density increases.But the second N-type emitter region is larger, the resistance in JEFT district is also larger, when the length of the second N-type emitter region is too large, and R
jEFTcannot ignore, total conducting resistance is increased, and conducting current density reduces, and therefore the length of the second N-type emitter region has a definite limitation, can not unrestrictedly increase.
And when change the one P type emitter region and the 5th P type emitter region length, as Figure 10, the length of a P type emitter region is longer, and the hole absorption ability in a territory, emitter p type island region, P type emitter region also strengthens, the anti-breech lock ability of device rises, and turn-off speed promotes; But the length of a P type emitter region increases, and the contraction in length of specific equivalent raceway groove, now the electron injection efficiency of emitter also can reduce, and the conducting current density of device also reduces.
Therefore device of the present invention significantly improves the current density of device on the basis that retainer member is withstand voltage, reduces the turn-off time of device, also improve the breech lock rejection ability of device.
In order to verify benefit of the present invention, this patent has carried out contrast simulation, by semiconductor device simulation software SentaurusTcad as shown in Figure 11 ~ Figure 16 to structure.In figure, W
pCbe the length of the first, the 5th P type emitter region, W
oCbe the length of the second, the 4th N-type emitter region, W
pEbe the length of the 3rd N-type emitter region.Current density figure when Figure 11 is second, third N-type emitter region different length of structure of the present invention, the length as seen from the figure when the 3rd N-type emitter region reduces, R
jEFTto increase, the length of the 3rd N-type emitter region little to a certain extent time, R
jEFTcannot ignore, now total conducting resistance increases, and conducting current density reduces, and therefore will ensure that the length of the 3rd N-type emitter region can not be too little; When the length of the 3rd N-type emitter region is oversize, the ratio of the two or four N-type emitter region length reduces, and the equivalent channel length of unit sizes reduces, and electron injection efficiency reduces, and conducting current density reduces, and therefore the length of the 3rd N-type emitter region can not be oversize.When increase second N-type emitter region and the 4th N-type emitter region length, the length of the second N-type emitter region is longer, and equivalent channel length is longer, and the injection efficiency of electronics is also higher, and conducting current density increases.But the second N-type emitter region is larger, the resistance in JEFT district is also larger, when the length of the second N-type emitter region is too large, and R
jEFTcannot ignore, total conducting resistance is increased, and conducting current density reduces, and therefore the length of the second N-type emitter region has a definite limitation, can not unrestrictedly increase.Conducting current density when Figure 12 is structure of the present invention one P type emitter region different length and breech lock voltage pattern, a P type emitter region length increases as seen from the figure, and the current density of device reduces, and breech lock voltage increases, in practical application, can the structure of adjusting device according to demand.Figure 13 is the I-V curve comparison figure of structure of the present invention and traditional structure, and the On current energy force rate traditional structure of structure of the present invention is strong as seen from the figure.Figure 14 is the breech lock voltage compare figure of structure of the present invention and traditional structure, and the breech lock voltage of structure devices of the present invention is larger as seen from the figure, stronger to the rejection ability of latch-up.Figure 15 shows that the turn-off time comparison diagram of structure of the present invention and traditional structure, the turn-off time of structure of the present invention is shorter as seen from the figure, and the turn-off power loss of device is lower.Figure 16 is the withstand voltage comparison diagram of structure of the present invention and traditional devices, and structure of the present invention is withstand voltage identical with traditional devices as seen from the figure, is improving the current density of device, and when improve the breech lock rejection ability of device, the withstand voltage not loss of device.
In sum, therefore the basis that can not degenerate at withstand voltage, the breech lock rejection ability of retainer member of device of the present invention improved the conducting current density of SOI-LIGBT and turn off speed.
Claims (3)
1. an intensifying current type landscape insulation bar double-pole-type transistor, comprise: P type substrate (1), P type substrate (1) is provided with and buries oxygen (2), be provided with N-type drift region (3) burying on oxygen (2), P type tagma (4) and N-type buffering area (9) are respectively equipped with in the both sides of N-type drift region (3), heavily doped P type collector area (8) is provided with in N-type buffering area (9), heavily doped P type collector area (8) is connected with anode metal (10), an oxygen layer (16) is provided with in the top of N-type drift region (3), one lateral boundaries of described field oxygen layer (16) drops on the top of N-type buffering area (9), opposite side border connects with P type tagma (4) and is straight flange circle, P type trap zone (5) is provided with in P type tagma (4), heavily doped P type emitter region (6) and emitter region (7) are provided with in P type trap zone (5), cathodic metal (11) is connected with heavily doped P type emitter region (6) and emitter region (7), it is characterized in that, described P type tagma (4), P type trap zone (5), the inner side boundary synchronisation of heavily doped P type emitter region (6) and emitter region (7) caves in formation one square groove (17), the bottom of the square groove that caves in (17) of emitter region (7) is defined as the 3rd N-type emitter region (7c), the both sides of the square groove that caves in (17) of emitter region (7) are defined as the second N-type emitter region (7b) and the 4th emitter region, N interval (7d) respectively, the emitter region part be connected with the summit, both sides of the square groove that caves in (17) of emitter region (7) is respectively defined as a P type emitter region (7a) and the 5th P type emitter region (7e) respectively, described N-type drift region (3) evagination is also full of square groove (17), P type tagma (4) surface beyond P type trap zone (5) is provided with gate oxide (13), described gate oxide (13) extends to field oxygen layer (16) and terminates in the border of an oxygen layer (16), polysilicon layer (15) is provided with and described polysilicon layer (15) extends to the top of an oxygen layer (16) on gate oxide (13) surface, polysilicon layer (15) is connected with grid metal (14).
2. intensifying current type landscape insulation bar double-pole-type transistor according to claim 1, is characterized in that a P type emitter region (7a), the 5th P type emitter region (7e) can become N-type heavy doping entirely.
3. intensifying current type landscape insulation bar double-pole-type transistor according to claim 1, it is characterized in that a P type emitter region (7a), the second N-type emitter region (7b), the 3rd N-type emitter region (7c), the 4th N-type emitter region (7d), the 5th N-type emitter region (7e) length range be 0.5um ~ 100um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510181744.2A CN104916674B (en) | 2015-04-17 | 2015-04-17 | A kind of intensifying current type landscape insulation bar double-pole-type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510181744.2A CN104916674B (en) | 2015-04-17 | 2015-04-17 | A kind of intensifying current type landscape insulation bar double-pole-type transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104916674A true CN104916674A (en) | 2015-09-16 |
| CN104916674B CN104916674B (en) | 2017-10-31 |
Family
ID=54085591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510181744.2A Active CN104916674B (en) | 2015-04-17 | 2015-04-17 | A kind of intensifying current type landscape insulation bar double-pole-type transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104916674B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826367A (en) * | 2016-03-18 | 2016-08-03 | 东南大学 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
| CN110190120A (en) * | 2019-05-05 | 2019-08-30 | 东南大学 | A kind of landscape insulation bar double-pole-type transistor with low unlatching overshoot current |
| CN110729345A (en) * | 2019-09-29 | 2020-01-24 | 东南大学 | Trench gate type silicon-on-insulator lateral insulated gate bipolar transistor device |
| WO2022247322A1 (en) * | 2021-05-28 | 2022-12-01 | 无锡华润上华科技有限公司 | Lateral insulated-gate bipolar transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213617A (en) * | 1994-11-14 | 1996-08-20 | Fuji Electric Co Ltd | Semiconductor device and its driving method |
| US20050020040A1 (en) * | 2003-06-23 | 2005-01-27 | Masaharu Yamaji | Manufacturing method of a semiconductor device |
| US20090242930A1 (en) * | 2008-03-26 | 2009-10-01 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device |
| CN103236437A (en) * | 2013-04-25 | 2013-08-07 | 东南大学 | High-reliability N-type transverse insulated gate bipolar device and preparation process thereof |
| US20140339602A1 (en) * | 2012-03-02 | 2014-11-20 | Denso Corporation | Semiconductor device |
-
2015
- 2015-04-17 CN CN201510181744.2A patent/CN104916674B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213617A (en) * | 1994-11-14 | 1996-08-20 | Fuji Electric Co Ltd | Semiconductor device and its driving method |
| US20050020040A1 (en) * | 2003-06-23 | 2005-01-27 | Masaharu Yamaji | Manufacturing method of a semiconductor device |
| US20090242930A1 (en) * | 2008-03-26 | 2009-10-01 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device |
| US20140339602A1 (en) * | 2012-03-02 | 2014-11-20 | Denso Corporation | Semiconductor device |
| CN103236437A (en) * | 2013-04-25 | 2013-08-07 | 东南大学 | High-reliability N-type transverse insulated gate bipolar device and preparation process thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826367A (en) * | 2016-03-18 | 2016-08-03 | 东南大学 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
| CN110190120A (en) * | 2019-05-05 | 2019-08-30 | 东南大学 | A kind of landscape insulation bar double-pole-type transistor with low unlatching overshoot current |
| WO2020224358A1 (en) * | 2019-05-05 | 2020-11-12 | 东南大学 | Lateral insulated gate bipolar transistor with low turn-on overshoot current |
| CN110190120B (en) * | 2019-05-05 | 2021-09-28 | 东南大学 | Transverse insulated gate bipolar transistor with low turn-on overshoot current |
| US11367785B2 (en) | 2019-05-05 | 2022-06-21 | Southeast University | Lateral insulated gate bipolar transistor with low turn-on overshoot current |
| CN110729345A (en) * | 2019-09-29 | 2020-01-24 | 东南大学 | Trench gate type silicon-on-insulator lateral insulated gate bipolar transistor device |
| CN110729345B (en) * | 2019-09-29 | 2023-08-04 | 东南大学 | Trench gate type silicon-on-insulator lateral insulated gate bipolar transistor device |
| WO2022247322A1 (en) * | 2021-05-28 | 2022-12-01 | 无锡华润上华科技有限公司 | Lateral insulated-gate bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104916674B (en) | 2017-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105322002B (en) | Reverse conduction IGBT | |
| CN102832216B (en) | Semiconductor device including insulated gate bipolar transistor and diode | |
| CN106505101B (en) | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device | |
| CN107768429B (en) | Super junction IGBT device with mixed conduction mode | |
| CN107785415B (en) | SOI-RC-LIGBT device and preparation method thereof | |
| CN106847891B (en) | A kind of RC-IGBT device controlling knot terminal integral body diode by MOSFET | |
| CN105826367A (en) | Large-current silicon on insulator lateral insulated gate bipolar transistor device | |
| US20110233684A1 (en) | Semiconductor device | |
| CN103022089A (en) | Reverse conducting type insulated gate bipolar transistor without snapback effect | |
| CN107293579A (en) | A kind of superjunction IGBT with low conduction voltage drop | |
| CN104299995A (en) | Semiconductor device | |
| US20150187877A1 (en) | Power semiconductor device | |
| JP2012064908A (en) | Semiconductor device and control method thereof | |
| CN104916674A (en) | Current enhanced type lateral insulated gate bipolar transistor | |
| CN102306657A (en) | Insulated gate bipolar transistor with floating buried layer | |
| CN103762230B (en) | N-channel injection efficiency reinforced insulation grid bipolar transistor | |
| CN106024876B (en) | For eliminating the inverse conductivity type landscape insulation bar double-pole-type transistor device of hysteresis phenomenon | |
| CN106876455A (en) | A kind of double trench gate SOI LIGBT device architectures of low turn-off power loss | |
| CN106067799B (en) | A kind of semiconductor devices | |
| JP2020532120A (en) | Power MOSFET device | |
| Zhang et al. | Optimization of ${V} _ {\text {CE}} $ Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF | |
| CN102194864A (en) | Groove-grid-type insulated gate bipolar transistor with body electrode | |
| CN104078498B (en) | A kind of trench isolations landscape insulation bar double-pole-type transistor | |
| CN103928507B (en) | A kind of inverse conductivity type double grid insulated gate bipolar transistor | |
| KR102585094B1 (en) | Separated Buffer Super Junction IGBT |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20170918 Address after: 99 No. 214135 Jiangsu New District of Wuxi City Linghu Avenue Applicant after: Southeast University Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 99 No. 214135 Jiangsu New District of Wuxi City Linghu Avenue Applicant before: Southeast University Applicant before: Wuxi CSMC Semiconductor Co., Ltd. Applicant before: Wuxi Huarun Shanghua Technology Co., Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |