CN102231627B - Method for realizing short-time pulse signal - Google Patents
Method for realizing short-time pulse signal Download PDFInfo
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- CN102231627B CN102231627B CN201110085576.9A CN201110085576A CN102231627B CN 102231627 B CN102231627 B CN 102231627B CN 201110085576 A CN201110085576 A CN 201110085576A CN 102231627 B CN102231627 B CN 102231627B
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Abstract
The invention relates to a method for realizing a short-time pulse signal and a device thereof, wherein the device comprises a latch unit for latching a high level of an input signal, a delay unit for delaying the latch signal and a reset unit for asynchronously clearing the latch signal; the latch unit is connected to the reset unit through the delay unit; the reset unit is connected to the latch unit; the latch unit is a flip-flop. The invention provides a method and a device for realizing a short-time pulse signal which can generate nanosecond short-time pulses, the width of the pulses is related to delay parameters of a delay circuit, is unrelated to the frequency of a working clock of the circuit and can meet a specific phase relation.
Description
Technical field
The present invention relates to a kind of implementation method of pulse signal, relate in particular to a kind of implementation method and device thereof of short pulse signal.
Background technology
At present, FPGA is widely used in Design of Digital System field, method for designing based on FPGA has advantages of flexibly, integrated level is high, but, application FPGA must face the constraint of device speed and area, and for the concrete application such as space flight, military project, the resource of the FPGA that can access and speed are all very limited, in the situation that speed and resource are all restricted, the design work meeting of FPGA faces some new problems.Such as in the design objective of certain FPGA, need to produce the short-time pulse control signal in cycle, the width of these pulse signals is about 10ns left and right, if realized with conventional synchronous design method, it is the input clock of 100MHz that FPGA at least needs frequency, but design objective the maximum operation frequency of getable FPGA be only 70MHz, obviously, constraints limit the application of conventional method, be badly in need of a kind of new method for designing, make its speed restriction of breaking through FPGA device itself, produce the short-time pulse of nanosecond, and meet specific phase relation.
Summary of the invention
In order to solve the above-mentioned technical problem existing in background technology, the invention provides and a kind ofly produce the short-time pulse of nanosecond, the width of pulse is relevant with the delay parameter of delay circuit, with the frequency-independent of the work clock of circuit and implementation method and the device thereof that can meet the short pulse signal of specific phase relation.
Technical solution of the present invention is: the invention provides a kind of implementation method of short pulse signal, its special character is: said method comprising the steps of:
1) obtain the clock signal that short-time pulse produces circuit;
2) produce input signal;
4) in step 1) triggering of resulting clock signal is along to step 2) high level of the input signal that obtains latchs, and obtains latch signal;
5) latch signal is carried out to time delay, obtain time delayed signal;
6) with time delayed signal as control signal to step 3) resulting latch signal carries out asynchronous resetting, obtains short pulse signal.
Said method is in step 2) and step 4) between also comprise:
3) to step 2) resulting input signal enters horizontal phasing control, obtains phase shift signalling.
During the phase shift signalling above-mentioned step 3 that obtains), described step 4) be in step 1) triggering of resulting clock signal is along to step 2) high level or the step 3 of the input signal that obtains) high level of the phase shift signalling obtaining that produces latchs, and obtains latch signal.
Said method also comprises:
7) to step 6) resulting short pulse signal carries out polarity adjustment.
Above-mentioned steps 1) clock signal in is by the direct frequency producing of crystal oscillator, to be less than the clock signal of 100MHz.
Latching above-mentioned steps 4) is to latch in the rising edge triggering of global clock signal.
The mode of the time delay above-mentioned steps 5) is gate delay and wiring time delay.
An implement device for short pulse signal, its special character is: described device comprises latch units for the high level of input signal is latched, for latch signal being carried out to the delay unit of time delay and the reset unit that carries out asynchronous resetting for latch signal; Described latch units accesses reset unit by delay unit; Described reset unit access latch units; Described latch units is trigger.
Said apparatus also comprises for input signal being entered to the phasing unit of horizontal phasing control; Described phasing unit is by latch units access delay unit; Described phasing unit is buffer.
Said apparatus also comprises for the short pulse signal having got being carried out to the Polarity Control unit of polarity adjustment; Described Polarity Control unit access latch units; Described Polarity Control unit is not gate or directly output.
Advantage of the present invention is:
1, can produce nanosecond short-time pulse.The implementation method of short pulse signal provided by the present invention latchs the high level on the triggering edge of the clock obtaining before, to carry out time delay to latch signal simultaneously, obtain after time delayed signal as control signal, by latch signal asynchronous resetting, obtaining short pulse signal.The present invention changes and traditional realize short-time pulse and need to adopt the clock cycle to be less than the clock of pulse duration, the method adopts low-frequency clock to produce the short-time pulse of nanosecond, clock frequency significantly reduces, and is highly suitable in the system that external clock frequency is restricted and uses.
2, can meet specific phase relation.The implementation method of short pulse signal provided by the present invention can change the polarity of short-time pulse according to actual needs, use low-frequency clock to produce the short-time pulse of nanosecond, this method can be applied to the occasion that FPGA operating frequency is restricted, simultaneously, by changing the number of buffer, can change short-time pulse width and phase place, implementation is flexible, simple in structure, be easy to realize.
Accompanying drawing explanation
Fig. 1 is the principle framework structural representation of the implement device of short pulse signal provided by the present invention;
Fig. 2 is the basic circuit diagram of the implement device of short pulse signal provided by the present invention;
Fig. 3 is the sequential chart of the short pulse signal that produces of the implementation method according to short pulse signal provided by the present invention.
Embodiment
The implementation method that the invention provides a kind of short pulse signal, the method comprises the following steps:
1) obtain the clock signal that short-time pulse produces circuit; This clock signal is that clock frequency is less than 100MHz by the direct clocking of crystal oscillator;
2) obtain the asynchronous reset signal that short-time pulse produces circuit; The effect of this reset signal is that the output signal of short-time pulse generation circuit is carried out to asynchronous reset, Low level effective;
3) produce input signal; The positive negative pulse stuffing width of input signal is all greater than input clock cycle;
4) for the phase relation of short pulse signal and input signal is met design requirement, can enter horizontal phasing control to input signal, obtain phase shift signalling;
5) in step 1) triggering of resulting clock is along to step 3) high level of the input signal that obtains latchs or step 4) high level of the phase shift signalling that obtains latchs, and obtains latch signal; Latch, utilize exactly the rising edge triggering of global clock to latch.
6) latch signal is carried out to time delay, obtain time delayed signal; The mode of time delay is: gate delay and wiring time delay.
7) use time delayed signal, as control signal by latch signal asynchronous resetting, obtains short pulse signal;
8) short pulse signal having acquired is carried out to polarity adjustment, namely the short-time pulse having acquired is carried out to operated in anti-phase.Short pulse signal is directly exported and obtained positive short pulse signal; The anti-phase rear output of short pulse signal is obtained to negative short pulse signal.
Referring to Fig. 1 and Fig. 2, the present invention is when providing a kind of short pulse signal production method, a kind of device that produces short pulse signal is also provided, and this device comprises latch units for the high level of input signal is latched, for latch signal being carried out to the delay unit of time delay and the reset unit that carries out asynchronous resetting for latch signal; Latch units accesses reset unit by delay unit; Reset unit access latch units; Latch units is trigger.
For the ease of the short-time pulse having obtained is entered to horizontal phasing control, short pulse signal generation device provided by the present invention also comprises for input signal being entered to the phasing unit of horizontal phasing control; Phasing unit is by latch units access delay unit; This phasing unit is buffer.
For the ease of the short pulse signal acquiring is carried out to polarity adjustment, device provided by the present invention also comprises for the short pulse signal having got being carried out to the Polarity Control unit of polarity adjustment; Polarity Control unit access latch units; This Polarity Control unit can be not gate or directly output.
The present invention is when work, and input signal directly triggers along being latched unit latches at clock after phasing unit enters horizontal phasing control; Latch signal is as the input signal of reset unit after delay unit time delay, and reset signal is as the input signal of reset unit; The output signal of reset unit as the control signal of latch units by latch signal zero clearing; Latch signal is exported short pulse signal after selecting to process by the polarity of Polarity Control unit.
Referring to Fig. 2 and Fig. 3, will the implementation method of short pulse signal provided by the present invention be described further by specific embodiment, the specific implementation step of the implementation method of short pulse signal provided by the present invention is as follows:
1) input end of clock of input clock signal CLK access trigger B-REG and C-REG, rising edge triggers, and trigger B-REG and C-REG form latch units;
2) input reset signal RESET first through not gate INV again through or door OR after the asynchronous resetting end CLR of input trigger B-REG and C-REG, CLR high level is effective, RESET Low level effective, not gate INV and or door OR form reset unit;
3) input signal A produces signal A-SHFT after the buffer BUFD of 3 series windings, A-SHFT input trigger B-REG, the buffer of 3 series windings forms phasing unit, if do not needed into horizontal phasing control, and the direct input trigger C-REG of input signal A;
4) the signal A-SHFT after phase place adjustment and input signal A are latched respectively in unit at rising edge clock trigger B-REG and C-REG latch;
5) trigger B-REG output signal first through the buffer BUFD time delay of 2 series windings again through or door OR after the asynchronous resetting end CLR of input trigger B-REG, trigger C-REG output signal first through 3 buffer BUFD time delay again through or door OR after the asynchronous resetting end CLR of input trigger C-REG, the buffer of series winding forms delay unit;
6) trigger C-REG output signal is exported negative short pulse signal C-N after not gate INV, and not gate forms Polarity Control unit, if do not need to carry out polarity adjustment, trigger B-REG directly exports positive short pulse signal B-P;
7) when RESET signal is ' 0 ', circuit reset, reset unit output ' 1 ', the asynchronous resetting end CLR of trigger B-REG and C-REG be ' 1 ', trigger B-REG and C-REG export and are ' 0 ', B-P and C-N is respectively ' 0 ' and ' 1 ';
8), when RESET signal is ' 1 ', circuit enters normal operating conditions; At the rising edge of clock CLK, input signal A is latching to trigger B-REG, the signal A-SHFT after phase place adjustment is latching to trigger C-REG; When A and A-SHFT are ' 0 ', rising edge triggers, and trigger B-REG and C-REG are output as ' 0 ', and keep 1 clock cycle; When A and A-SHFT are ' 1 ', rising edge triggers, trigger B-REG and C-REG are output as ' 1 ', this signal is output as ' 1 ' after delay unit and reset unit, and the asynchronous resetting end CLR of input trigger B-REG and C-REG is by trigger B-REG and C-REG zero clearing, the output of trigger B-REG and C-REG becomes ' 0 ' from ' 1 ', and keeps ' 0 ' to next rising edge clock; Trigger B-REG from the ' 1 ' time that becomes ' 0 ' process experience is: time delay+wiring time delay of time delay+1 of 2 buffer BUFD or an OR, this time is exactly the width of the short pulse signal B-P of generation, trigger C-REG from the ' 1 ' time that becomes ' 0 ' process experience is: time delay+wiring time delay of time delay+1 of 3 buffer BUFD or an OR, and this time is exactly the width of the short pulse signal C-N of generation; The quantity that increases or reduce buffer BUFD can increase and reduce the width of short-time pulse;
9) output of trigger C-REG produces negative short pulse signal C-N through 1 not gate;
10) signal A-SHFT is the phase shift signal producing after 3 buffer BUFD time delay of signal A, and the quantity that increases or reduce buffer in phasing unit is equivalent to increase or reduce short pulse signal with respect to the phase shift size of A-SHFT signal.
Claims (5)
1. an implementation method for short pulse signal, is characterized in that: said method comprising the steps of:
1) obtain the clock signal that short-time pulse produces circuit; Described clock signal is by the direct frequency producing of crystal oscillator, to be less than the clock signal of 100MHz;
2) produce input signal; The positive negative pulse stuffing width of described input signal is all greater than input clock cycle;
4) in the triggering of the resulting clock signal of step 1) along to step 2) high level of the input signal that obtains latchs, and obtains latch signal; Described latching is to trigger and latch at the rising edge of global clock signal;
5) latch signal is carried out to time delay, obtain time delayed signal;
6) with time delayed signal, as control signal, the resulting latch signal of step 4) is carried out to asynchronous resetting, obtain short pulse signal; Described asynchronous resetting needs asynchronous reset signal, Low level effective.
2. the implementation method of short pulse signal according to claim 1, is characterized in that: described method is in step 2) and step 4) between also comprise:
3) to step 2) resulting input signal enters horizontal phasing control, obtains phase shift signalling.
3. the implementation method of short pulse signal according to claim 2, it is characterized in that: described in while obtaining the phase shift signalling of step 3), described step 4) is along to step 2 in the triggering of the resulting clock signal of step 1)) high level of the input signal that obtains or the high level that step 3) produces the phase shift signalling obtaining latch, and obtains latch signal.
4. according to the implementation method of the short pulse signal described in claim 1 or 2 or 3, it is characterized in that: described method also comprises:
7) the resulting short pulse signal of step 6) is carried out to polarity adjustment.
5. the implementation method of short pulse signal according to claim 4, is characterized in that: the mode of the time delay in described step 5) is gate delay and wiring time delay.
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| CN201110085576.9A CN102231627B (en) | 2011-04-06 | 2011-04-06 | Method for realizing short-time pulse signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102427350B (en) * | 2011-11-29 | 2014-07-23 | 上海新进半导体制造有限公司 | PWM (Pulse-Width Modulation) signal phase-shift circuit and control method |
| CN109428592B (en) * | 2017-08-23 | 2023-08-15 | 科大国盾量子技术股份有限公司 | Method and system for generating high-frequency specific sequence pulse |
| CN109932995B (en) * | 2017-12-18 | 2021-06-15 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3487437B2 (en) * | 1992-12-29 | 2004-01-19 | ソニー株式会社 | Pulse width modulation circuit |
| CN101446843A (en) * | 2008-12-30 | 2009-06-03 | 北京中星微电子有限公司 | High-frequency clock generator, clock frequency conversion method, and chip |
| CN101509943A (en) * | 2008-12-25 | 2009-08-19 | 北京握奇数据***有限公司 | Phase detecting method and apparatus |
| CN101536311A (en) * | 2007-01-25 | 2009-09-16 | 夏普株式会社 | Pulse output circuit, display device driving circuit using the circuit, display device, and pulse output method |
| CN101694991A (en) * | 2009-10-22 | 2010-04-14 | 浙江大学 | Circuit for realizing synchronization of asynchronous pulse signals with random pulse width |
| CN202068389U (en) * | 2011-04-06 | 2011-12-07 | 中国科学院西安光学精密机械研究所 | Device for realizing short-time pulse signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5124573A (en) * | 1990-12-20 | 1992-06-23 | International Business Machines | Adjustable clock chopper/expander circuit |
-
2011
- 2011-04-06 CN CN201110085576.9A patent/CN102231627B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3487437B2 (en) * | 1992-12-29 | 2004-01-19 | ソニー株式会社 | Pulse width modulation circuit |
| CN101536311A (en) * | 2007-01-25 | 2009-09-16 | 夏普株式会社 | Pulse output circuit, display device driving circuit using the circuit, display device, and pulse output method |
| CN101509943A (en) * | 2008-12-25 | 2009-08-19 | 北京握奇数据***有限公司 | Phase detecting method and apparatus |
| CN101446843A (en) * | 2008-12-30 | 2009-06-03 | 北京中星微电子有限公司 | High-frequency clock generator, clock frequency conversion method, and chip |
| CN101694991A (en) * | 2009-10-22 | 2010-04-14 | 浙江大学 | Circuit for realizing synchronization of asynchronous pulse signals with random pulse width |
| CN202068389U (en) * | 2011-04-06 | 2011-12-07 | 中国科学院西安光学精密机械研究所 | Device for realizing short-time pulse signal |
Non-Patent Citations (7)
| Title |
|---|
| 《一种基于数字电路的纳秒级脉冲产生方法》;张涛等;《现代电子技术》;20060515;119-123 * |
| 《基于FPGA的高速可变周期脉冲发生器的设计与实现》;陈满;《国外电子元器件》;20070305;35-37 * |
| 《脉宽可调纳秒脉冲产生器》;王玲;《核电子学与探测技术》;20030520;243-245 * |
| 张孝飞等.《基于PFGA的脉冲发生器波形模块设计》.《长春工业大学学报(自然科学版)》.2011,第32卷(第3期),258-262. * |
| 张涛等.《一种基于数字电路的纳秒级脉冲产生方法》.《现代电子技术》.2006,119-123. |
| 王玲.《脉宽可调纳秒脉冲产生器》.《核电子学与探测技术》.2003,243-245. |
| 陈满.《基于FPGA的高速可变周期脉冲发生器的设计与实现》.《国外电子元器件》.2007,35-37. |
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