CN104901859A - AXI/PCIE bus converting device - Google Patents
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Abstract
The present invention discloses an AXI/PCIE bus converting device which is used for data communication between an AXI bus and a PCIE bus. The device includes: an AXI read channel module, an AXI write channel module, a transmission FIFO module, a reception FIFO module, a transmission control module, a reception control module, a Master module, a Slave module, a TX module and an RX module. Compared with the prior art, the device of the present invention can achieve data information interaction between two equipment nodes via the PCIE bus while rapidly and accurately carrying out the data communications between the AXI bus and the PCIE bus; moreover, the device has advantages of simple structure, low cost, and good compatibility.
Description
Technical field
The present invention relates to a kind of bus conversion device, particularly relate to a kind of AXI/PCIE bus conversion device, for realizing the data communication between AXI bus and PCIE bus.
Background technology
AXI is a new high performance agreement, is the most important part in the AMBA3.0 of AMBA company proposition, meets the demand of very-high performance and complicated system-on-chip designs.It is a kind of bus on chip towards high-performance, high bandwidth, low delay.Its main feature is address/control is be separated with data, supports the transfer of data do not lined up, and it is reading and writing data channel separation simultaneously, and supports significant transmission access and out of order access.
PCIE is bus and the interface standard of current main-stream, and this new standard replaces original PCI and AGP bus, becomes the interface standard of next generation computer equipment.PCIE bus adopts point-to-point serial communication mode, carries out transfer of data based on bag, and the computer interface of present main flow both provides PCIE interface.Many utilization systems with AXI interface directly can access PCIE device by this general line system controller.
For the data communication between two kinds of different agreement buses, bus conversion device (or claiming Bridge) can be passed through and realize.Existing AXI/PCIE bus conversion device is all the transmission only only completing protocol conversion, data.
Summary of the invention
Technical problem to be solved by this invention is to overcome prior art deficiency, a kind of AXI/PCIE bus conversion device is provided, quick and precisely to realize between AXI bus and PCIE bus while data communication, having that structure is simple, to realize cost low, and compatible good advantage.
The present invention is concrete by the following technical solutions:
A kind of AXI/PCIE bus conversion device, for realizing the data communication between AXI bus and PCIE bus, it is characterized in that, this device comprises: configuration module, AXI read channel module, AXI write access module, transmission fifo module, reception fifo module, transmission control module, reception control module, Master module, Slave module, TX module and RX module, wherein:
Described configuration module is connected with AXI bus, receives the operational order of self processor, is responsible for configuration DMA control register group, log-on data transmission operation;
Described AXI read channel module is connected with AXI bus, sends in fifo module for the data from AXI bus being sent to;
Described AXI write access module is connected with AXI bus, for the data received in fifo module are sent to AXI bus;
Described transmission fifo module is connected with AXI read channel module, and for the data of buffer memory from AXI bus, the clock frequency that the data of its buffer memory press PCIE bus end is removed;
Described reception fifo module is connected with AXI write access module, and for the data of buffer memory from PCIE bus, the clock frequency that the data of its buffer memory press AXI bus end is removed;
Described transmission control module is changed for completing AXI bus to the data bit width of PCIE bus, and controls the transmission from the data of AXI bus;
Described reception control module is changed for completing PCIE bus to the data bit width of AXI bus, and controls the reception from the data of PCIE bus;
Described Master module and transmission FIFO with send control module and be connected respectively, for the data, address information etc. that acquire from that end of AXI bus are assembled into message, pass to TX module;
Described Slave module is connected with RX module, for completing reception and the differentiation of various message, different disposal is carried out to read-write message and error message, for correct message, Master module is mail to after extracting relevant information and data, for error message, its control information is sent to Master module;
Described TX module is connected with Master module, is responsible for data to be sent to PCIE bus;
Described RX module is connected with Slave module, is responsible for receiving from the data of PCIE bus, and gives Slave module and resolve.
Preferably, send control module to complete AXI bus to the data bit width of PCIE bus in accordance with the following methods and change: send PCIE bus to by from every 4 data being connected into a 256bits into a spelling of the 64bits data of AXI bus.
Receive control module to complete PCIE bus to the data bit width of AXI bus in accordance with the following methods and change: the data data of the 256bits from PCIE bus being disassembled into 4 64bits send AXI bus to.
Preferably, the transmission control logic handling process of described Master module, specific as follows:
1) initialization, under present case, constantly monitoring sends request signal, and when sending request signal and being effective, horse back enters that next step is ready;
2) ready, whether now first Master module detects is the message being with data, if be not with data, then next step is the transmission of message packet header; If with the message of data, then the marking signal payload being provided with data payload is 1; If error message, the processing logic of error message will be followed; After completing aforesaid operations, next step is the transmission of message packet header;
3) message packet header transmission, now Master module sends a request to TX module and to send datagram sending request of head, after data message hair send, a feedback signal will be returned, after whole transmission control logic receives feedback signal, detect the value of payload, if payload is 0, then current message end of transmission, otherwise the data payload continuing message transmission;
4) data payload of message transmission, Master module sets up linking between TX module and corresponding transmission fifo module, and what TX module was continued reads that current message is remaining does not transmit data payload from transmission fifo module;
5) current data message end of transmission, after one-period, carries out the transmission of next data message.
Preferably, the reception control logic handling process of described Slave module, specific as follows:
1) initialization, when Slave module receives message, carries out further work message field (MFLD) at once and resolves inspection;
2) message header field is resolved and is checked, Slave module checks the field that in heading, each parses, if legal, then next step prepares to receive message, if illegally, then stops receiving message;
3) prepare to receive message, whether Slave module detection messages is with data, if be not with data, then comes back to initialization, terminates the reception of this message, if with data, then accepts message data; If the message received is with data, then data write in FIFO by Slave module; All data have all received, and receive logic is initialization again, and this message finishes receiving; If illegal message, then message is stopped to receive;
4) stop the reception of message, after terminating reception message, receive control logic initialization again, terminate the reception of this message.
Preferably, the message transmission processing flow process of described TX module, specific as follows:
1) initialization, TX module detects always and sends request signal, and when sending request signal and being effective, next step sends message packet header;
2) send message packet header, now TX module starts to send data, and information extraction from message packet header, whether confirmation message can be sent completely in one-period, if passable, then waits for feedback signal, if not all right, then continues the transmission of residue message;
3) continue the transmission of the remaining data message of current message, until current message is sent, wait for feedback signal;
4) TX module waits for the feedback signal that PCIE bus is disposed, once receive the feedback signal from PCIE bus, initialization, starts the transmission of new round message.
Preferably, the message of described RX module receives handling process, specific as follows:
1) initialization, whether now RX module continues detection has message to need to receive, once detect that message needs to receive, then starts to receive message packet header;
2) message packet header is received, now the header information of RX module to the data message received extracts, the length of the message that acquisition will receive, judge whether message has exception or mistake according to the information of header simultaneously, if message is normal and can receives in one-period, so whether detection messages terminates; If message is normal and can not receives in one-period, so continue the reception of the message do not finished receiving; If message is abnormal, so will stop receiving exception message;
3) receive the message remaining and do not receive, RX module continues the reception of the message that current message not yet receives, until receive, comes back to initialization;
4) stop receive exception message, the message received is invalid, can not transmission buffer in FIFO, but receive terminate after can provide one reception end signal;
5) message receives, now the end signal of RX module detection messages always, once the end signal of message be detected, flow process comes back to initialization.
Compared to existing technology, the present invention has following beneficial effect:
1, the present invention can realize bus protocol conversion, can realize again internal memory and directly access;
2, in the present invention with reception and send FIFO and can realize the conversion of clock zone, the effect controlling flow can be played again and prevent loss of data, this just can make work clock can the configuration of quite flexible, and also permission configuration work clock in existing technology, but also can be subject to the restriction of some other factors, the mode of operation of configuration is more limited and fixing.
Accompanying drawing explanation
Fig. 1 is the basic structure schematic diagram of AXI/PCIE bus conversion device of the present invention;
Fig. 2 is the flow path switch schematic diagram that AXI bus data is converted to PCIE bus data by AXI/PCIE bus conversion device of the present invention;
Fig. 3 is the flow path switch schematic diagram that PCIE bus data is converted to AXI bus data by AXI/PCIE bus conversion device of the present invention;
Fig. 4 is the state transition diagram that Master module sends state machine;
Fig. 5 is the state transition diagram of Slave module receive state machine;
Fig. 6 is the state transition diagram of TX module receive state machine;
Fig. 7 is the state transition diagram of RX module receive state machine;
Fig. 8 is reception, sends the control principle block diagram that fifo module is sent in control module docking sending and receiving;
Fig. 9 is the workflow diagram of configuration module.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in detail:
The equipment hung in AXI bus is divided into two kinds: Master equipment and Slave equipment, and Master equipment initiatively can initiate the transmission of data, and the reception that Slave equipment can only be passive is from the transfer of data of Master.Thinking of the present invention is using the overall Master equipment as AXI bus of AXI/PCIE bus conversion device, thus realizes the data communication between AXI bus and PCIE bus.
Fig. 1 shows the basic structure of AXI/PCIE bus conversion device of the present invention.As shown in Figure 1, AXI/PCIE bus conversion device (in figure in dotted line frame part) two ends connect the communication interface of AXI bus and PCIE bus respectively, and it comprises: configuration module, AXI read channel module, AXI write access module, send fifo module, receive fifo module, send control module, receive control module, Master module, Slave module, TX module and RX module; Wherein, AXI read channel module is the module be connected with AXI bus with AXI write access module, meets AXI standard, is responsible for the communication between AXI bus; Send fifo module and receive the fifo module buffer memory data from one side bus, send control module and receive control module for realizing the data bit width conversion between two kinds of buses, the transmission of control data simultaneously and reception; Master module is the nucleus module of bus conversion device transmission path, the data assembling sending PCIE bus to is become corresponding data message, send to TX module, thus be sent to PCIE bus from AXI bus; Slave module is the nucleus module of bus conversion device receiving path, resolves the packet that PCIE bus transmits, thus by data separating out, and by Master module, by data buffer storage to receiving in fifo module; Packet is mail to PCIE bus by TX module, and RX module receives the packet from PCIE bus.Concrete,
Configuration module is connected with AXI bus, receives the operational order of self processor, is responsible for configuration DMA control register group, log-on data transmission operation;
AXI read channel module is connected with AXI bus, is responsible for the data from AXI bus to be sent to send in FIFO.
AXI write access module is connected with AXI bus, is responsible for the data received in FIFO to be sent in AXI bus.
Send fifo module to be connected with AXI read channel, buffer memory is from the data of AXI bus, and the clock frequency that the data of its buffer memory press PCIE bus end is removed, achieves the transmission of data between two different bus clock zones.
Receive fifo module to be connected with AXI write access, buffer memory is from the data of PCIE bus, and the clock frequency that the data of its buffer memory press AXI bus end is removed, achieves the transmission of data between two different bus clock zones.
Send control module to complete AXI bus to the data bit width of PCIE bus and change, control the transmission of the data from AXI bus; Concrete data bit width conversion method is: send 4 data that are a spelling be connected into a 256bits every from the 64bits data of AXI bus to PCIE bus.
Receive control module to complete PCIE bus to the data bit width of AXI bus and change, control the reception of the data from PCIE bus; Concrete data bit width conversion method is: the data data of the 256bits from PCIE bus being disassembled into 4 64bits send AXI bus to
Master module and transmission fifo module with send control module and be connected, complete the assembling of the data message that will send.Before this, data and packet header separate.The information that will send message is assembled into heading, from transmission fifo module, extracts the current message data that will send according to header packet information, send to TX module.
Slave module is connected with RX module, mainly completes reception and the differentiation of various message, for the different disposal reading and writing message and error message, mails to Master module after extracting relevant information and data.
TX module is connected with Master module, is responsible for data to be sent to PCIE bus.According to difference request, the present transmission state of different length message, message controls its transmitting procedure, and transmission state is fed back to Master end, with from the stopping of data source header controls transfer and continuation, also carries out the large small end conversion of data simultaneously.
RX module is connected with Slave module, is responsible for receiving from the data of PCIE bus, and gives Slave module and resolve; It mainly comprises 3 functions: complete whole message and receive; Be separated packet header and data; Complete data from large end to the conversion of small end.The data of common read-write requests and control information pass toward Slave, and the control information of error message then passes toward Master.
Fig. 2 is showing data from AXI bus to the flow path switch of PCIE bus, specifically comprises the steps:
(1) by AXI read channel module, data are read out from AXI bus;
(2) the data temporal cache read out from AXI bus is sending in fifo module;
(3) Master module is according to the relevant information of current transmission data, encapsulation of data packet header, and takes out data from transmission fifo module, data packet head is become a packet completed with data assembling, is sent to TX module;
(4) by the connection of TX module, data are directly sent to PCIE bus, finally realize data from AXI bus to PCIE bus transmission.
Fig. 3 shows data from PCIE bus to the flow path switch of AXI bus, specifically comprises the steps:
(1) data pass toward RX module with the form of packet from PCIE bus;
(2) various messages RX module received by Slave module carry out deblocking and parsing;
(3) the data temporal cache parsed from message is in reception FIFO;
(4) by AXI write access, the data received in FIFO are sent in AXI bus, finally complete the communication between PCIE bus to AXI bus.
In the present invention, Master module, Slave module, TX module and RX module preferably adopt the mode of state machine to realize.Be below specific implementation:
Be provided with a transmission control logic in Master module, as shown in Figure 4, concrete steps are as follows for the state transition diagram of the transmission state machine adopted:
(1) initialization (Idle state), under present case, constantly monitoring sends request signal, and when sending request signal and being effective, horse back enters that next step is ready;
(2) ready (Prep state), whether now first Master module detects is the message being with data, if be not with data, then next step is the transmission of message packet header; If with the message of data, then the marking signal payload being provided with data payload is 1; If error message, the processing logic of error message will be followed; After completing aforesaid operations, next step is the transmission of message packet header;
(3) message packet header transmission (Req state), now Master module sends a request to TX module and to send datagram sending request of head, after data message hair send, a feedback signal will be returned, after whole transmission control logic receives feedback signal, detect the value of payload, if payload is 0, then current message end of transmission, otherwise the data payload continuing message transmission;
(4) data payload (Trans state) of message transmission, Master module sets up linking between TX module and corresponding transmission fifo module, and what TX module was continued reads that current message is remaining does not transmit data payload from transmission fifo module;
(5) End state, current data message end of transmission, after one-period, carries out the transmission of next data message.
Be provided with a reception control logic handling process in Slave module, as shown in Figure 5, concrete steps are as follows for the state transition diagram of its receive state machine adopted:
(1) initialization (Idle state), when Slave module receives message, carries out further work message field (MFLD) at once and resolves inspection;
(2) message header field is resolved and is checked (Req state), and Slave module checks the field that in heading, each parses, if legal, then next step prepares to receive message, if illegally, then stops receiving message;
(3) prepare to receive message (Ack state), whether Slave module detection messages is with data, if be not with data, then comes back to initialization, terminates the reception of this message, if with data, then accepts message data; If the message received is with data, then data write in FIFO by Slave module; All data have all received, and receive logic is initialization again, and this message finishes receiving; If illegal message, then message is stopped to receive;
(4) stop the reception (Abort state) of message, after terminating reception message, receive control logic initialization again, terminate the reception of this message.
Be provided with message transmission processing flow process in TX module, as shown in Figure 6, concrete steps are as follows for the state transition diagram of the transmission state machine that it adopts:
(1) initialization (Idle state), TX module detects always and sends request signal, and when sending request signal and being effective, next step sends message packet header;
(2) send message packet header (Header state), now TX module starts to send data, and information extraction from message packet header, whether confirmation message can be sent completely in one-period, if passable, then waits for feedback signal, if not all right, then continue the transmission of residue message;
(3) Trans state, continues the transmission of the remaining data message of current message, until current message is sent, waits for feedback signal;
(4) Wait state, TX module waits for the feedback signal that PCIE bus is disposed, once receive the feedback signal from PCIE bus, initialization, starts the transmission of new round message.
RX module comprises message and receives handling process, and as shown in Figure 7, concrete steps are as follows for the state transition diagram of the transmission state machine that it adopts:
(1) initialization (Idle state), whether now RX module continues detection has message to need to receive, once detect that message needs to receive, then starts to receive message packet header;
(2) message packet header (Req state) is received, now the header information of RX module to the data message received extracts, the length of the message that acquisition will receive, judge whether message has exception or mistake according to the information of header simultaneously, if message is normal and can receives in one-period, so whether detection messages terminates; If message is normal and can not receives in one-period, so continue the reception of the message do not finished receiving; If message is abnormal, so will stop receiving exception message;
(3) receive the message (Trans state) remaining and do not receive, RX module continues the reception of the message that current message not yet receives, until receive, comes back to initialization;
(4) stop receive exception message (Abort state), the message received is invalid, can not transmission buffer in FIFO, but receive terminate after can provide one reception end signal;
(5) message receives (Turn state), now the end signal of RX module detection messages always, once the end signal of message be detected, flow process comes back to initialization.
Fig. 8 shows reception, sends the control principle that fifo module is sent in control module docking sending and receiving.Wherein realize data buffer storage with 2 FIFO respectively for sendaisle and receive path, asynchronous FIFO is the data that transmit of buffer memory one side interface before this, and then opposite side interface reads the data of buffer memory from FIFO according to the clock zone of oneself.The data bit width of that side of AXI bus interface is 64bits, but the data bit width of that side of PCIE bus is 256bits, and for this reason, data are sent to the conversion that other side needs data bit width in side.For transmission path, data from AXI read channel, data bit width is 64bits, and before data are sent into transmission FIFO, data bit width must be 256 bits by 64 bits switch.For receiving path, data from PCIE bus, after from reception, FIFO goes out data with the clock of AXI, data bit width is could send into AXI write access after 64 bits by 256 bits switch.One end of transmitting-receiving buffer memory FIFO be the clock of PCIE, opposite side be the clock-driven of AXI.Data cache module asynchronous FIFO is just responsible for the work clock between conversion two kinds of buses, and data bit width conversion has special data bit width conversion logic, namely send control logic and receive control logic, this ensure that the logic of design is reasonable, orderliness is clear, realizes simple.
Fig. 9 shows the main working process of configuration module.Configuration module is connected from interface with AXI, receives the operational order of self processor, is responsible for groups of configuration registers, log-on data transmission operation.Processor initiates read-write requests order by AXI bus, if read request, then configures read register group, log-on data read operation; If write request, then configurable write request register group, log-on data write operation.
Claims (7)
1. an AXI/PCIE bus conversion device, for realizing the data communication between AXI bus and PCIE bus, it is characterized in that, this device comprises: configuration module, AXI read channel module, AXI write access module, transmission fifo module, reception fifo module, transmission control module, reception control module, Master module, Slave module, TX module and RX module, wherein:
Described configuration module is connected with AXI bus, receives the operational order of self processor, is responsible for configuration DMA control register group, log-on data transmission operation;
Described AXI read channel module is connected with AXI bus, sends in fifo module for the data from AXI bus being sent to;
Described AXI write access module is connected with AXI bus, for the data received in fifo module are sent to AXI bus;
Described transmission fifo module is connected with AXI read channel module, and for the data of buffer memory from AXI bus, the clock frequency that the data of its buffer memory press PCIE bus end is removed;
Described reception fifo module is connected with AXI write access module, and for the data of buffer memory from PCIE bus, the clock frequency that the data of its buffer memory press AXI bus end is removed;
Described transmission control module is changed for completing AXI bus to the data bit width of PCIE bus, and controls the transmission from the data of AXI bus;
Described reception control module is changed for completing PCIE bus to the data bit width of AXI bus, and controls the reception from the data of PCIE bus;
Described Master module and transmission FIFO with send control module and be connected respectively, for the data obtained from AXI bus end, address information are assembled into message, pass to TX module;
Described Slave module is connected with RX module, for completing reception and the differentiation of various message, different disposal is carried out to read-write message and error message, for correct message, Master module is mail to after extracting relevant information and data, for error message, its control information is sent to Master module;
Described TX module is connected with Master module, is responsible for data to be sent to PCIE bus;
Described RX module is connected with Slave module, is responsible for receiving from the data of PCIE bus, and gives Slave module and resolve.
2. AXI/PCIE bus conversion device as claimed in claim 1, it is characterized in that, send control module and complete AXI bus to the data bit width of PCIE bus in accordance with the following methods and change: send PCIE bus to by from every 4 data being connected into a 256bits into a spelling of the 64bits data of AXI bus.
3. AXI/PCIE bus conversion device as claimed in claim 1, it is characterized in that, receive control module and complete PCIE bus to the data bit width of AXI bus in accordance with the following methods and change: the data data of the 256bits from PCIE bus being disassembled into 4 64bits send AXI bus to.
4. AXI/PCIE bus conversion device as claimed in claim 1, is characterized in that, the transmission control logic handling process of described Master module, specific as follows:
1) initialization, under present case, constantly monitoring sends request signal, when sending request signal and being effective, enters that next step is ready;
2) ready, whether now first Master module detects is the message being with data, if be not with data, then next step is the transmission of message packet header; If with the message of data, then the marking signal payload being provided with data payload is 1; If error message, the processing logic of error message will be followed; After completing aforesaid operations, next step is the transmission of message packet header;
3) message packet header transmission, now Master module sends a request to TX module and to send datagram sending request of head, after data message hair send, a feedback signal will be returned, after whole transmission control logic receives feedback signal, detect the value of payload, if payload is 0, then current message end of transmission, otherwise the data payload continuing message transmission;
4) data payload of message transmission, Master module sets up linking between TX module and corresponding transmission fifo module, and what TX module was continued reads that current message is remaining does not transmit data payload from transmission fifo module;
5) current data message end of transmission, after one-period, carries out the transmission of next data message.
5. AXI/PCIE bus conversion device as claimed in claim 1, is characterized in that, the reception control logic handling process of described Slave module, specific as follows:
1) initialization, when Slave module receives message, carries out further work message field (MFLD) at once and resolves inspection;
2) message header field is resolved and is checked, Slave module checks the field that in heading, each parses, if legal, then next step prepares to receive message, if illegally, then stops receiving message;
3) prepare to receive message, whether Slave module detection messages is with data, if be not with data, then comes back to initialization, terminates the reception of this message, if with data, then accepts message data; If the message received is with data, then data write in FIFO by Slave module; All data have all received, and receive logic is initialization again, and this message finishes receiving; If illegal message, then message is stopped to receive;
4) stop the reception of message, after terminating reception message, receive control logic initialization again, terminate the reception of this message.
6. AXI/PCIE bus conversion device as claimed in claim 1, is characterized in that, the message transmission processing flow process of described TX module, specific as follows:
1) initialization, TX module detects always and sends request signal, and when sending request signal and being effective, next step sends message packet header;
2) send message packet header, now TX module starts to send data, and information extraction from message packet header, whether confirmation message can be sent completely in one-period, if passable, then waits for feedback signal, if not all right, then continues the transmission of residue message;
3) continue the transmission of the remaining data message of current message, until current message is sent, wait for feedback signal;
4) TX module waits for the feedback signal that PCIE bus is disposed, once receive the feedback signal from PCIE bus, initialization, starts the transmission of new round message.
7. AXI/PCIE bus conversion device as claimed in claim 1, is characterized in that, the reception handling process of described RX module, specific as follows:
1) initialization, whether now RX module continues detection has message to need to receive, once detect that message needs to receive, then starts to receive message packet header;
2) message packet header is received, now the header information of RX module to the data message received extracts, the length of the message that acquisition will receive, judge whether message has exception or mistake according to the information of header simultaneously, if message is normal and can receives in one-period, so whether detection messages terminates; If message is normal and can not receives in one-period, so continue the reception of the message do not finished receiving; If message is abnormal, so will stop receiving exception message;
3) receive the message remaining and do not receive, RX module continues the reception of the message that current message not yet receives, until receive, comes back to initialization;
4) stop receive exception message, the message received is invalid, can not transmission buffer in FIFO, but receive terminate after can provide one reception end signal;
5) message receives, now the end signal of RX module detection messages always, once the end signal of message be detected, flow process comes back to initialization.
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| CN111339012A (en) * | 2020-02-20 | 2020-06-26 | 广东博智林机器人有限公司 | Processor system bus structure and system |
| WO2021056632A1 (en) * | 2019-09-24 | 2021-04-01 | 山东华芯半导体有限公司 | Host device data transmission extension method based on axi bus |
| CN113051212A (en) * | 2021-03-02 | 2021-06-29 | 长沙景嘉微电子股份有限公司 | Graphics processor, data transmission method, data transmission device, electronic device, and storage medium |
| CN113473648A (en) * | 2021-06-29 | 2021-10-01 | 南京濠暻通讯科技有限公司 | Data transmission method between RMII and 10G interfaces in 5G base station RU |
| CN115328827A (en) * | 2022-10-14 | 2022-11-11 | 北京航天驭星科技有限公司 | PCIE (peripheral component interface express) -based storage system and method and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103530216A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE verification method based on UVM |
| US20140089553A1 (en) * | 2012-09-24 | 2014-03-27 | Broadcom Corporation | Interface between a host and a peripheral device |
| CN103714034A (en) * | 2013-12-26 | 2014-04-09 | 中国船舶重工集团公司第七0九研究所 | SOC applied to PC system |
| CN104281548A (en) * | 2013-07-03 | 2015-01-14 | 炬芯（珠海）科技有限公司 | Method, device and system for data transmission based on AXI bus |
-
2015
- 2015-06-11 CN CN201510320857.6A patent/CN104901859A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140089553A1 (en) * | 2012-09-24 | 2014-03-27 | Broadcom Corporation | Interface between a host and a peripheral device |
| CN104281548A (en) * | 2013-07-03 | 2015-01-14 | 炬芯（珠海）科技有限公司 | Method, device and system for data transmission based on AXI bus |
| CN103530216A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE verification method based on UVM |
| CN103714034A (en) * | 2013-12-26 | 2014-04-09 | 中国船舶重工集团公司第七0九研究所 | SOC applied to PC system |
Non-Patent Citations (1)
| Title |
|---|
| 张亮 等: "PCIe-AXI协议转换设计与实现", 《第十八届计算机工程与工艺年会暨第四届微处理器技术论坛论文集》 * |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017107528A1 (en) * | 2015-12-21 | 2017-06-29 | 深圳市中兴微电子技术有限公司 | Multi-security boot chip and startup method thereof and storage medium |
| CN107783927A (en) * | 2016-08-30 | 2018-03-09 | 安凯(广州)微电子技术有限公司 | For connecting the circuit conversion system and method for AXI interfaces and DMA interface |
| CN107783927B (en) * | 2016-08-30 | 2020-11-20 | 安凯(广州)微电子技术有限公司 | Circuit conversion system and method for connecting AXI interface and DMA interface |
| CN108664335A (en) * | 2017-04-01 | 2018-10-16 | 北京忆芯科技有限公司 | The method and apparatus of queue communication is carried out by agency |
| CN108345555B (en) * | 2018-03-13 | 2021-10-08 | 算丰科技（北京）有限公司 | Interface bridge circuit based on high-speed serial communication and method thereof |
| CN108345555A (en) * | 2018-03-13 | 2018-07-31 | 算丰科技（北京）有限公司 | Interface bridgt circuit based on high-speed serial communication and its method |
| CN108958800A (en) * | 2018-06-15 | 2018-12-07 | 中国电子科技集团公司第五十二研究所 | A kind of DDR management control system accelerated based on FPGA hardware |
| CN109933547A (en) * | 2019-01-29 | 2019-06-25 | 山东华芯半导体有限公司 | The passive accelerator of RAID and accelerated method in a kind of SSD master control |
| WO2021056632A1 (en) * | 2019-09-24 | 2021-04-01 | 山东华芯半导体有限公司 | Host device data transmission extension method based on axi bus |
| CN111339012A (en) * | 2020-02-20 | 2020-06-26 | 广东博智林机器人有限公司 | Processor system bus structure and system |
| CN113051212A (en) * | 2021-03-02 | 2021-06-29 | 长沙景嘉微电子股份有限公司 | Graphics processor, data transmission method, data transmission device, electronic device, and storage medium |
| CN113051212B (en) * | 2021-03-02 | 2023-12-05 | 长沙景嘉微电子股份有限公司 | Graphics processor, data transmission method, data transmission device, electronic equipment and storage medium |
| CN113473648A (en) * | 2021-06-29 | 2021-10-01 | 南京濠暻通讯科技有限公司 | Data transmission method between RMII and 10G interfaces in 5G base station RU |
| CN115328827A (en) * | 2022-10-14 | 2022-11-11 | 北京航天驭星科技有限公司 | PCIE (peripheral component interface express) -based storage system and method and electronic equipment |
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