CN104900657A - Array substrate and making method thereof, display panel, and display device - Google Patents
Array substrate and making method thereof, display panel, and display device Download PDFInfo
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- CN104900657A CN104900657A CN201510303491.1A CN201510303491A CN104900657A CN 104900657 A CN104900657 A CN 104900657A CN 201510303491 A CN201510303491 A CN 201510303491A CN 104900657 A CN104900657 A CN 104900657A
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- film transistor
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- Thin Film Transistor (AREA)
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Abstract
The invention discloses an array substrate and a making method thereof, a display panel, and a display device. The array substrate includes a substrate and a thin film transistor arranged on the substrate. The thin film transistor includes an active layer. The array substrate further includes a shading layer which is arranged above the active layer of the thin film transistor, and the shading layer at least covers a channel region of the thin film transistor. Illumination of light on the active layer is reduced, leakage current is reduced, the occurrence of crosstalk, voltage flicker, residual image and other phenomena is reduced, and the display effect is improved.
Description
Technical field
The present invention relates to Display Technique field, be specifically related to a kind of array base palte, a kind ofly comprise the display floater of this array base palte and a kind of display unit comprising this display floater.
Background technology
Liquid crystal panel comprises array base palte and to box substrate, array base palte is provided with grid line and data wire, grid line and data wire limit multiple pixel cell, thin-film transistor is provided with in each pixel cell, the grid of thin-film transistor is connected with corresponding grid line, when the voltage on grid line reaches cut-in voltage, the source electrode of thin-film transistor and drain electrode conducting, thus the data voltage on data wire is inputed to pixel electrode.But the irradiation of active layer 11 pairs of light of thin-film transistor is more responsive.As shown in Figure 1, when the illumination (e.g., surround lighting) of side shown in arrow exposes to active layer 11, the leakage current of thin-film transistor can be caused to be affected, thus produce the phenomenon such as crosstalk, voltage flicker, and then have influence on the quality of display frame.
Summary of the invention
The object of the present invention is to provide a kind of array base palte and preparation method thereof, a kind ofly comprise the display floater of this array base palte and a kind of display unit comprising this display floater, to reduce the impact of illumination on display frame.
In order to above-mentioned purpose, the invention provides a kind of array base palte, the thin-film transistor comprising substrate and arrange over the substrate, described thin-film transistor includes active layer, described array base palte also comprises the light shield layer above the active layer being arranged on described thin-film transistor, and described light shield layer at least covers the channel region of described thin-film transistor.
Preferably, described thin-film transistor comprises source electrode and drain electrode, and described light shield layer is arranged on the top of described source electrode and drain electrode, and described array base palte also comprises the chock insulator matter be arranged on described light shield layer.
Preferably, described light shield layer and described chock insulator matter are integrally formed.
Preferably, described light shield layer comprises lighttight photoresist layer.
Preferably, described array base palte also comprises the passivation layer be arranged on above described thin-film transistor, and described light shield layer is arranged on described passivation layer.
Correspondingly, the present invention also provides a kind of manufacture method of array base palte, comprising:
Form the active layer of thin-film transistor;
Above the active layer of described thin-film transistor, form light shield layer, described light shield layer at least covers the channel region of described thin-film transistor.
Preferably, described manufacture method also comprises: formed and comprise the source electrode of thin-film transistor and the figure of drain electrode; The described step forming light shield layer above the active layer of thin-film transistor is carried out after described formation comprises the step of the source electrode of thin-film transistor and the figure of drain electrode, and described manufacture method also comprises:
Form the figure comprising chock insulator matter, described chock insulator matter is positioned at the top of described light shield layer.
Preferably, above the active layer of thin-film transistor, form the step that the step of light shield layer and described formation comprises the figure of chock insulator matter synchronously formed, the step of described synchronous formation comprises:
Form lighttight photoresist layer;
Intermediate tone mask plate is utilized to expose described photoresist layer and develop, retain with the part making the photoresist layer after developing be positioned at presumptive area, other parts are removed, described presumptive area corresponds to the position of described light shield layer, and, described presumptive area comprises middle sub-field and is positioned at the edge subregion around this middle sub-field, the thickness being positioned at the photoresist layer of described middle sub-field is greater than the thickness of the photoresist layer being positioned at described edge subregion, and described middle sub-field corresponds to the position of described chock insulator matter.
Preferably, described photoresist layer is negative photo glue-line, the transparent area of described intermediate tone mask plate corresponds to described middle sub-field, the semi-opaque region of described intermediate tone mask plate corresponds to described edge subregion, and the light tight region of described intermediate tone mask plate corresponds to the region beyond described presumptive area.
Preferably, described manufacture method is also included in and carries out between the step of the active layer of described formation thin-film transistor and the described step forming light shield layer above the active layer of thin-film transistor:
Form passivation layer.
Correspondingly, the present invention also provides a kind of display floater, described display floater comprise array base palte and with this array base palte be oppositely arranged to box substrate, described array base palte is above-mentioned array base palte provided by the invention, describedly comprise black matrix to box substrate, the projection over the substrate of described black matrix covers the projection over the substrate of described light shield layer.
Correspondingly, the present invention also provides a kind of display unit, and described display unit comprises above-mentioned display floater provided by the invention.
In the present invention, because light shield layer at least covers the channel region of described thin-film transistor, the channel region that side direction light enters thin-film transistor can be reduced, reduce leakage current, thus the phenomenon such as crosstalk, voltage flicker can be reduced, and then improve display quality; In addition, chock insulator matter and barrier bed can synchronously be formed, and without the need to making the step forming separately chock insulator matter in the process of box substrate, thus simplify manufacture craft on the whole.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 is array base-plate structure schematic diagram of the prior art;
Fig. 2 is the array base-plate structure schematic diagram in the embodiment in the present invention;
Fig. 3 is the schematic diagram forming photoresist layer;
Fig. 4 is the schematic diagram utilizing intermediate tone mask plate to expose photoresist layer.
Wherein, Reference numeral is; 10, substrate; 11, active layer; 12, light shield layer; 13, chock insulator matter; 14, passivation layer; 15, pixel electrode; 16, grid; 17, source electrode; 18, drain; 21, photoresist layer; 22, intermediate tone mask plate; A, light tight district; B, semi-opaque region; C, transparent area.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the present invention, is not limited to the present invention.
As first aspect of the present invention, a kind of array base palte is provided, as shown in Figure 2, the thin-film transistor comprising substrate 10 and arrange over the substrate, described thin-film transistor includes active layer 11, described array base palte also comprises the light shield layer 12 above the active layer being arranged on described thin-film transistor, and light shield layer 12 at least covers the channel region of described thin-film transistor.
In the present invention, due to the channel region of light shield layer 12 at least cover film transistor, the channel region that side direction light enters thin-film transistor can be reduced, therefore when source electrode 17 and drain electrode 18 conducting of thin-film transistor, leakage current can be reduced, thus decrease the generation of the crosstalk of display unit, voltage flicker, afterimage phenomenon, and then improve the display quality of display unit, the useful life of prolong showing device.
The present invention is particularly useful for bottom gate thin film transistor, namely active layer 11 is arranged on the top of grid 16, grid 16 can block the light of backlight, reduce the light of backlight and be irradiated to channel region by below active layer, the light shield layer 12 above active layer 11 can block the surround lighting of side direction or backlight through to the some light exposing to channel region after the reflection of box substrate.
Comprising array base palte and in the display floater of box substrate, to box substrate being provided with black matrix, for blocking thin-film transistor.Thin-film transistor in the present invention comprises source electrode 17 and drain electrode 18, source electrode 17, drain electrode 18 and active layer 11 orthographic projection over the substrate 10 can exceed light shield layer 12 orthographic projection over the substrate 10, block while blocking thin-film transistor to make black matrix to light shield layer.
Further, as shown in Figure 2, light shield layer 12 is arranged on above source electrode 17 and drain electrode 18, and described array base palte can also comprise the chock insulator matter 13 be arranged on light shield layer 12.When described array base palte is with when becoming display floater to box substrate to box-like, chock insulator matter 13 can play the effect to supporting box substrate, thick to maintain certain box.Be understandable that, the orthographic projection of chock insulator matter 13 on substrate is no more than barrier bed 12 orthographic projection over the substrate 10.
Preferably, in the present invention, light shield layer 12 and chock insulator matter 13 are integrally formed, and therefore, in the manufacturing process of array base palte, do not need the step forming separately chock insulator matter 13, thus simplify manufacture craft.
The shape of the present invention to chock insulator matter 13 is not construed as limiting, such as, chock insulator matter 13 is cylindricality, namely the top surface area of chock insulator matter 13 is equal with base area, or as shown in Figure 2, the cross-sectional area of chock insulator matter 13 is increased to direction, bottom gradually by the top of chock insulator matter 13, thus improves the stability of the support of chock insulator matter 13.Described " top of chock insulator matter 13 " refers to one end away from substrate 10 of chock insulator matter 13, and " bottom of chock insulator matter 13 " refers to one end of the close substrate 10 of chock insulator matter 13.
Preferably, light shield layer 12 comprises lighttight photoresist layer, and therefore, when making light shield layer 12, after only needing to form photoresist layer, then expose photoresist layer and develop, and not needing other steps such as etching, manufacture craft is simpler.
Further, as shown in Figure 2, described array base palte also comprises the passivation layer 14 be arranged on above described thin-film transistor, and light shield layer 12 is arranged on passivation layer 14.Position passivation layer 14 corresponding to the drain electrode of thin-film transistor is provided with via hole, and array base palte also comprises the pixel electrode 15 be arranged on passivation layer 14, and pixel electrode 15 is connected with the drain electrode of thin-film transistor by described via hole.
As second aspect of the present invention, a kind of manufacture method of array base palte is provided, comprises:
The active layer 11 of S10, formation thin-film transistor;
S20, above the active layer of described thin-film transistor, form light shield layer, described light shield layer at least covers the channel region of described thin-film transistor.
Particularly, can comprise before step S10: form grid metal level, lithography patterning process is utilized to form the figure comprising grid and grid line, that is: on grid metal level, form photoresist layer, photoresist layer is exposed and develops, to retain the photoresist of grid and grid line position, the photoresist of other positions is removed, again the grid metal layer part not covering photoresist is etched, finally remove remaining photoresist layer, form the figure comprising grid and grid line.The substrate being formed with grid forms gate insulator.Step S10 can comprise: form semiconductor material layer, utilizes lithography patterning process to form the figure including active layer.
Further, described manufacture method also comprises: S15, formation comprise the source electrode of thin-film transistor and the figure of drain electrode, and described source electrode, described drain electrode and the orthographic projection over the substrate of described active layer can exceed the orthographic projection over the substrate of described light shield layer.The concrete steps forming source electrode and drain electrode are similar with the step forming grid, photoetching composition can be adopted to be formed, repeat no more here, and wherein, the data line synchronization of source electrode and array base palte is formed.
In the present invention, step S20 carries out after the step s 15, and described manufacture method also comprises: S30, formed and comprise the figure of chock insulator matter, and described chock insulator matter is positioned at the top of described light shield layer.
In order to simplify manufacture craft, described step S20 and step S30 is synchronously formed, and the synchronous step formed comprises:
Form lighttight photoresist layer 21, as shown in Figure 3;
Intermediate tone mask board to explosure is utilized to expose described photoresist layer and develop, retain with the part making the photoresist layer after developing be positioned at presumptive area, other parts are removed, described presumptive area corresponds to the position of described light shield layer, and, described presumptive area comprises middle sub-field and is positioned at the edge subregion around this middle sub-field, the thickness being positioned at the photoresist layer of described middle sub-field is greater than the thickness of the photoresist layer being positioned at described edge subregion, and described middle sub-field corresponds to the position of described chock insulator matter.
Wherein, described photoresist layer is negative photo glue-line, as shown in Figure 4, the transparent area C of intermediate tone mask plate 22 corresponds to described middle sub-field, the semi-opaque region B of intermediate tone mask plate 22 corresponds to described edge subregion, and the light tight district A of intermediate tone mask plate 22 corresponds to the region beyond described presumptive area.Thus after exposure, be positioned at the photoresist sex change of middle sub-field, be positioned at the photoresist partial denaturation of edge subregion, the photoresist being positioned at the region beyond presumptive area is unchanged, thus after making development, the photoresist being positioned at zone line retains completely, forms described chock insulator matter; The photoresist part being positioned at edge subregion is removed a part, is formed as light shield layer; The photoresist being positioned at the region beyond presumptive area is dissolved in developer solution completely and is removed.
Certainly, described photoresist layer also can be positive photoresist, and at this moment, the transparent area of intermediate tone mask plate corresponds to the region beyond described presumptive area, and semi-opaque region corresponds to described edge subregion, and light tight district corresponds to described middle sub-field.
Further, described manufacture method is also included in and carries out between described step S10 and step S20:
Form passivation layer 14.Passivation layer 14 is arranged on above source electrode 17 and drain electrode 18, light shield layer 12 and chock insulator matter 13 are arranged on described passivation layer, thus after making to form multiple chock insulator matter, the simple height of mode to chock insulator matter such as polishing can be utilized to adjust, with the height making multiple chock insulator matter reach unified.
After formation passivation layer 14, on passivation layer 14, via hole can be formed by lithography patterning process, then on the passivation layer being formed with via hole, form pixel electrode 15, be connected with the drain electrode of thin-film transistor by described via hole to make pixel electrode 15.
As the 3rd aspect of the present invention, a kind of display floater is provided, described display floater comprise array base palte and with this array base palte be oppositely arranged to box substrate, described array base palte is above-mentioned array base palte provided by the invention, describedly comprise black matrix to box substrate, the projection over the substrate of described black matrix covers the projection over the substrate of described light shield layer.Because the light shield layer arranged in array base palte of the present invention can reduce the impact of light on thin-film transistor, reduce leakage current, thus the phenomenon such as crosstalk, voltage flicker can be reduced, and then improve display quality; In addition, chock insulator matter and barrier bed can synchronously be formed, and without the need to making the step forming separately chock insulator matter in the process of box substrate, thus simplify manufacture craft on the whole.
As the 4th aspect of the present invention, provide a kind of display unit, the above-mentioned display floater of described display unit.
Because arranging of light shield layer can reduce the phenomenon such as crosstalk, voltage flicker, make the display effect of display floater better, thus improve display unit display quality, the useful life of prolong showing device.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (12)
1. an array base palte, the thin-film transistor comprising substrate and arrange over the substrate, described thin-film transistor includes active layer, it is characterized in that, described array base palte also comprises the light shield layer above the active layer being arranged on described thin-film transistor, and described light shield layer at least covers the channel region of described thin-film transistor.
2. array base palte according to claim 1, is characterized in that, described thin-film transistor comprises source electrode and drain electrode, and described light shield layer is arranged on the top of described source electrode and drain electrode, and described array base palte also comprises the chock insulator matter be arranged on described light shield layer.
3. array base palte according to claim 2, is characterized in that, described light shield layer and described chock insulator matter are integrally formed.
4. array base palte as claimed in any of claims 1 to 3, is characterized in that, described light shield layer comprises lighttight photoresist layer.
5. array base palte as claimed in any of claims 1 to 3, is characterized in that, described array base palte also comprises the passivation layer be arranged on above described thin-film transistor, and described light shield layer is arranged on described passivation layer.
6. a manufacture method for array base palte, is characterized in that, comprising:
Form the active layer of thin-film transistor;
Above the active layer of described thin-film transistor, form light shield layer, described light shield layer at least covers the channel region of described thin-film transistor.
7. manufacture method according to claim 6, is characterized in that, described manufacture method also comprises: formed and comprise the source electrode of thin-film transistor and the figure of drain electrode; The described step forming light shield layer above the active layer of thin-film transistor is carried out after described formation comprises the step of the source electrode of thin-film transistor and the figure of drain electrode, and described manufacture method also comprises:
Form the figure comprising chock insulator matter, described chock insulator matter is positioned at the top of described light shield layer.
8. manufacture method according to claim 7, is characterized in that, described above the active layer of thin-film transistor, form light shield layer step and the described formation step that comprises the figure of chock insulator matter synchronously formed, the step of described synchronous formation comprises:
Form lighttight photoresist layer;
Intermediate tone mask plate is utilized to expose described photoresist layer and develop, retain with the part making the photoresist layer after developing be positioned at presumptive area, other parts are removed, described presumptive area corresponds to the position of described light shield layer, and, described presumptive area comprises middle sub-field and is positioned at the edge subregion around this middle sub-field, the thickness being positioned at the photoresist layer of described middle sub-field is greater than the thickness of the photoresist layer being positioned at described edge subregion, and described middle sub-field corresponds to the position of described chock insulator matter.
9. manufacture method according to claim 8, it is characterized in that, described photoresist layer is negative photo glue-line, the transparent area of described intermediate tone mask plate corresponds to described middle sub-field, the semi-opaque region of described intermediate tone mask plate corresponds to described edge subregion, and the light tight region of described intermediate tone mask plate corresponds to the region beyond described presumptive area.
10. according to the manufacture method in claim 6 to 9 described in any one, it is characterized in that, described manufacture method is also included in carries out between the step of the active layer of described formation thin-film transistor and the described step forming light shield layer above the active layer of thin-film transistor:
Form passivation layer.
11. 1 kinds of display floaters, described display floater comprise array base palte and with this array base palte be oppositely arranged to box substrate, it is characterized in that, described array base palte is the array base palte in claim 1 to 5 described in any one, describedly comprise black matrix to box substrate, the projection over the substrate of described black matrix covers the projection over the substrate of described light shield layer.
12. 1 kinds of display unit, is characterized in that, described display unit comprises display floater according to claim 11.
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| CN201510303491.1A CN104900657A (en) | 2015-06-04 | 2015-06-04 | Array substrate and making method thereof, display panel, and display device |
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| CN201510303491.1A CN104900657A (en) | 2015-06-04 | 2015-06-04 | Array substrate and making method thereof, display panel, and display device |
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Cited By (7)
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| CN105633015A (en) * | 2016-03-09 | 2016-06-01 | 合肥京东方显示技术有限公司 | Manufacturing method of array substrate, array substrate and display device |
| CN106054480A (en) * | 2016-08-04 | 2016-10-26 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and device |
| CN106125430A (en) * | 2016-08-26 | 2016-11-16 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, display floater and array base palte |
| CN106711153A (en) * | 2017-01-06 | 2017-05-24 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display panel |
| CN111223878A (en) * | 2020-01-09 | 2020-06-02 | Tcl华星光电技术有限公司 | Array substrate, display panel and liquid crystal display device |
| CN111834465A (en) * | 2019-12-09 | 2020-10-27 | 云谷（固安）科技有限公司 | Array substrate, display panel and display device |
| CN112488086A (en) * | 2020-12-29 | 2021-03-12 | 厦门天马微电子有限公司 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105633015A (en) * | 2016-03-09 | 2016-06-01 | 合肥京东方显示技术有限公司 | Manufacturing method of array substrate, array substrate and display device |
| CN105633015B (en) * | 2016-03-09 | 2018-04-17 | 合肥京东方显示技术有限公司 | A kind of manufacture method of array base palte, array base palte and display device |
| US10090338B2 (en) | 2016-03-09 | 2018-10-02 | Boe Technology Group Co., Ltd. | Method for manufacturing array substrate, array substrate and display device |
| CN106054480A (en) * | 2016-08-04 | 2016-10-26 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and device |
| CN106125430A (en) * | 2016-08-26 | 2016-11-16 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, display floater and array base palte |
| CN106711153A (en) * | 2017-01-06 | 2017-05-24 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display panel |
| CN111834465A (en) * | 2019-12-09 | 2020-10-27 | 云谷（固安）科技有限公司 | Array substrate, display panel and display device |
| CN111223878A (en) * | 2020-01-09 | 2020-06-02 | Tcl华星光电技术有限公司 | Array substrate, display panel and liquid crystal display device |
| CN111223878B (en) * | 2020-01-09 | 2023-01-10 | Tcl华星光电技术有限公司 | Array substrate, display panel and liquid crystal display device |
| CN112488086A (en) * | 2020-12-29 | 2021-03-12 | 厦门天马微电子有限公司 | Display panel and display device |
| CN112488086B (en) * | 2020-12-29 | 2022-10-04 | 厦门天马微电子有限公司 | Display panel and display device |
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Application publication date: 20150909 |