CN104882449A - 一种阵列基板的制作方法、阵列基板及显示面板 - Google Patents

一种阵列基板的制作方法、阵列基板及显示面板 Download PDF

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CN104882449A
CN104882449A CN201510152388.1A CN201510152388A CN104882449A CN 104882449 A CN104882449 A CN 104882449A CN 201510152388 A CN201510152388 A CN 201510152388A CN 104882449 A CN104882449 A CN 104882449A
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吕晓文
曾志远
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TCL China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种阵列基板的制作方法、阵列基板及显示面板,该制作方法包括在基板上依次形成第一金属层、绝缘层、第一薄膜层、第二金属层及无机层;在有无机层上形成光阻层;在无机层及光阻层上形成有机层;在有机层及无机层上挖孔以形成第一通孔,使第二金属层部分裸露出来;在有机层以及裸露的第二金属层上形成第二薄膜层。通过上述方式,本发明能够减小金属层的损坏以及减少制程中的光罩,提高生产良率。

Description

一种阵列基板的制作方法、阵列基板及显示面板
技术领域
本发明涉及显示领域,特别是涉及一种阵列基板的制作方法、阵列基板及显示面板。
背景技术
OLED由于具有自发光,宽视角,响应快,轻薄,易于用于柔性显示领域等诸多优点而成为目前研究的热点,是公认的继LCD,PDP之后下一代显示技术的主流。
氧化物半导体具有较高的迁移率,同时非晶结构与目前a-Si制程兼容性较高,在OLED大尺寸面板的生产中得到了广泛的应用。
氧化物半导体背板TFT应用较多的结构包括蚀刻阻止(ESL)结构,背沟道蚀刻(BCE)结构,共平面(CP)结构,这些结构各有优缺点,其中ESL结构因为蚀刻阻止层保护氧化物半导体,器件稳定性较好,但是蚀刻阻止结构Array制程中需多一道光罩,且耦合电容较大,不利于良率的提升,及成本的下降。
发明内容
本发明主要解决的技术问题是提供一种阵列基板的制作方法、阵列基板及显示面板,能够减小金属层的损坏以及减少制程中的光罩,提高生产良率。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种阵列基板的制作方法,其特征在于,方法包括:在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层;在有无机层上形成光阻层;在无机层及光阻层上形成有机层;在有机层及无机层上挖孔以形成第一通孔,使第二金属层部分裸露出来;在有机层以及裸露的第二金属层上形成第二薄膜层。
其中,在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层的步骤,具体为:在基板上形成第一金属层并图形化,以形成第一金属电极及第二金属电极;在基板及第一金属层上形成绝缘层并图形化,以裸露部分第二金属电极;在绝缘层上形成第一薄膜层并图形化,形成第一薄膜电极及第二薄膜电极,以分别对应第一金属电极及第二金属电极;在薄膜层上形成蚀刻阻止层以及在蚀刻阻止层和裸露的第二金属电极上形成第二金属层,对应形成源/漏电极;在第二金属层上形成无机层。
其中,在薄膜层上形成蚀刻阻止层以及在蚀刻阻止层和裸露的第二金属电极上形成第二金属层,对应形成源/漏电极的步骤,具体为:在第一薄膜电极及第二薄膜电极上分别形成第一蚀刻阻止层及第二蚀刻阻止层;在第一蚀刻阻止层、第二蚀刻阻止层和裸露的第二金属电极上形成第二金属层并图形化,以在第一薄膜电极及第二薄膜电极上分别形成源/漏电极,从而形成第一岛状半导体及第二岛状半导体;其中,第一岛状半导体的源极或漏极与第二岛状半导体中裸露的第二金属电极连接。
其中,在有机层以及裸露的第二金属层上形成第二薄膜层的步骤,具体为:在有机层以及裸露的第二金属层上形成第二薄膜层并图形化,以形成第三薄膜电极;其中,第三薄膜电极与第二岛状半导体的源极或漏极通过第一通孔连接。
其中,在有机层及无机层上挖孔以形成第一通孔,使第二金属层部分裸露出来的步骤,具体为:对有机层进行灰化,并以有机层作为光阻对无机层进行图形化开孔,以形成第一通孔。
其中,在有无机层上形成光阻层的步骤,具体为:在有无机层上分别形成红、绿、蓝三色光阻。
其中,第一薄膜层为IGZO材料,第二薄膜层为ITO材料。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种阵列基板,其特征在于,阵列基板包括基板以及依次形成在基板上的第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层、无机层、光阻层、有机层以及第二薄膜层;其中,第二金属层包括源/漏电极;无机层及有机层上设有第一通孔,使裸露出来的源极或漏极与第二薄膜层连接。
其中,第一金属层包括第一金属电极及第二金属电极,第一薄膜层包括分别对应于第一金属电极及第二金属电极的第一薄膜电极及第二薄膜电极;第二金属层包括对应于第一薄膜电极的第一源极/漏极,以及对应于第二薄膜电极的第二源极/漏极;第一源极或第一漏极与第二金属电极连接;第二源极或第二漏极与第二薄膜层通过第一通孔连接。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种显示面板,该显示面板包括阵列基板,该阵列基板是如上述的阵列基板。
本发明的有益效果是:区别于现有技术的情况,本发明在阵列基板的制作过程中,在形成无机层后不立即打孔,而是先在无机层上形成RGB光阻,再在光阻上形成有机层后,再对有机层和无机层打孔以使金属源极/漏极裸露出来,避免了传统的工艺中先打孔再形成RGB时对金属源极/漏极的腐蚀破坏,并且对有机层和无机层同时打孔,避免了先后打孔时对位要求精确的问题,提高了面板的开口率,降低了工艺难度。
附图说明
图1是本发明阵列基板的制作方法第一实施方式的流程图;
图2是本发明阵列基板的制作方法第一实施方式中步骤101的结构示意图;
图3是本发明阵列基板的制作方法第一实施方式中步骤102的结构示意图;
图4是本发明阵列基板的制作方法第一实施方式中步骤103的结构示意图;
图5是本发明阵列基板的制作方法第一实施方式中步骤104的结构示意图;
图6是本发明阵列基板的制作方法第一实施方式中步骤105的结构示意图;
图7是本发明阵列基板的制作方法第二实施方式的流程图;
图8是本发明阵列基板的制作方法第二实施方式中步骤701-705的结构示意图;
图9是本发明阵列基板的制作方法第二实施方式中步骤706-709的结构示意图;
图10是本发明阵列基板一实施方式的结构示意图。
具体实施方式
参阅图1,本发明阵列基板的制作方法第一实施方式的流程图,该方法包括:
步骤101:在基板200上依次形成第一金属层201、绝缘层202、第一薄膜层203、蚀刻阻止层204、第二金属层205及无机层206;
如图2所示,步骤101具体包括:
在基板200上沉积第一金属层201;其中,该基板200一般是玻璃基板,在基板200上沉积第一金属层201的方法一般是溅射沉积或者化学气相沉积;
在第一金属层201上形成绝缘层202,该绝缘层202一般也称为栅极绝缘层;
在绝缘层202上形成第一薄膜层203,对该薄膜层203图形化以使该薄膜层的大小对应于第一金属层201;其中,该第一薄膜层203一般是透明的半导体材料IGZO,也可以是ITO等其他具有类似功能的材料;
在第一薄膜层203上形成蚀刻阻止层204并图形化,以使图形化后的第一薄膜层203裸露两端部分;
在蚀刻阻止层204及第一薄膜层203裸露出来的部分沉积第二金属层205,并图形化以分别形成源极和漏极,源极和漏极分别对应于第一薄膜层203的两端;
在蚀刻阻止层204及第二金属层205上形成无机层206。
步骤102:在无机层206上形成光阻层207;
如图3所示,步骤102具体包括:在无机层206上分别形成红、绿、蓝三色光阻。
步骤103:在无机层206及光阻层207上形成有机层208;(如图4)
步骤104:在有机层208及无机层206上挖孔以形成第一通孔210,使第二金属层205部分裸露出来;(如图5)
步骤105:在有机层208以及裸露的第二金属层205上形成第二薄膜层209。(如图6)
区别于现有技术,本实施方式在阵列基板的制作过程中,在形成无机层后不立即打孔,而是先在无机层上形成RGB光阻,再在光阻上形成有机层后,再对有机层和无机层打孔以使金属源极/漏极裸露出来,避免了传统的工艺中先打孔再形成RGB时对金属源极/漏极的腐蚀破坏,并且对有机层和无机层同时打孔,避免了先后打孔时对位要求精确的问题,提高了面板的开口率,降低了工艺难度。
参阅图7,本发明阵列基板的制作方法第二实施方式的流程图,该方法包括:
如图8所示,图8为以下步骤701-705的结构示意图。
步骤701:在基板800上形成第一金属层并图形化,以形成第一金属电极8011及第二金属电极8012;
步骤702:在基板及第一金属层上形成绝缘层802并图形化,以裸露部分第二金属电极8012;
步骤703:在绝缘层802上形成第一薄膜层并图形化,形成第一薄膜电极8031及第二薄膜电极8032,以分别对应第一金属电极8011及第二金属电极8012;
步骤704:在薄膜层上形成蚀刻阻止层804以及在蚀刻阻止层804和裸露的第二金属电极8012上形成第二金属层805,对应形成源/漏电极;
步骤705:在第二金属层805上形成无机层806;
以上步骤与第一实施方式类似,不同之处在于在基板800上形成了两个栅电极以及与两个栅电极对应的半导体小岛,在对第二金属层805图形化后,每个半导体小岛均包括源极和漏极,其中,第一半导体小岛的漏极或源极与第二半导体小岛的栅极(即第二金属电极8012)连接。
如图9所示,图9为以下步骤706-709的结构示意图。
步骤706:在有无机层806上形成光阻层807;
步骤707:在无机层806及光阻层807上形成有机层808;
步骤708:在有机层808及无机层807上挖孔以形成第一通孔,使第二金属层805部分裸露出来;
其中,裸露的第二金属层805部分是对应于如图9中第二半导体小岛的源极或漏极。
步骤709:在有机层807以及裸露的第二金属层805上形成第二薄膜层809。
该第二薄膜层一般是ITO,也可以是IGZO等其他类似功能的半导体材料。
参阅图10,本发明阵列基板一实施方式的结构示意图,该阵列基板包括:
基板1000以及依次形成在基板1000上的第一金属层1010、绝缘层1020、第一薄膜层1030、蚀刻阻止层1040、第二金属层1050、无机层1060、光阻层1070、有机层1080以及第二薄膜层1090;其中,第二金属层1050包括源/漏电极;无机层1060及有机层1080上设有第一通孔,使裸露出来的源极或漏极与第二薄膜层1090连接。
其中,第一金属层1010包括第一金属电极1011及第二金属电极1012,第一薄膜层1030包括分别对应于第一金属电极1011及第二金属电极1012的第一薄膜电极1031及第二薄膜电极1032;第二金属层1050包括对应于第一薄膜电极1031的第一源极/漏极(图未示),以及对应于第二薄膜电极1032的第二源极/漏极(图未示);第一源极或第一漏极与第二金属电极1012连接;第二源极或第二漏极与第二薄膜层1090通过第一通孔连接。
区别于现有技术,本实施方式在阵列基板的制作过程中,在形成无机层后不立即打孔,而是先在无机层上形成RGB光阻,再在光阻上形成有机层后,再对有机层和无机层打孔以使金属源极/漏极裸露出来,避免了传统的工艺中先打孔再形成RGB时对金属源极/漏极的腐蚀破坏,并且对有机层和无机层同时打孔,避免了先后打孔时对位要求精确的问题,提高了面板的开口率,降低了工艺难度。
另外,本发明还提供一种显示面板,该显示面板包括如上各个实施方式中所述的阵列基板。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种阵列基板的制作方法,其特征在于,所述方法包括:
在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层;
在所述有无机层上形成光阻层;
在所述无机层及所述光阻层上形成有机层;
在所述有机层及所述无机层上挖孔以形成第一通孔,使所述第二金属层部分裸露出来;
在所述有机层以及裸露的第二金属层上形成第二薄膜层。
2.根据权利要求1所述的方法,其特征在于,所述在基板上依次形成第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层及无机层的步骤,具体为:
在基板上形成第一金属层并图形化,以形成第一金属电极及第二金属电极;
在所述基板及所述第一金属层上形成绝缘层并图形化,以裸露部分所述第二金属电极;
在所述绝缘层上形成第一薄膜层并图形化,形成第一薄膜电极及第二薄膜电极,以分别对应所述第一金属电极及第二金属电极;
在所述薄膜层上形成蚀刻阻止层以及在所述蚀刻阻止层和裸露的所述第二金属电极上形成第二金属层,对应形成源/漏电极;
在所述第二金属层上形成无机层。
3.根据权利要求2所述的方法,其特征在于,所述在所述薄膜层上形成蚀刻阻止层以及在所述蚀刻阻止层和裸露的所述第二金属电极上形成第二金属层,对应形成源/漏电极的步骤,具体为:
在所述第一薄膜电极及第二薄膜电极上分别形成第一蚀刻阻止层及第二蚀刻阻止层;
在所述第一蚀刻阻止层、第二蚀刻阻止层和裸露的所述第二金属电极上形成第二金属层并图形化,以在所述第一薄膜电极及第二薄膜电极上分别形成源/漏电极,从而形成第一岛状半导体及第二岛状半导体;
其中,所述第一岛状半导体的源极或漏极与所述第二岛状半导体中裸露的所述第二金属电极连接。
4.根据权利要求3所述的方法,其特征在于,所述在所述有机层以及裸露的第二金属层上形成第二薄膜层的步骤,具体为:
在所述有机层以及裸露的第二金属层上形成第二薄膜层并图形化,以形成第三薄膜电极;
其中,所述第三薄膜电极与所述第二岛状半导体的源极或漏极通过第一通孔连接。
5.根据权利要求1所述的方法,其特征在于,所述在所述有机层及所述无机层上挖孔以形成第一通孔,使所述第二金属层部分裸露出来的步骤,具体为:
对所述有机层进行灰化,并以所述有机层作为光阻对所述无机层进行图形化开孔,以形成所述第一通孔。
6.根据权利要求1所述的方法,其特征在于,所述在所述有无机层上形成光阻层的步骤,具体为:
在所述有无机层上分别形成红、绿、蓝三色光阻。
7.根据权利要求1所述的方法,其特征在于,所述第一薄膜层为IGZO材料,所述第二薄膜层为ITO材料。
8.一种阵列基板,其特征在于,所述阵列基板包括基板以及依次形成在所述基板上的第一金属层、绝缘层、第一薄膜层、蚀刻阻止层、第二金属层、无机层、光阻层、有机层以及第二薄膜层;
其中,所述第二金属层包括源/漏电极;
所述无机层及有机层上设有第一通孔,使裸露出来的源极或漏极与所述第二薄膜层连接。
9.根据权利要求8所述的阵列基板,其特征在于,所述第一金属层包括第一金属电极及第二金属电极,所述第一薄膜层包括分别对应于所述第一金属电极和所述第二金属电极的第一薄膜电极和第二薄膜电极;
所述第二金属层包括对应于所述第一薄膜电极的第一源极/漏极,以及对应于所述第二薄膜电极的第二源极/漏极;
所述第一源极或第一漏极与所述第二金属电极连接;
所述第二源极或第二漏极与所述第二薄膜层通过所述第一通孔连接。
10.一种显示面板,其特征在于,所述显示面板包括阵列基板,所述阵列基板是如权利要求8-9任一项所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109585516A (zh) * 2018-12-13 2019-04-05 武汉华星光电半导体显示技术有限公司 一种tft驱动背板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090121232A1 (en) * 2007-11-13 2009-05-14 Chul Huh Array substrate, method for manufacturing the same and display panel having the same
CN101634789A (zh) * 2009-08-25 2010-01-27 友达光电股份有限公司 像素结构以及像素结构的制作方法
CN103824876A (zh) * 2014-02-12 2014-05-28 京东方科技集团股份有限公司 一种三维显示面板、其制作方法及三维显示装置
CN103928343A (zh) * 2014-04-23 2014-07-16 深圳市华星光电技术有限公司 薄膜晶体管及有机发光二极管显示器制备方法
CN104241298A (zh) * 2014-09-02 2014-12-24 深圳市华星光电技术有限公司 Tft背板结构及其制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101409263B (zh) * 2008-12-02 2010-06-30 友达光电股份有限公司 像素结构、显示面板以及光电装置的制造方法
CN101604104B (zh) * 2009-07-22 2014-06-11 友达光电股份有限公司 薄膜晶体管阵列及其制造方法
US9142568B2 (en) * 2010-09-10 2015-09-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing light-emitting display device
KR101407310B1 (ko) * 2011-12-30 2014-06-16 엘지디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
TWI469360B (zh) * 2012-09-06 2015-01-11 Innocom Tech Shenzhen Co Ltd 顯示面板及顯示裝置
TWI500144B (zh) * 2012-12-31 2015-09-11 Lg Display Co Ltd 有機發光顯示裝置及其製造方法
CN103219283A (zh) * 2013-03-19 2013-07-24 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN103337500B (zh) * 2013-05-24 2015-12-23 友达光电股份有限公司 主动元件阵列基板及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090121232A1 (en) * 2007-11-13 2009-05-14 Chul Huh Array substrate, method for manufacturing the same and display panel having the same
CN101634789A (zh) * 2009-08-25 2010-01-27 友达光电股份有限公司 像素结构以及像素结构的制作方法
CN103824876A (zh) * 2014-02-12 2014-05-28 京东方科技集团股份有限公司 一种三维显示面板、其制作方法及三维显示装置
CN103928343A (zh) * 2014-04-23 2014-07-16 深圳市华星光电技术有限公司 薄膜晶体管及有机发光二极管显示器制备方法
CN104241298A (zh) * 2014-09-02 2014-12-24 深圳市华星光电技术有限公司 Tft背板结构及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109585516A (zh) * 2018-12-13 2019-04-05 武汉华星光电半导体显示技术有限公司 一种tft驱动背板
US11177298B2 (en) 2018-12-13 2021-11-16 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. TFT driving backplane

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