CN104167447B - 一种薄膜晶体管及其制备方法、显示基板和显示设备 - Google Patents

一种薄膜晶体管及其制备方法、显示基板和显示设备 Download PDF

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CN104167447B
CN104167447B CN201410351335.8A CN201410351335A CN104167447B CN 104167447 B CN104167447 B CN 104167447B CN 201410351335 A CN201410351335 A CN 201410351335A CN 104167447 B CN104167447 B CN 104167447B
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barrier layer
etching barrier
layer
film transistor
thin film
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CN104167447A (zh
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张锋
曹占锋
姚琪
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种薄膜晶体管，包括：基板、有源层、第一刻蚀阻挡层、第二刻蚀阻挡层、源电极和漏电极，其中：有源层设于基板的上方；第一刻蚀阻挡层设于有源层的上方；第二刻蚀阻挡层设于第一刻蚀阻挡层的上方；源电极和漏电极设于第二刻蚀阻挡层的上方，利用第一刻蚀阻挡层和第二刻蚀阻挡层中的过孔，所述源电极和漏电极彼此通过有源层连接；处于沟道位置处的第一刻蚀阻挡层的长度小于第二刻蚀阻挡层的长度。本发明同时还公开了一种薄膜晶体管的制备方法、阵列基板和显示设备。本发明薄膜晶体管的沟道长度小于现有薄膜晶体管的沟道长度，从而减小了薄膜晶体管的尺寸和能耗，提高了液晶面板的开口率，提高了薄膜晶体管的开启电流，进一步提高了薄膜晶体管的整体性能。

Description

一种薄膜晶体管及其制备方法、显示基板和显示设备
技术领域
本发明涉及显示领域，尤其是一种薄膜晶体管(Thin Film Transistor，TFT)及其制备方法、显示基板和显示设备。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器由于可以做得更轻更薄，可视角度更大，无辐射，并且能够显著节省电能，从而在当前的平板显示设备市场占据了主导地位，被认为是最可能的下一代新型平面显示器。有源矩阵OLED为每一个像素配备了用于控制该像素的薄膜晶体管作为开关，所述薄膜晶体管通常包括栅极、源极和漏极以及栅绝缘层和有源层。
氧化物(Oxide)，如铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)等和非晶硅均可作为薄膜晶体管的有源层材料，与非晶硅薄膜晶体管相比，氧化物薄膜晶体管的载流子浓度是非晶硅薄膜晶体管的十倍左右，载流子迁移率是非晶硅薄膜晶体管的20-30倍，因此，氧化物薄膜晶体管可以大大地提高薄膜晶体管对于像素电极的充放电速率，提高像素的响应速度，进而实现更快的刷新率。氧化物薄膜晶体管能够满足需要快速响应和较大电流的应用场合，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等，因此，氧化物薄膜晶体管成为用于新一代LCD，OLED显示设备的半导体组件。
图1A为现有技术中刻蚀阻挡型氧化物薄膜晶体管的结构示意图，图1B为图1A所示氧化物薄膜晶体管沿A-A’的截面图，如图1A和图1B所示，图1B中，11为基板，12为栅极，13为栅极绝缘层，14为有源层，15为刻蚀阻挡层，16为源漏电极，现有的氧化物薄膜晶体管中，由于氧化物半导体层多为非晶半导体氧化物，因此，其与源漏(SD)金属层的欧姆接触存在问题，从而容易导致薄膜晶体管的稳定性不良。另外，薄膜晶体管的沟道长度会影响薄膜晶体管的开启电流，沟道长度越小薄膜晶体管的开启电流就越大，然而现有的刻蚀阻挡型氧化物薄膜晶体管中，由于刻蚀阻挡层的存在，使得现有氧化物薄膜晶体管的沟道长度较大，开启电流较小，严重降低了薄膜晶体管的性能，不利于高性能显示设备的开发。
发明内容
为了解决上述现有技术中存在的问题，本发明提出一种薄膜晶体管及其制备方法、显示基板和显示设备。
根据本发明的一方面，提出一种薄膜晶体管，包括：基板、有源层、第一刻蚀阻挡层、第二刻蚀阻挡层、源电极和漏电极，其中：
所述有源层设置于所述基板的上方；
所述第一刻蚀阻挡层设置于所述有源层的上方；
所述第二刻蚀阻挡层设置于所述第一刻蚀阻挡层的上方；
所述源电极和漏电极设置于所述第二刻蚀阻挡层的上方，利用所述第一刻蚀阻挡层和第二刻蚀阻挡层中的过孔，所述源电极和漏电极彼此通过所述有源层连接；
其中，处于沟道位置处的第一刻蚀阻挡层的长度小于处于沟道位置处的第二刻蚀阻挡层的长度。
其中，所述第一刻蚀阻挡层的刻蚀速率高于第二刻蚀阻挡层的刻蚀速率。
其中，所述第一刻蚀阻挡层与第二刻蚀阻挡层均采用氧化硅制作；或者所述第一刻蚀阻挡层采用氮化硅制作，而第二刻蚀阻挡层采用氧化硅制作。
其中，还包括钝化层，所述钝化层设置于所述源电极和漏电极的上方。
其中，所述有源层为金属氧化物半导体材料。
根据本发明的另一方面，还提出一种阵列基板，包括如上所述的薄膜晶体管。
根据本发明的另一方面，还提出一种显示设备，包括如上所述的阵列基板。
根据本发明的再一方面，还提出一种薄膜晶体管的制备方法，该制备方法包括以下步骤：
在基板上形成半导体层，并进行图形化，得到有源层；
在所述有源层上形成第一刻蚀阻挡材料层；
在所述第一刻蚀阻挡材料层上形成第二刻蚀阻挡材料层，进行图形化，得到第一刻蚀阻挡层和第二刻蚀阻挡层，其中，处于沟道位置处的第一刻蚀阻挡层的长度小于处于沟道位置处的第二刻蚀阻挡层的长度；
在所述第二刻蚀阻挡层上形成电极材料层，并进行图形化，得到源电极和漏电极，利用所述第一刻蚀阻挡层和第二刻蚀阻挡层中的过孔，所述源电极和漏电极彼此通过有源层连接。
其中，所述第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率。
其中，所述第一刻蚀阻挡层的沉积速率大于所述第二刻蚀阻挡层的沉积速率，所述第一刻蚀阻挡材料层与第二刻蚀阻挡材料层均采用氧化硅制作；或者所述第一刻蚀阻挡层采用氮化硅制作，而第二刻蚀阻挡层采用氧化硅制作。
其中，所述有源层为金属氧化物半导体材料。
其中，在形成所述源电极和漏电极后，还包括在所述源电极和漏电极上形成钝化层的步骤。
根据上述技术方案，本发明薄膜晶体管中设置了双层刻蚀阻挡层，并利用位于下层的第一刻蚀阻挡层较位于上层的第二刻蚀阻挡层的刻蚀速率快的特性，使得刻蚀速率快的第一刻蚀阻挡层被刻蚀的部分大于刻蚀速率慢的第二刻蚀阻挡层，进而使得第一刻蚀阻挡层与第二刻蚀阻挡层形成了一种倒沟槽结构，缩短了源、漏电极之间载流子的传输距离，从而减小了薄膜晶体管的沟道长度。较小的沟道长度能够减小薄膜晶体管的尺寸，提高液晶面板的开口率，减少能耗；并且较小的沟道长度能够提高薄膜晶体管的开启电流，提高充电效率，从而大大地提高薄膜晶体管的整体性能，有利于高分辨率产品的开发。
附图说明
图1A为现有技术中的氧化物薄膜晶体管的结构示意图；
图1B为图1A所示氧化物薄膜晶体管沿A-A’的截面图；
图2为根据本发明一实施例的薄膜晶体管的结构示意图；
图3为根据本发明一实施例的薄膜晶体管制备工艺流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
根据本发明的一方面，提出一种薄膜晶体管，如图2所示，该薄膜晶体管依次包括：基板1、有源层4、第一刻蚀阻挡层5、第二刻蚀阻挡层6、源电极和漏电极，其中：
所述有源层4设置于所述基板1的上方；
所述第一刻蚀阻挡层5设置于所述有源层4的上方；
所述第二刻蚀阻挡层6设置于所述第一刻蚀阻挡层5的上方，所述第一刻蚀阻挡层5和第二刻蚀阻挡层6用于保护处于源漏电极之间的沟道区域中的有源层4部分不受显影液和刻蚀液的侵蚀影响；
所述源电极和漏电极设置于所述第二刻蚀阻挡层6的上方，通过所述有源层4连接，其中，利用所述第一刻蚀阻挡层5和第二刻蚀阻挡层6中的过孔，所述源电极和漏电极彼此通过所述有源层4连接；
其中，处于沟道位置处的第一刻蚀阻挡层5的长度小于处于沟道位置处的第二刻蚀阻挡层6的长度，即第一刻蚀阻挡层5和第二刻蚀阻挡层6形成一种倒沟槽结构，从而减小了源漏电极之间的距离，即所述薄膜晶体管的沟道长度，缩短了源、漏电极之间载流子的传输距离。
其中，所述第一刻蚀阻挡层和第二刻蚀阻挡层由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的其中一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，并且具有良好的介电特性以及对水汽、氧气的阻挡特性，因此采用上述材料制作刻蚀阻挡层时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，并且能够满足金属氧化物薄膜晶体管的特性要求。
需要特别注意的是，本发明中，所述第一刻蚀阻挡层5的刻蚀速率高于第二刻蚀阻挡层6的刻蚀速率，这样就使得刻蚀完成之后，刻蚀速率快的第一刻蚀阻挡层被刻蚀的部分大于刻蚀速率慢的第二刻蚀阻挡层，即所述第一刻蚀阻挡层5和第二刻蚀阻挡层6形成一种倒沟槽结构。
在本发明一实施例中，所述第一刻蚀阻挡层5与第二刻蚀阻挡层6采用相同的制作材料，比如氧化硅，但是所述第一刻蚀阻挡层5的沉积速率大于第二刻蚀阻挡层6的沉积速率，进而使得第一刻蚀阻挡层5的刻蚀速率高于第二刻蚀阻挡层6的刻蚀速率。
在本发明另一实施例中，所述第一刻蚀阻挡层5与第二刻蚀阻挡层6采用不同的制作材料，比如所述第一刻蚀阻挡层5采用相对易于刻蚀的氮化硅来制作，所述第二刻蚀阻挡层6采用相对难于刻蚀的氧化硅来制作，这样也可以使得第一刻蚀阻挡层5的刻蚀速率高于第二刻蚀阻挡层6的刻蚀速率。
需要说明的是，本发明对于第一刻蚀阻挡层5与第二刻蚀阻挡层6的制作材料和形成方法不作特别的限定，能够使得第一刻蚀阻挡层5的刻蚀速率高于第二刻蚀阻挡层6的刻蚀速率的任何合理的制作材料和形成方法都落入本发明的保护范围内。
可选地，所述基板1的制作材料包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述有源层4为金属氧化物半导体材料，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述源电极和漏电极由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料。
本发明对于源电极和漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极需要根据其与像素电极的连接关系来决定，本申请中定义与像素电极连接的是漏电极。
在本发明一实施例中，所述薄膜晶体管还包括钝化层8，所述钝化层8设置于所述源电极和漏电极的上方。
此外，对于顶栅结构的薄膜晶体管，所述薄膜晶体管还包括：位于所述源电极和漏电极7之上的栅极绝缘层，以及位于所述栅极绝缘层之上的栅极。
对于底栅结构的薄膜晶体管，如图2所示，所述薄膜晶体管还包括：位于所述有源层4之下的栅极绝缘层3，以及位于所述栅极绝缘层3之下的栅极2。
根据上述任一实施例的薄膜晶体管，由于设置有双层刻蚀阻挡层，并利用位于下层的第一刻蚀阻挡层较位于上层的第二刻蚀阻挡层的刻蚀速率快的特性，使得刻蚀速率快的第一刻蚀阻挡层被刻蚀的部分大于刻蚀速率慢的第二刻蚀阻挡层，第一刻蚀阻挡层与第二刻蚀阻挡层形成一种倒沟槽结构。在通电的情况下，源漏电极之间的区域形成沟道，这样由于第一刻蚀阻挡层与第二刻蚀阻挡层形成一种倒沟槽结构，从而缩短了源、漏电极之间载流子的传输距离，进而减小了所述薄膜晶体管的沟道长度，使得根据本发明上述技术方案的薄膜晶体管的沟道长度D2小于现有技术的薄膜晶体管的沟道长度D1，如图2所示。根据目前设备的精度和工艺的限制，所能实现的薄膜晶体管的沟道长度D2相对于现有技术中的沟道长度能够减小1.0um～3.0um。较小的沟道长度能够减小薄膜晶体管的尺寸，提高液晶面板的开口率，减少能耗；并且较小的沟道长度能够提高薄膜晶体管的开启电流，提高充电效率，从而大大提高薄膜晶体管的整体性能，有利于高分辨产品的开发。
根据本发明的另一方面，还提出一种阵列基板，所述阵列基板包括上述任一实施例所述的薄膜晶体管。
根据本发明的另一方面，还提出一种显示设备，所述显示设备包括如上所述的阵列基板。
根据本发明的再一方面，还提出一种薄膜晶体管的制备方法，所述制备方法包括以下步骤：
步骤1，在基板1上形成半导体层，并进行图形化，得到有源层4；
可选地，所述基板1的制作材料包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述有源层4为金属氧化物，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述半导体层可采用溅射技术或等离子体化学气相沉积(PECVD)技术形成，本发明对于所述半导体层的形成方式不作特殊限定。
可选地，通过灰阶掩膜曝光工艺来对半导体层进行图形化，形成有源层4。
步骤2，在所述有源层4上形成第一刻蚀阻挡材料层；
步骤3，在所述第一刻蚀阻挡材料层上形成第二刻蚀阻挡材料层，进行图形化，得到第一刻蚀阻挡层5和第二刻蚀阻挡层6，所述第一刻蚀阻挡层5和第二刻蚀阻挡层6用于保护处于源漏电极之间的沟道区域中的有源层4部分不受显影液和刻蚀液的侵蚀影响；
其中，利用等离子体化学气相沉积等常见半导体形成工艺来得到第一刻蚀阻挡材料层和第二刻蚀阻挡材料层。
其中，利用曝光、显影、刻蚀等常见的构图工艺来进行图形化。
图形化之后，处于沟道位置处的第一刻蚀阻挡层5的长度小于处于沟道位置处的第二刻蚀阻挡层6的长度，即第一刻蚀阻挡层5和第二刻蚀阻挡层6形成一种倒沟槽结构，从而减小了源漏电极之间的距离，即所述薄膜晶体管的沟道长度，缩短了源、漏电极之间载流子的传输距离。
其中，所述第一刻蚀阻挡材料层和第二刻蚀阻挡材料层由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的其中一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，并且具有良好的介电特性以及对水汽、氧气的阻挡特性，因此采用上述材料制作刻蚀阻挡层时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，并且能够满足金属氧化物薄膜晶体管的特性要求。
需要特别注意的是，本发明中，所述第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率，这样就使得刻蚀完成之后，刻蚀速率快的第一刻蚀阻挡层被刻蚀的部分大于刻蚀速率慢的第二刻蚀阻挡层，即所述第一刻蚀阻挡层5和第二刻蚀阻挡层6形成一种倒沟槽结构，如图3E所示，从而减小了所述薄膜晶体管的沟道长度。
在本发明一实施例中，所述第一刻蚀阻挡材料层与第二刻蚀阻挡材料层采用相同的制作材料，比如氧化硅，但是所述第一刻蚀阻挡材料层的沉积速率大于第二刻蚀阻挡材料层的沉积速率，进而使得第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率。
在本发明另一实施例中，所述第一刻蚀阻挡材料层与第二刻蚀阻挡材料层采用不同的制作材料，比如所述第一刻蚀阻挡材料层采用相对易于刻蚀的氮化硅来制作，所述第二刻蚀阻挡材料层采用相对难于刻蚀的氧化硅来制作，这样也可以使得第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率。
需要说明的是，本发明对于第一刻蚀阻挡材料层与第二刻蚀阻挡材料层的制作材料和形成方法不作特别的限定，能够使得第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率的任何合理的制作材料和形成方法都落入本发明的保护范围内。
步骤4，在所述第二刻蚀阻挡层6上形成电极材料层，并进行图形化，得到源电极和漏电极7，利用所述第一刻蚀阻挡层5和第二刻蚀阻挡层6中的过孔，所述源电极和漏电极7彼此通过所述有源层4连接；
其中，所述电极材料层由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料。
可选地，可通过曝光、显影、刻蚀等构图工艺来形成所述源电极和漏电极7。
本发明对于源电极和漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极需要根据其与像素电极的连接关系来决定，本申请中定义与像素电极连接的是漏电极。
在本发明一实施例中，所述制备方法在形成源电极和漏电极7之后，还包括在所述源电极和漏电极7上形成钝化层8的步骤。
此外，在制备顶栅结构的薄膜晶体管时，还包括在所述源电极和漏电极7上形成栅极绝缘层，以及在所述栅极绝缘层上形成栅极的步骤。
在制备底栅结构的薄膜晶体管时，在形成所述有源层4之前，还包括在所述基板1上形成栅极2，以及在形成有所述栅极层2的基板上形成栅极绝缘层3的步骤。
下面以底栅结构的薄膜晶体管为例更详细的说明本发明的技术方案，如图3所示，所述底栅结构的薄膜晶体管的制备方法包括以下步骤：
步骤1，在基板1上依次形成栅极材料层和栅极绝缘材料层，并进行图形化，得到栅极2和栅极绝缘层3，如图3A所示；
可选地，所述基板1的制作材料包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述栅极2由导电材料制成，比如金属、半导体材料，优选为金属材料。
可选地，所述栅极绝缘层3可通过CVD方法来沉积，其制作材料优选为绝缘材料，包括二氧化硅、氮化硅、氮氧化硅等，或者以上材料的组合。
步骤2，在所述栅极绝缘层3上形成半导体层，并进行图形化，得到有源层4，如图3B所示；
其中，所述有源层4为金属氧化物，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述半导体层可采用溅射技术或等离子体化学气相沉积(PECVD)技术形成，本发明对于所述半导体层的形成方式不作特殊限定。
可选地，通过灰阶掩膜曝光工艺来对半导体层进行图形化，形成有源层4。
步骤3，在所述有源层4上形成第一刻蚀阻挡材料层，如图3C所示；
步骤4，在所述第一刻蚀阻挡材料层上形成第二刻蚀阻挡材料层，如图3D所示，进行图形化，得到第一刻蚀阻挡层5和第二刻蚀阻挡层6，如图3E所示，所述第一刻蚀阻挡层5和第二刻蚀阻挡层6用于保护处于源漏电极之间的沟道区域中的有源层4部分不受显影液和刻蚀液的侵蚀影响；
其中，利用等离子体化学气相沉积等常见半导体形成工艺来得到第一刻蚀阻挡材料层和第二刻蚀阻挡材料层。
其中，利用曝光、显影、刻蚀等常见的构图工艺来进行图形化。
图形化之后，处于沟道位置处的第一刻蚀阻挡层5的长度小于处于沟道位置处的第二刻蚀阻挡层6的长度，即第一刻蚀阻挡层5和第二刻蚀阻挡层6形成一种倒沟槽结构，从而减小了源漏电极之间的距离，即所述薄膜晶体管的沟道长度，缩短了源、漏电极之间载流子的传输距离。
其中，所述第一刻蚀阻挡材料层和第二刻蚀阻挡材料层由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的其中一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，并且具有良好的介电特性以及对水汽、氧气的阻挡特性，因此采用上述材料制作刻蚀阻挡层时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，并且能够满足金属氧化物薄膜晶体管的特性要求。
需要特别注意的是，本发明中，所述第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率，这样就使得刻蚀完成之后，刻蚀速率快的第一刻蚀阻挡层被刻蚀的部分大于刻蚀速率慢的第二刻蚀阻挡层，即所述第一刻蚀阻挡层5和第二刻蚀阻挡层6形成一种倒沟槽结构，如图3E所示，进而减小了所述薄膜晶体管的沟道长度。
可采用多种方法实现第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率，形成倒沟槽结构。
在本发明一实施例中，所述第一刻蚀阻挡材料层与第二刻蚀阻挡材料层采用相同的制作材料，比如氧化硅，但是所述第一刻蚀阻挡材料层的沉积速率大于第二刻蚀阻挡材料层的沉积速率，进而使得第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率，比如，第一刻蚀阻挡材料层的具体沉积参数可参考表1，第二刻蚀阻挡材料层的具体沉积参数可参考表2：
表1
表2
在本发明另一实施例中，所述第一刻蚀阻挡材料层与第二刻蚀阻挡材料层采用不同的制作材料，比如所述第一刻蚀阻挡材料层采用相对易于刻蚀的氮化硅来制作，所述第二刻蚀阻挡材料层采用相对难于刻蚀的氧化硅来制作，这样也可以使得第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率。
需要说明的是，本发明对于第一刻蚀阻挡材料层与第二刻蚀阻挡材料层的制作材料和形成方法不作特别的限定，能够使得第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率的任何合理的制作材料和形成方法都落入本发明的保护范围内。
步骤5，在所述第二刻蚀阻挡层6上形成电极材料层，并进行图形化，得到源电极和漏电极7，如图3F所示，利用所述第一刻蚀阻挡层5和第二刻蚀阻挡层6中的过孔，所述源电极和漏电极7彼此通过所述有源层4连接；
其中，所述电极材料层由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料。
可选地，可通过曝光、显影、刻蚀等构图工艺来形成所述源电极和漏电极7。
本发明对于源电极和漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极需要根据与像素电极的连接关系来决定，本申请中定义与像素电极连接的是漏电极。
步骤6，在所述源电极和漏电极7上形成钝化层8，如图3G所示。
根据上述任一实施例所描述的制备方法制得的薄膜晶体管，由于设置有双层刻蚀阻挡层，并利用位于下层的第一刻蚀阻挡层较位于上层的第二刻蚀阻挡层的刻蚀速率快的特性，使得刻蚀速率快的第一刻蚀阻挡层被刻蚀的部分大于刻蚀速率慢的第二刻蚀阻挡层，第一刻蚀阻挡层与第二刻蚀阻挡层形成一种倒沟槽结构。在通电的情况下，源漏电极之间的区域形成沟道，这样由于第一刻蚀阻挡层与第二刻蚀阻挡层形成一种倒沟槽结构，从而缩短了源、漏电极之间载流子的传输距离，进而减小了所述薄膜晶体管的沟道长度，使得根据本发明上述技术方案制得的薄膜晶体管的沟道长度D2小于现有技术制得的薄膜晶体管的沟道长度D1。根据目前设备的精度和工艺的限制，所能实现的薄膜晶体管的沟道长度D2相对于现有技术中的沟道长度能够减小1.0um～3.0um。较小的沟道长度能够减小薄膜晶体管的尺寸，提高液晶面板的开口率，减少能耗；并且较小的沟道长度能够提高薄膜晶体管的开启电流，提高充电效率，从而大大提高薄膜晶体管的整体性能，有利于高分辨产品的开发。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种薄膜晶体管，其特征在于，包括：基板、有源层、第一刻蚀阻挡层、第二刻蚀阻挡层、源电极和漏电极，其中：
所述有源层设置于所述基板的上方；
所述第一刻蚀阻挡层设置于所述有源层的上方；
所述第二刻蚀阻挡层设置于所述第一刻蚀阻挡层的上方；
所述源电极和漏电极设置于所述第二刻蚀阻挡层的上方，利用所述第一刻蚀阻挡层和第二刻蚀阻挡层中的过孔，所述源电极和漏电极彼此通过所述有源层连接；
其中，处于沟道位置处的第一刻蚀阻挡层的长度小于处于沟道位置处的第二刻蚀阻挡层的长度，且形成倒沟槽结构。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一刻蚀阻挡层的刻蚀速率高于第二刻蚀阻挡层的刻蚀速率。
3.根据权利要求2所述的薄膜晶体管，其特征在于，所述第一刻蚀阻挡层与第二刻蚀阻挡层均采用氧化硅制作；或者所述第一刻蚀阻挡层采用氮化硅制作，而第二刻蚀阻挡层采用氧化硅制作。
4.根据权利要求1所述的薄膜晶体管，其特征在于，还包括钝化层，所述钝化层设置于所述源电极和漏电极的上方。
5.根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层为金属氧化物半导体材料。
6.一种阵列基板，其特征在于，包括如权利要求1‐5任一项所述的薄膜晶体管。
7.一种显示设备，其特征在于，包括如权利要求6所述的阵列基板。
8.一种薄膜晶体管的制备方法，其特征在于，该制备方法包括以下步骤：
在基板上形成半导体层，并进行图形化，得到有源层；
在所述有源层上形成第一刻蚀阻挡材料层；
在所述第一刻蚀阻挡材料层上形成第二刻蚀阻挡材料层，进行图形化，得到第一刻蚀阻挡层和第二刻蚀阻挡层，其中，处于沟道位置处的第一刻蚀阻挡层的长度小于处于沟道位置处的第二刻蚀阻挡层的长度，且形成倒沟槽结构；
在所述第二刻蚀阻挡层上形成电极材料层，并进行图形化，得到源电极和漏电极，利用所述第一刻蚀阻挡层和第二刻蚀阻挡层中的过孔，所述源电极和漏电极彼此通过有源层连接。
9.根据权利要求8所述的制备方法，其特征在于，所述第一刻蚀阻挡材料层的刻蚀速率高于第二刻蚀阻挡材料层的刻蚀速率。
10.根据权利要求9所述的制备方法，其特征在于，所述第一刻蚀阻挡层的沉积速率大于所述第二刻蚀阻挡层的沉积速率，所述第一刻蚀阻挡材料层与第二刻蚀阻挡材料层均采用氧化硅制作；或者所述第一刻蚀阻挡层采用氮化硅制作，而第二刻蚀阻挡层采用氧化硅制作。
11.根据权利要求8所述的制备方法，其特征在于，所述有源层为金属氧化物半导体材料。
12.根据权利要求8所述的制备方法，其特征在于，在形成所述源电极和漏电极后，还包括在所述源电极和漏电极上形成钝化层的步骤。
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