CN104881072B - Low difference voltage regulator and electric power system - Google Patents
Low difference voltage regulator and electric power system Download PDFInfo
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- CN104881072B CN104881072B CN201510266228.XA CN201510266228A CN104881072B CN 104881072 B CN104881072 B CN 104881072B CN 201510266228 A CN201510266228 A CN 201510266228A CN 104881072 B CN104881072 B CN 104881072B
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Abstract
The invention provides a kind of low difference voltage regulator and electric power system, low difference voltage regulator comprises power tube, error amplifier, feedback voltage sample circuit, controls transistor, Enable Pin, output capacitance, gauge tap and output. The source electrode of power tube is connected with power end, and drain electrode is connected with output, and grid is connected with the output of error amplifier, and the second input of error amplifier is connected with reference voltage; Feedback voltage sample circuit for sample output voltage and export feedback voltage; Control transistorized the first link and be connected with power end, the second link is connected with the grid of power tube, and control end is connected with Enable Pin; Gauge tap and output capacitance are connected between output and ground successively, and the control end of gauge tap is connected with Enable Pin, and Enable Pin is used for receiving enable signal. Compared with prior art, the low difference voltage regulator in the present invention can be saved the extra energy consuming in service intermittent mode.
Description
[technical field]
The present invention relates to circuit design technique field, particularly a kind of low voltage difference voltage that can save energy is adjustedJoint device and electric power system.
[background technology]
As shown in Figure 1, it comprises error amplifier EA, power output to traditional low difference voltage regulatorPMOS manages MP5, divider resistance R1 and R2, and (or other is supplied for output capacitance C1 and arm processorElectricity circuit). Along with the rise of Internet of Things (InternetofThings) application, system requires more next to power consumptionStricter, particularly with battery powered system, wish that power consumption is the smaller the better, in order to reduce average power consumption,Circuit in a lot of systems is service intermittent, such as, based on ARM (AdvancedRISCMachines)Processor, generally realize and reduce average power consumption by closing and restarting its power supply, work as power supplyWhile closing, the supply voltage of arm processor reduces to zero, thus no longer power consumption.
In Fig. 1, low difference voltage regulator is arm processor power supply as power supply, at above-mentionedIn the formula of having a rest working method, in the time that low difference voltage regulator is closed, owing to having electric charge on output capacitance C1, ARMProcessor consumes the energy on output capacitance C1 by continuing, until the charge depletion on it; In the time restarting, lowDropout voltage adjuster can be full of output capacitance C1 again, makes it charge to arm processor neededOperating voltage VTR (for example, being 1.2V). constantly close with restarting process in, on output capacitance C1Electric charge released and the process that is full of by extra consumed energy, this energy is aboutWherein,C is the capacitance of output capacitance C1, and VTR is the required operating voltage of arm processor, and f is batch (-type)The frequency of work.
Therefore, be necessary to provide a kind of improved technical scheme to save above-mentionedly additionally disappears on output capacitance C1The energy of consumption.
[summary of the invention]
The object of the present invention is to provide a kind of low difference voltage regulator, it can be saved at service intermittentThe extra energy consuming in mode, thus the average power consumption of system further reduced.
In order to address the above problem, according to an aspect of the present invention, the invention provides a kind of low voltage difference voltageAdjuster, it comprises power tube, error amplifier, feedback voltage sample circuit, controls transistor, enablesEnd, output capacitance, gauge tap and output VO. The source electrode of described power tube is connected with power end, its leakageThe utmost point is connected with output VO, and its grid is connected with the output of error amplifier, second of error amplifierInput is connected with reference voltage; The input of described feedback voltage sample circuit is connected with output VO,The output of described feedback voltage sample circuit is connected with the first input end of described error amplifier, described anti-Feedthrough voltage sample circuit for sample described output VO voltage and export feedback voltage; Described control is brilliantThe first link of body pipe is connected with power end, and its second link is connected with the grid of power tube, its controlEnd is connected with Enable Pin; Described gauge tap and output capacitance are connected in described output VO and ground connection successivelyBetween end, the control end of described gauge tap is connected with described Enable Pin, and described Enable Pin enables for receivingSignal.
Further, in the time that described enable signal is the first logic level, it makes to control transistor turns, willThe grid voltage of power tube is drawn high to supply voltage, thereby switch-off power pipe is realized and closed low voltage difference voltage tuneJoint device, meanwhile, this first logic level is turn-offed gauge tap, to cut off output capacitance and output VOConnection; In the time that described enable signal is the second logic level, it makes to control transistor and turn-offs, now, and meritThe grid voltage of rate pipe is subject to the output control of error amplifier, and meanwhile, this second logic level makes to control and opensClose conducting, be connected with output VO to realize output capacitance, restart low difference voltage regulator thereby realize.
Further, described low difference voltage regulator also comprise be connected in gauge tap control end and enableLogic control circuit between end, the first input end of described logic control circuit is connected with Enable Pin, and it is years oldTwo inputs are connected with output VO, being connected between its 3rd input and output capacitance and gauge tapNode is connected, and its output is connected with the control end of described gauge tap. When described enable signal is second to patrolWhile collecting level, if the voltage of output VO is less than V1-Vos, letter is controlled in described logic control circuit outputNumber with make gauge tap turn-off, if when the voltage of output VO is more than or equal to V1-Vos, described logic controlCircuit processed makes gauge tap conducting, and wherein, V1 is the electricity of the connected node between output capacitance and gauge tapPressure value, Vos is predefined deviation voltage, in the time that described enable signal is the first logic level, described inLogic control circuit output control signal is turn-off gauge tap.
Further, described logic control circuit comprises comparator, voltage source and logical block, described comparisonThe first input end of device is connected with output VO, and its second input is connected with the negative pole of voltage source, this electricityThe positive pole of potential source is connected with the connected node between output capacitance and gauge tap, the output of comparator with patrolAn input collecting unit is connected; Another input of described logical block is connected with Enable Pin, described inThe output of logical block is connected with the control end of gauge tap, and the magnitude of voltage of described voltage source is described deviationThe magnitude of voltage of voltage.
Further, the span of described deviation voltage Vos is: 0 < Vos < 50mV.
Further, described power tube is PMOS transistor; The first input end of described error amplifier isNormal phase input end, its second input is negative-phase input; Described feedback voltage sample circuit comprises and being series atResistance R 2 between described output VO and earth terminal and resistance R 1, between resistance R 2 and resistance R 1Connected node is the output of described feedback voltage sample circuit.
Further, described control transistor is PMOS transistor, and described control transistorized first connectsEnd is source electrode, and its second link is drain electrode, and its control end is grid; Or described control transistor is PNPBipolar transistor, transistorized the first link of described control is emitter-base bandgap grading, its second link is colelctor electrode,Its control end is base stage.
Further, the first input end of described comparator is normal phase input end, and its second input is negativeInput; Described logical block comprises and door; The first logic level of enable signal is low level, and it is second years oldLogic level is high level.
Further, described control transistor is nmos pass transistor, and described control transistorized first connectsEnd is drain electrode, and its second link is source electrode, and its control end is grid; Or described control transistor is NPNBipolar transistor, transistorized the first link of described control is colelctor electrode, its second link is emitter-base bandgap grading,Its control end is base stage.
According to another aspect of the present invention, the invention provides a kind of electric power system, it comprises and is powered circuitAnd low difference voltage regulator. Described low difference voltage regulator is given and is powered circuit by its output VOPower supply, described in to be powered circuit be arm processor. Described low difference voltage regulator comprises power tube, mistakePoor amplifier, feedback voltage sample circuit, control transistor, Enable Pin, output capacitance, gauge tap andOutput VO. The source electrode of described power tube is connected with power end, and its drain electrode is connected with output VO, its gridThe utmost point is connected with the output of error amplifier, and the second input of error amplifier is connected with reference voltage; InstituteThe input of stating feedback voltage sample circuit is connected with output VO, described feedback voltage sample circuit defeatedGo out end and be connected with the first input end of described error amplifier, the described feedback voltage sample circuit institute that is used for samplingState the voltage of output VO and export feedback voltage; Transistorized the first link of described control and power endBe connected, its second link is connected with the grid of power tube, and its control end is connected with Enable Pin; Described controlSwitch and output capacitance are connected between described output VO and earth terminal successively, the control of described gauge tapSystem end is connected with described Enable Pin, and described Enable Pin is used for receiving enable signal.
Compared with prior art, when the present invention closes at low difference voltage regulator, cut off output capacitance and defeatedGo out the connection of end, in the time that low difference voltage regulator is restarted, connection output capacitance is connected with output, thisSample can save low difference voltage regulator constantly close with restarting process in, in output capacitance additionally consumeEnergy, thereby further reduce the average power consumption of system.
[brief description of the drawings]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, required in describing embodiment belowThe accompanying drawing using is briefly described, and apparently, the accompanying drawing in the following describes is only of the present inventionSome embodiment, for those of ordinary skill in the art, are not paying under the prerequisite of creative work,Can also obtain according to these accompanying drawings other accompanying drawing. Wherein:
Fig. 1 is the circuit diagram of traditional a kind of low difference voltage regulator;
Fig. 2 is the circuit diagram of the present invention's low difference voltage regulator in one embodiment;
Fig. 3 is that the output VO in the low difference voltage regulator shown in Fig. 2 becomes height at enable signal ENStartup oscillogram after level.
[detailed description of the invention]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing andThe present invention is further detailed explanation for detailed description of the invention.
Alleged " embodiment " or " embodiment " refer to and can be contained at least one realization side of the present invention hereinSpecial characteristic, structure or characteristic in formula. Different in this manual local " in one embodiment " that occurNot all refer to same embodiment, neither be independent or the reality mutually exclusive with other embodiment optionallyExecute example. Unless stated otherwise, the word that connection herein, the expression that is connected, joins are electrically connected all representsDirectly or indirectly be electrical connected.
Please refer to shown in Fig. 2 its circuit that is the present invention's low difference voltage regulator in one embodimentSchematic diagram. Low difference voltage regulator in Fig. 2 comprises power tube MP5, error amplifier EA, feedback electricityPress sample circuit 210, control transistor 220, Enable Pin EN, output capacitance C1, gauge tap S1 andOutput VO.
The source electrode of described power tube MP5 is connected with power end VIN, and its drain electrode is connected with output VO, itsGrid is connected with the output of error amplifier EA, the second input and the reference voltage of error amplifier EAVR is connected; The input of described feedback voltage sample circuit 210 is connected with output VO, described feedback electricityPress the output of sample circuit 210 to be connected with the first input end of described error amplifier EA, described feedback electricityPress sample circuit 210 for the voltage of the described output VO that samples and export feedback voltage FB; Described controlThe first link of transistor 220 is connected with power end VIN, the grid of its second link and power tube MP5Extremely connected, its control end is connected with Enable Pin EN; Described gauge tap S1 and output capacitance C1 connect successivelyBe connected between described output VO and earth terminal GND, the control end of described gauge tap S1 with described in makeCan hold EN to be connected; Described Enable Pin EN is used for receiving enable signal, and described enable signal can be first to patrolCollect level and the second logic level.
In the embodiment shown in Figure 2, described power tube MP5 is PMOS transistor; Described error is amplifiedThe first input end of device EA is normal phase input end, and its second input is negative-phase input; Described control crystalPipe 220 is PMOS transistor MP2, and the first link of described control transistor 220 is source electrode, and it is the years oldTwo links are drain electrode, and its control end is grid; Described feedback voltage sample circuit 210 comprises and is series at instituteState resistance R 2 and resistance R 1 between output VO and earth terminal GND, resistance R 2 and resistance R 1 itBetween connected node be the output of described feedback voltage sample circuit 210. In another embodiment, Fig. 2In PMOS transistor MP2 also replaceable be PNP bipolar transistor, this PNP bipolar transistorThe first link be emitter-base bandgap grading, its second link is colelctor electrode, its control end is base stage.
For the ease of understanding the present invention, below specifically introduce the work of the low difference voltage regulator shown in Fig. 2Principle.
In the time that described enable signal EN is the first logic level (or being called disable control signal), it makes controlTransistor 220 conductings processed, draw high the grid voltage of power tube MP5 to supply voltage VIN, thereby turn-offPower tube MP5, realizes and closes the low difference voltage regulator shown in Fig. 2, meanwhile, and this first logic levelGauge tap S1 is turn-offed, to cut off being connected of output capacitance C1 and output VO, can prevent like thisElectric charge on output capacitance C1 leaks electricity by resistance R 1, R2 and load LOAD (being powered circuit),To realize after low difference voltage regulator is closed, the charge number on output capacitance C1 can continue to be maintained workTime charge number.
In the time that described enable signal EN is the second logic level (or be called enable control signal), it makes to controlTransistor 220 turn-offs, and now, the grid voltage of power tube MP5 is subject to the output control of error amplifier EASystem, meanwhile, this second logic level makes gauge tap S1 conducting, to realize output capacitance C1 and outputVO is connected, and restarts low difference voltage regulator thereby realize.
In summary, due to when the low difference voltage regulator of closing shown in Fig. 2, on output capacitance C1Electric charge is not consumed, and therefore, in the time restarting, low difference voltage regulator does not need output capacitance C1 to mend yetCharging lotus, just can make the voltage on output capacitance C1 reach the needed operating voltage of load LOADVTR, can save in above-mentioned background technology like this, and low difference voltage regulator is constantly being closed and restartingIn journey (being service intermittent process), the extra energy consuming on output capacitance C1, thus further fallThe average power consumption of low system.
For fear of above-mentioned close with restarting process in, the output voltage VO of low difference voltage regulator goes outExisting overshoot or fluctuation, the low difference voltage regulator shown in Fig. 2 is in control end and the Enable Pin of gauge tap S1Between EN, be also provided with logic control circuit 230, the first input end of described logic control circuit 230 1 withEnable Pin EN is connected, and its second input 2 is connected with output VO, its 3rd input 3 and output electricityThe connected node V1 holding between C1 and gauge tap S1 is connected, its output and described gauge tap S1'sControl end is connected. When described enable signal EN is the second logic level, when and VO >=(V1-Vos), instituteState logic control circuit 230 gauge tap S1 conductings, otherwise gauge tap S1 turn-offs, wherein, V1 isThe magnitude of voltage of connected node V1, VO is the magnitude of voltage of output VO, Vos is predefined deviation electricityPress. That is to say, the effect of logic control circuit 230 is: when described enable signal EN is the first logic electricity(now, low difference voltage regulator is closed) at ordinary times, described logic control circuit 230 makes gauge tap S1Turn-off; In the time that described enable signal EN is the second logic level (now, low difference voltage regulator is restarted),If the voltage VO < (V1-Vos) of output, described logic control circuit 230 continues gauge tap S1Turn-off, if the voltage VO of output is increased to while approaching V1-Vos (be VO >=(V1-Vos)), described inLogic control circuit 230 gauge tap S1 conductings. In one embodiment, getting of described deviation voltage VosValue scope is: 0 < Vos < 50mV (millivolt).
In the embodiment shown in Figure 2, described logic control circuit 230 comprises comparator C omp, voltage sourceVOS and logical block 232. The first input end of described comparator C omp is connected with output VO, and it is years oldTwo inputs are connected with the negative pole of voltage source V OS, the positive pole of this voltage source V OS and described connected node V1Be connected, the output of comparator C omp is connected with an input of logical block 232; Described logic listAnother input of unit 232 is connected with Enable Pin EN, and output and the control of described logical block 232 are openedThe control end that closes S1 is connected, the magnitude of voltage that the magnitude of voltage of described voltage source V OS is above-mentioned deviation voltage.
In the specific embodiment shown in Fig. 2, the first input end of described comparator C omp is positive inputEnd, its second input is negative-phase input; Described logical block 232 comprises and door AND2; Enable signalThe first logic level of EN is low level, and its second logic level is high level. When enable signal EN is lowWhen level, PMOS transistor MP2 conducting, low difference voltage regulator is closed, meanwhile, enable signal ENFor low level control and the output output low level of door AND2, gauge tap S1 is turn-offed; When enabling letterWhen number EN is high level, PMOS transistor MP2 turn-offs, and low difference voltage regulator is restarted, if outputThe voltage VO < (V1-Vos) of end, comparator C omp output low level is low with door AND2 outputLevel, makes gauge tap S1 continue to turn-off, and approaches V1-Vos (if the voltage of output VO is increased toVO >=(V1-Vos)) time, comparator C omp exports high level, with door AND2 output high level, makesGauge tap S1 conducting, is connected with output VO thereby realize output capacitance C1, at this design deviation electricityOne of object of pressing Vos is to realize (now, output VO in the time that low difference voltage regulator is normally workedVoltage and the voltage of node V1 equate), comparator C omp still exports high level, opens to maintain to controlClose S1 conducting, thereby keep output capacitance C1 to be connected with output VO.
Please refer to shown in Fig. 3, it makes for the output VO in the low difference voltage regulator shown in Fig. 2Can become the startup oscillogram after high level by signal EN. As can be seen from Figure 3, when enable signal EN has just become heightWhen level, the voltage of output VO is 0V, lower than V1-Vos, and comparator C omp output low level, defeatedGo out capacitor C 1 and be cut off with being connected of output VO, now, low difference voltage regulator is to output VOCharging rate very fast; In the time that the voltage of output VO is increased to V1-Vos, comparator C omp output is highLevel, causes output capacitance C1 to be connected with output VO, and after this, voltage difference voltage regulator is to outputThe charging rate of VO is slack-off, until be elevated to the operating voltage VTR that equals load LOAD, and then, steadyDue to the magnitude of voltage of operating voltage VTR. Hence one can see that, in two of the object of this design deviation voltage Vos be,Can be in the restarting process of low difference voltage regulator, avoid output voltage VO to occur overshoot or fluctuation.
Above once pointed out, the control transistor 220 in Fig. 2 can be PMOS transistor MP2 or PNPBipolar transistor. It should be noted that, the control transistor 220 in Fig. 2 can be also NMOS crystalline substanceBody pipe or npn bipolar transistor, concrete, in the time that control transistor 220 is nmos pass transistor, instituteState the first link of controlling transistor 220 for draining, its second link is source electrode, and its control end is gridThe utmost point, corresponding, also need between Enable Pin EN and the grid of nmos pass transistor, set up phase inverter, withRealize aforesaid logic control; In the time that control transistor 220 is NPN bipolar transistor, described control crystalline substanceThe first link of body pipe 220 is colelctor electrode, and its second link is emitter-base bandgap grading, and its control end is base stage, rightAnswer, need between Enable Pin EN and the base stage of NPN bipolar transistor, set up phase inverter, to realizeAforesaid logic control. In addition, the load LOAD in Fig. 2 can be powered electricity for arm processor etc.Road.
In sum, the low difference voltage regulator in the present invention comprises power tube MP5, error amplifier EA,Feedback voltage sample circuit 210, control transistor 220, logic control circuit 230, Enable Pin EN, outputCapacitor C 1, gauge tap S1 and output VO. In the time that described enable signal EN is the first logic level,It makes to control transistor 220 conductings, and realize low difference voltage regulator and close, meanwhile, described logic controlCircuit 230 turn-offs based on this first logic level gauge tap S1, cuts off output capacitance C1 and output VOConnection; In the time that described enable signal EN is the second logic level, it makes to control transistor 220 and turn-offs, realNow restart low difference voltage regulator, if the voltage VO < (V1-Vos) of output, described logic controlCircuit 230 continues gauge tap S1 and turn-offs, and approaches V1-Vos (if the voltage VO of output is increased toVO >=(V1-Vos)) time, described logic control circuit 230 gauge tap S1 conductings, to realize output electricityHolding C1 is connected with output VO. Like this, between the low difference voltage regulator in the present invention not only can be savedIn the formula of the having a rest course of work, the upper extra energy consuming of output capacitance C1, the average power consumption of reduction system, andCan also avoid output voltage VO in restarting process to occur overcharging or fluctuating.
In the present invention, " connection ", be connected, word that expressions such as " companys ", " connecing " is electrical connected, as nothing especiallyIllustrate, represent direct or indirect electric connection.
It is pointed out that appointing of being familiar with that person skilled in art does the specific embodiment of the present inventionWhat changes the scope that does not all depart from claims of the present invention. Correspondingly, the model of claim of the present inventionEnclose and be also not limited only to previous embodiment.
Claims (10)
1. a low difference voltage regulator, is characterized in that, it comprises power tube, error amplifier, anti-Feedthrough voltage sample circuit, control transistor, Enable Pin, output capacitance, gauge tap and output VO,
The source electrode of described power tube is connected with power end, and its drain electrode is connected with output VO, its grid and mistakeThe output of poor amplifier is connected, and the second input of error amplifier is connected with reference voltage;
The input of described feedback voltage sample circuit is connected with output VO, described feedback voltage sampling electricityThe output on road is connected with the first input end of described error amplifier, and described feedback voltage sample circuit is used forSample described output VO voltage and export feedback voltage;
Transistorized the first link of described control is connected with power end, the grid of its second link and power tubeExtremely connected, its control end is connected with Enable Pin;
Described gauge tap and output capacitance are connected between described output VO and earth terminal successively, described inThe control end of gauge tap is connected with described Enable Pin, and described Enable Pin is used for receiving enable signal.
2. low difference voltage regulator according to claim 1, is characterized in that,
In the time that described enable signal is the first logic level, it makes to control transistor turns, by the grid of power tubePole tension is drawn high to supply voltage, thus switch-off power pipe, and low difference voltage regulator is closed in realization, meanwhile,This first logic level is turn-offed gauge tap, to cut off being connected of output capacitance and output VO;
In the time that described enable signal is the second logic level, it makes to control transistor and turn-offs, now, and power tubeGrid voltage be subject to the output control of error amplifier, meanwhile, this second logic level is led gauge tapLogical, be connected with output VO to realize output capacitance, restart low difference voltage regulator thereby realize.
3. low difference voltage regulator according to claim 2, is characterized in that, it also comprises connectionLogic control circuit between control end and the Enable Pin of gauge tap, first of described logic control circuitInput is connected with Enable Pin, and its second input is connected with output VO, its 3rd input and outputConnected node between electric capacity and gauge tap is connected, and its output is connected with the control end of described gauge tap,
In the time that described enable signal is the second logic level, if the voltage of output VO is less than V1-Vos,Described logic control circuit output control signal is so that gauge tap is turn-offed, if the voltage of output VO is largeIn the time equaling V1-Vos, described logic control circuit makes gauge tap conducting,
Wherein, V1 is the magnitude of voltage of the connected node between output capacitance and gauge tap, and Vos is for establishing in advanceFixed deviation voltage,
In the time that described enable signal is the first logic level, described logic control circuit output control signal so thatObtaining gauge tap turn-offs.
4. low difference voltage regulator according to claim 3, is characterized in that,
Described logic control circuit comprises comparator, voltage source and logical block, described comparator first defeatedEnter end and be connected with output VO, its second input is connected with the negative pole of voltage source, the positive pole of this voltage sourceBe connected with the connected node between output capacitance and gauge tap, one of the output of comparator and logical blockIndividual input is connected; Another input of described logical block is connected with Enable Pin, described logical blockOutput is connected with the control end of gauge tap, the voltage that the magnitude of voltage of described voltage source is described deviation voltageValue.
5. low difference voltage regulator according to claim 4, is characterized in that,
The span of described deviation voltage Vos is: 0 < Vos < 50mV.
6. low difference voltage regulator according to claim 4, is characterized in that,
Described power tube is PMOS transistor;
The first input end of described error amplifier is normal phase input end, and its second input is negative-phase input;
Described feedback voltage sample circuit comprises the resistance R 2 being series between described output VO and earth terminalWith resistance R 1, the connected node between resistance R 2 and resistance R 1 is the output of described feedback voltage sample circuitEnd.
7. low difference voltage regulator according to claim 6, is characterized in that,
Described control transistor is PMOS transistor, and transistorized the first link of described control is source electrode,Its second link is drain electrode, and its control end is grid; Or
Described control transistor is PNP bipolar transistor, and transistorized the first link of described control is for penetratingThe utmost point, its second link is colelctor electrode, its control end is base stage.
8. low difference voltage regulator according to claim 7, is characterized in that,
The first input end of described comparator is normal phase input end, and its second input is negative-phase input; InstituteStating logical block comprises and door; The first logic level of enable signal is low level, and its second logic level isHigh level.
9. low difference voltage regulator according to claim 3, is characterized in that,
Described control transistor is nmos pass transistor, and transistorized the first link of described control is drain electrode,Its second link is source electrode, and its control end is grid; Or
Described control transistor is NPN bipolar transistor, and transistorized the first link of described control is collectionElectrode, its second link is emitter-base bandgap grading, its control end is base stage.
10. an electric power system, is characterized in that, it comprises and is powered circuit and as arbitrary in claim 1-9Described low difference voltage regulator,
Described low difference voltage regulator is powered circuit supply by its output VO, described in be poweredCircuit is arm processor.
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| CN105159385B (en) * | 2015-09-25 | 2017-01-18 | 灿芯半导体(上海)有限公司 | Low-power-dissipation low-dropout voltage regulator |
| FR3092706A1 (en) | 2019-02-12 | 2020-08-14 | Stmicroelectronics (Grenoble 2) Sas | Power supply device |
| CN112732001A (en) * | 2021-04-01 | 2021-04-30 | 上海艾为微电子技术有限公司 | Low-power-consumption power supply circuit, method, chip and electronic equipment |
| KR20230104923A (en) | 2021-06-07 | 2023-07-11 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Earth Leakage Isolation for Low-Dropout Regulators |
| CN114115029A (en) * | 2021-11-19 | 2022-03-01 | 湖南省邮电规划设计院有限公司 | Intelligent power distribution controller and control method thereof |
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| CN202183059U (en) * | 2011-06-23 | 2012-04-04 | 上海集成电路研发中心有限公司 | Low-dropout linear voltage regulator |
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