CN104867863A - Manufacture Of Electronic Module - Google Patents
Manufacture Of Electronic Module Download PDFInfo
- Publication number
- CN104867863A CN104867863A CN201510067672.9A CN201510067672A CN104867863A CN 104867863 A CN104867863 A CN 104867863A CN 201510067672 A CN201510067672 A CN 201510067672A CN 104867863 A CN104867863 A CN 104867863A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- semiconductor chip
- contacting
- circuit board
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/77—Apparatus for connecting with strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
- H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/40227—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/404—Connecting portions
- H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
- H01L2224/40499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/4101—Structure
- H01L2224/4103—Connectors having different sizes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
- H01L2224/4105—Shape
- H01L2224/41051—Connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75314—Auxiliary members on the pressing surface
- H01L2224/75315—Elastomer inlay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/75981—Apparatus chuck
- H01L2224/75982—Shape
- H01L2224/75983—Shape of the mounting surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/77—Apparatus for connecting with strap connectors
- H01L2224/7725—Means for applying energy, e.g. heating means
- H01L2224/773—Means for applying energy, e.g. heating means by means of pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/77—Apparatus for connecting with strap connectors
- H01L2224/7725—Means for applying energy, e.g. heating means
- H01L2224/773—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/77313—Wedge
- H01L2224/77325—Auxiliary members on the pressing surface
- H01L2224/77328—Material of the auxiliary member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/77—Apparatus for connecting with strap connectors
- H01L2224/77981—Apparatus chuck
- H01L2224/77982—Shape
- H01L2224/77983—Shape of the mounting surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8314—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8412—Aligning
- H01L2224/84136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/84138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/842—Applying energy for connecting
- H01L2224/84201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84399—Material
- H01L2224/844—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/84438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/84447—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/8484—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9221—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92246—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92252—Sequential connecting processes the first connecting process involving a strap connector
- H01L2224/92255—Sequential connecting processes the first connecting process involving a strap connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Abstract
The invention relates to a method used for manufacturing an electronic module (L), especially a power electronic module (S1-S8). The method includes at least one semiconductor chip (3, 4) contacted with a contact of at least one lead frame (1). The upper side and the lower side of the semiconductor chip (3, 4) are provided with at least one electric interface (8, 9). Besides, the at least one lead frame (1) is in contact connection with at least one interface (8, 9). The electronic module can be manufactured with the method (S1-S8). The electronic module can be applied to the power electronic module.
Description
Technical field
The present invention relates to a kind of method for the manufacture of electronic module, particularly power electronics modules, described method comprises the contacting of at least one semiconductor chip and at least one lead frame, wherein, semiconductor chip side has at least one electrical interface on its underside respectively thereon.The present invention also relates to a kind of electronic module, described electronic module manufactures by means of described method.The present invention particularly can be applied on power electronics modules, and described power electronics modules has the semiconductor chip of at least one power semiconductor chip form.
Background technology
In power (electronics) module, the electrical connection to corresponding described power semiconductor chip is set up in the usual upside by power semiconductor chip or downside.Typically on upside, set up electrical connection, to produce to the electric current of the interface of module dynamic.What become known for setting up this electrical connection is aluminum conductor (heavy gauge wire or thin wire), described aluminum conductor be adhered on the one hand upside upper and be adhered to module-external on the other hand and/or inside joint face on.Also be well known that, set up described electrical connection by the bonding of (heavy gauge wire or thin wire) copper conductor, faciola bonding and the bonding of wire that forms with by alloy.Also have other connection solution, comprise such as according to so-called " SkiN " technology, sintering, the metallized plastic film of Semikron company.The feature of SkiN technology is to substitute bond wire by flexibility, structurized film, and on circuit boards, described circuit board has power electronic component fixed thereon to described thin film planar ground sintering.In addition, the bus-bar of the known welding be made up of blister copper.In addition, known so-called " SiPLIT " technology of Siemens company.
The shortcoming had in known interconnection technique is, using in uneven (such as by means of wire adhesion) interconnection technique, the wiring layer on the top be connected with chip surface can only difficulty cool.Smooth interconnection technique, the application of such as " SkiN " technology or " SiPLIT " technology spends relatively high in contrast in the mill, and in addition especially owing to spending high manufacturing step, such as structuring or metallization to be expensive.
Summary of the invention
The object of the invention is to, overcome the shortcoming of prior art at least in part, and particularly propose a kind of can transform simply and at an easy rate and can effectively cool for there is at least one electronic unit, particularly power electronic component, being the interconnection technique of electronic module of power semiconductor chip specially.
The feature of this object according to independent claims realizes.Preferred embodiment particularly can draw from dependent claims.
This object is realized by a kind of method for the manufacture of electronic module, described method comprises the contacting of at least one semiconductor chip and at least one lead frame, wherein, semiconductor chip is upper and have at least one electrical interface respectively on the side arranged on the other hand (below described side be not called " downside " with not limiting generality) its side (below described side be not called " upside " with not limiting generality), and at least one interface of one of side, particularly upside described in the direct contacting of at least one lead frame.
The advantage that described method has is, can manufacture simply and at an easy rate relative to known smooth interconnection technique, and can provide the highly stable, reliably and can the possibility of effective cooling of wiring or electrical connection relative to the interconnection technique of non-flat forms.Lead frame particularly can substitute the manufacture process of the whole bonding in the power model of usual non-flat forms and the complexity in such as SiPLIT.
At least one semiconductor chip can be power semiconductor chip.Electronic module then also can be called power electronics modules.An improvement project is that at least one semiconductor chip is power switch.An improvement project is also had to be that at least one semiconductor chip is IGBT, power MOSFET, power diode, thyristor, bidirectional thyristor etc.
Except at least one semiconductor chip, at least one other parts of module can also be connected with lead frame in a similar fashion, and at least one other parts described are such as electronic unit of at least one band shell, the distance piece, resistance, coil, electric capacity etc. that can conduct electricity.
Lead frame can be such as made up of copper or copper alloy.Lead frame usually can manufacture independently and be steerable circuit structure.
Semiconductor chip side and downside has at least one electrical interface respectively thereon, this can comprise especially: described semiconductor chip only side and downside has at least one electrical interface respectively thereon, that is, not there is the connection pin or little connection leg of drawing side.
An improvement project is, the electrical interface of semiconductor chip is smooth interface or join domain, such as contact area or contact pad, thus described electrical interface can especially easily contacting.The interface of plane or join domain can particularly be interpreted as and the corresponding recess of non-intrusive in protuberance, that is, be not connecting pin.Therefore, smooth join domain can have especially or form smooth contact-making surface, but is not limited to this.Smooth join domain also can be integrated in below insulator.
" directly " contact is interpreted as so a kind of contact especially, namely, in described contact, the interface of lead frame and semiconductor chip is connected to each other when not using bond wire or analog when not having other Connection Element, namely.But attached dose of increasing can be used when direct contacting, such as contact cream, solder or sinter layer.Increase attached dose to exist as articulamentum especially.
A structural scheme is, described method at least comprises the steps: that (i) provides (at least one) lead frame; (ii) by the upside contacting exemplarily chosen of (at least one) lead frame and at least one semiconductor chip; And (iii) by least one parts and the downside of lead frame and common circuit board contact are connected if desired.
Step (ii) is particularly including the contacting of at least one join domain at the upside place of semiconductor.For this situation, on upside, namely there is multiple join domain electrically isolated from one, lead frame can with the one or more contactings in described join domain, particularly also can with all join domain contactings.
Common circuit board in step (iii) can have the substrate of tabular especially, described substrate thereon or front side has at least one structurized can conductive layer (Lage), for at least one semiconductor at least one on the downside of contact.Structurized layer also can be called the wiring layer of conductor structure or bottom and such as have at least one conductor circuit.In addition, the parts that structurized layer can be other with at least one are connected and/or (such as passing through distance piece) is connected with lead frame.The contacting of circuit board is particularly including the contacting of structurized layer.
Common circuit board also can be called " substrate ", and the carrier of electric insulation then also can be called " insulating barrier ".Common circuit board can be DCB circuit board or IMS circuit board.This circuit board is such as because it effectively cooling can be particularly useful for the operation utilizing power electronic component.But common circuit board also can be DAB (" Direct Aluminum Bonded (direct aluminium bonding) ") circuit board, AMB (" Active Metal Brazing (active metal brazing) ") circuit board or also be such as common FR4 circuit board.
Therefore, in step (iii), lead frame can be connected with circuit board, and described lead frame has at least one electronic unit as common steerable unit mounted thereto.For this reason, circuit board can be arranged on and be equipped with on the lead frame of at least one electronic unit, and/or the lead frame of assembling can be settled on circuit boards.
The advantage of described structural scheme is, the upside of at least one semiconductor chip can with very high precision contacting semiconductor chip.This is advantageous particularly when multiple contact area and/or relatively little contact area are positioned on upside.Downside can with higher alignment tolerance by contacting when particularly only a contact area is positioned at herein.Described structural scheme such as can be used on igbt chip, and described chip has collector electrode interface on its underside, side has emitter interface thereon and additionally side has control interface, particularly gate pole interface thereon.
Control interface such as can medially or Central places, particularly with " central gate pole " arranged in form on upside.Described control interface alternatively can be arranged on avris (" edge gate pole ") or on the angle of upside (" side door pole ").
But other orders of electronic module combination in principle are also possible, such as, with at least one electronic unit wiring harness plate, and are then set on the circuit board of assembling by least one lead frame.
Another design is, step (ii) at least comprises the steps: that (iia) is to increase the contact area preset that attached dose is carried out bedding lead frame accordingly; And (iib) at least one interface of at least one electronic unit is arranged on corresponding contact area.The upside of electronic unit such as can have multiple interface area, and described interface area is connected by a contact area and at least one leadframe contact respectively.This design achieves especially simply installs.
Another design is, in step (ii) or (iib), use flip-chip (Flip-Chip) mounting technique.This achieve and assemble lead frame simply, reliably and exactly with at least one electronic unit.
A design is also had to be that step (iii) comprises by increasing attached dose, particularly by the contacting of the increasing attached dose identical with step (iia).This achieve comparatively unified and then better simply manufacture.Such as can by attached dose of increasing coating on circuit boards.
Increase attached dose such as to print by means of mould printing method.
In addition, a design is, increasing attached dose is agglomerated material or sintered material.But also can use other material in principle, such as soldering paste, energy electrically-conducting adhesive etc.
Also having one for the decision design simply manufactured is, when attached dose of increasing is agglomerated material, then the step (iv) of common sintering process is connected to step (iii).That is, in a procedure, the contact between at least one electronic unit and lead frame, the contact between at least one electronic unit and circuit board and-if present-contact (distance piece as necessary by intermediary element is such as conducted electricity) between realizing circuit plate and lead frame can not only be realized.
For can for the sintering process of unusual simple conversion preferably, described sintering process be sintering pressing process or has this sintering pressing process.At this, the sintering of agglomerated material realizes by applying sufficiently high pressure.Therefore can cancel high temperature, which avoid the cause thermal damage at least one electronic unit.In sintering pressing process, the unit of the compound be made up of circuit board, (multiple) electronic unit and lead frame can be given in suitable pressing mold.At this, in order to the power difference on averaging circuit plate and small height difference, pressure compensation material can be fed in pressing mold together.But sintering process is not limited to this, and such as also can be designed to sintering with no pressure or the other sintering with pressure.
Such as silver paste can be used as agglomerated material, such as exists as silver-colored sinter layer for increasing attached described silver paste.Described silver paste is particularly applicable to sinter the sintering during pressing process.Substitute or except silver paste, preformed silver pad (such as so-called " Preforms (precast body) ") can be used.
Substitute sintering, increase attached dose and also simply can be dried or harden, and/or first increase and at temperature liquefaction and then again solidify.Attached dose of this increasing can be such as solder or thermal conductance adhesive.
In addition, a design is, carries out with the step of electrical insulating material at least one section of the outside bedding lead frame of contact area between step (i) and (ii).Therefore, plane unexpectedly contacting lead frame can being avoided and can conduct electricity.In addition, can therefore extend or even avoid air gap.With the step of bedding electrical insulating material also can be step (i) and/or step (ii) step by step.
Electrical insulating material can such as be set up as filler, pigment, material, film or the thin layer that can spray or exist.
An improvement project is, with electrical insulating material then on contact area or be adjacent to contact area bedding lead frame.When making such as on the upside of electronic unit during center interface area contacting by means of described contact area, above-mentioned situation is such as useful.Then can be avoided by electrical insulating material: the portion's section connected with contact area can contact another interface area (such as emitter region) in contiguous described hub-interface region.Therefore have a design in addition, that is, with at least one section of electrical insulating material bedding lead frame, at least one section described can be positioned at the top of electronic unit.
Electrical insulating material can solidify in atmosphere.Described electrical insulating material can at ambient temperature or at the temperature increased, such as solidify in stove.Described solidification at the temperature do not increased avoids such as stove process, and the solidification at the temperature increased achieves solidification quickly.In addition described solidification can be carried out by means of ultraviolet etc.Lead frame can utilize completely crued electrical insulating material, partially cured electrical insulating material or in fact uncured electrical insulating material to be connected with at least one electronic unit.
Additionally or alternatively electrical insulating material can be applied at least one electronic unit and/or on circuit board on the position expected.
Can by increase attached dose of coating or its contact area of bedding and/or to prepare lead frame by arranging electrical insulating material for step (ii).
In addition, a design is, separated for lead frame step (v) is connected to step (iii) or step (iv).Therefore, lead frame can be divided into two or more conductor circuit.Described separation can such as be carried out by means of laser cutting.Lead frame can be understood as wire circuit group, described wire circuit group by-particularly thin-auxiliary contact pin be connected to each other.When being separated by lead frame, cut at least one auxiliary contact pin.
This object is also realized by a kind of electronic module, and described electronic module manufactures by means of foregoing method.This electronic module can be similar to described method construct and have identical advantage.
Accompanying drawing explanation
Afore-mentioned characteristics of the present invention, feature and advantage and realize its mode and method can clearly and clearly be understood by following sketch in conjunction with the embodiments, describe described embodiment by reference to the accompanying drawings in detail.At this for simple and clear object, element that is identical or phase same-action is provided with identical Reference numeral.
Fig. 1 illustrates according to one embodiment of the method for the invention according to flow chart;
Fig. 2 illustrates by means of electronic module made according to the method for the present invention with vertical view;
The electronic module of Fig. 3 in Fig. 2 shown in the end view by the first cross section shown in Fig. 2 is as sectional view; With
The electronic module of Fig. 4 in Fig. 2 shown in the end view by the first cross section shown in Fig. 2 is as sectional view.
Embodiment
For carrying out the possible flow chart of the method for the manufacture of the power electronics modules L shown in Fig. 2 to 4 shown in Fig. 1.
In first step S1, provide lead frame 1, described lead frame should form the upper wiring layer (see Fig. 2) of power electronics modules L.At this, lead frame 1 be a combination be made up of multiple wire circuit 2 or 2a to 2d, layer structure, first described wire circuit is connected to each other by thin auxiliary contact pin (not shown).Lead frame 1 is made up of copper or its alloy, and can be handled to self-supporting.Lead frame 1 can such as be created by copper sheet.
In second step S2, provide multiple electronic unit 3,4, namely in this as power semiconductor chip and other the electronic unit 4 such as power diode of igbt chip 3 form.Other electronic unit can be band shell and/or exist as chip or bare chip.
Electronic unit 3,4 just have interface area on its underside or on its underside respectively.Particularly igbt chip 3 has the interface area (not shown) for collector electrode (" collector electrode interface ") on 6 on the downside of it, and have on the upside 7 of described chip two join domains 8 and 9, namely for the central authorities of the gate pole (" central gate pole " 8) of corresponding igbt chip first interface region and electrically separated to it, for second interface area 9 around central gate pole 8 of the emitter (" emitter interface ") of corresponding IGBT 3.But except central gate pole 8, edge gate pole and side door pole such as can also be there is.The cross section III-III coming from Fig. 2 for describing Fig. 3 extends through central gate pole 8.The cross section IV-IV coming from Fig. 2 for describing Fig. 4 extends with central gate pole 8 perpendicular to cutting plane III-III with staggering.
Other parts, such as coil, resistance, the distance piece etc. that can conduct electricity also can be provided.The distance piece 10 of conduction, the contacting of such as square copper billet are also exemplarily also shown below.
In third step S3a, by with the contact area of the such as increasing attached dose of bedding lead frame 1 of silver-colored sintered paste (not shown) form.Alternatively or additionally, in third step S3b to increase the upper contact region 8,9 of attached dose of bedding electronic unit 3,4 and distance piece 10.
In the fourth step s 4, with electrical insulating material (not shown), such as filler in portion's section of the outside bedding lead frame 1 of contact area.Described portion section can be particularly such portion's section, and it extends in the manufacture state of power electronics modules L on the upside 7 of at least one electronic unit 3,4.
In the 5th step S5, such as, by compressing mutually, make the interface area 7,8 of the upside of the contact area of lead frame 1 and electronic unit 3,4 and be connected or contacting with distance piece 10.Particularly can carry out step S5 by means of use flip chip mounting technique.After carrying out step S5, electronic unit 3,4 and distance piece 10 combine with lead frame 1.
At this, lead frame 1 is connected for twice with each igbt chip 3, that is, to be connected and to be connected with emitter interface area 9 by least one other contact area by contact area with central gate pole 8.The portion's section being connected to the contact area with central gate pole 8 of lead frame 1 at least in its downside towards IGBT 3 on the top of emitter interface area 9 with electrical insulating material by bedding, therefore to stop electrical connection.
In addition, electronic unit 3,4 advantages first drawn with the contacting of lead frame 1 are, the central gate pole 8 of relative small size can with the contact area contacting belonging to high accuracy and lead frame 1, exactly, contacting is carried out with when precision higher compared with electronic unit 3,4 is first with circuit board and when then connecting with lead frame 1.
In following step S6, electronic unit 3, the downside 6 of 4 and distance piece 10 and common circuit board 11 contacting.Common circuit board 11 is DCB circuit boards, the layer 13 that described circuit version has the ceramic substrate 12 of tabular, the structurized of front side is made up of copper and the layer 14 be made up of copper of dorsal part.The layer 13 of front side is configured for electronic unit 3, and 4 and wiring layer, particularly the wire circuit structure of downside of distance piece 10.At this, the layer 13 of front side is divided into five region 13a to 13e electrically isolated from one.Refer to the layer 13 of described front side or the contacting of 13a to 13e with the contacting of circuit board 11 especially with being connected or being connected.At this, distance piece 10 is for the altimetric compensation between lead frame 1 and the layer 13 of front side, thus lead frame 1 does not need to be connected with the layer 13 of front side deviously.
In order to realize the contacting of mechanically stable with very little resistance, in following step S7, the element 1 to 14 connected before power electronics modules L stands to sinter pressing process.For this reason, described element 1 to 14 is given in suitable model (such as punch), is wherein selectively placed with pressure compensation film (not shown) in advance.Apply pressure in described model described element 1 to 14, therefore, sinter silver-colored sintered paste or silver-colored sinter layer (not shown) at least in part.The silver layer of sintering is remarkable mechanically stable, and obtains the adhesiveness of improvement compared with unsintered silver paste.Resistance and thermal resistance are minimum.
In following step S8, by means of incision auxiliary contact pin, lead frame 1 is separated into each conductor circuit 2a-2d.
Although the present invention is shown specifically in particular by shown embodiment and illustrates, and the present invention is not limited to this and can be derived other modification in the case without departing from the scope of protection of the present invention thus by those skilled in the art.
Therefore, the process steps shown in Fig. 1 does not need to carry out with described order.Such as step S2 can carry out after step S3a/S3b and/or S4.Step S4 also carried out before step S3a/S3b.
In general, as long as no being limited by term " just what a " clearly, such as, then " one ", " one " etc. are interpreted as odd number or plural number, are particularly interpreted as the meaning of " at least one " or " one or more ".
As long as no limiting clearly, numeral illustrates and also can comprise the numeral that provides exactly and comprise the common margin of tolerance.
Claims (12)
1. the method (S1-S8) for the manufacture of electronic module (L), particularly power electronics modules, described method comprises at least one semiconductor chip (3,4) with the contacting of at least one lead frame (1), wherein
Described semiconductor chip (3,4) is gone up in the upside (7) of described semiconductor chip and on the downside (6) of described semiconductor chip, is had the interface (8,9) of at least one electricity respectively, and
The described interface (8,9) of one of direct contacting (S5) described side of lead frame described at least one (1).
2. method according to claim 1 (S1-S8), wherein, described method (S1-S8) at least comprises the steps:
I () provides (S1) described lead frame (1);
(ii) by described upside (7) contacting (S5) of described lead frame (1) with at least one semiconductor chip (3,4); And
(iii) by semiconductor chip described at least one (3,4) and described downside (6) and common circuit board (11) contacting (S6) of described lead frame (1).
3. method according to claim 2 (S1-S8), wherein, step (ii) at least comprises the steps:
(iia) to increase the contact area preset of the attached dose of described lead frame of bedding (S3a) (1) accordingly; And
(iib) by semiconductor chip described at least one (3,4) at least one described in interface (8,9) be arranged on corresponding contact area place.
4. method according to claim 3 (S1-S8), wherein, uses flip chip mounting technique in step (iib).
5. the method (S1-S8) according to any one of Claims 2 or 3, wherein, step (iii) comprises the contacting (S6) by increasing attached dose.
6. the method (S1-S8) according to the combination of claim 3 or 4 and claim 5, wherein, attached dose of described increasing is agglomerated material, and the step (iv) of common sintering pressing process (S7) is connected to step (iii).
7. the method (S1-S8) according to any one of claim 2 to 6, wherein, carry out between step (i) and (ii) with the step (S4) of electrical insulating material at least one section of lead frame (1) described in the outside bedding of described contact area.
8. method according to claim 7 (S1-S8), wherein, with at least one section of lead frame (1) described in described electrical insulating material bedding, at least one section described can be positioned at the top of semiconductor (3).
9. the method (S1-S8) according to any one of claim 2 to 8, wherein, described lead frame (1,2,2a-2d) separated step (v) is connected to step (iii) or step (iv).
10. according to method in any one of the preceding claims wherein (S1-S8), wherein, at least one electronic unit comprises at least one semiconductor chip (3,4), particularly at least one power switch (3).
11. methods (S1-S8) according to any one of claim 2 to 10, wherein, described circuit board (11) is DCB circuit board or IMS circuit board.
12. 1 kinds of electronic modules (L), described electronic module manufactures by means of according to method in any one of the preceding claims wherein (S1-S8).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102014203306.3 | 2014-02-25 | ||
DE102014203306.3A DE102014203306A1 (en) | 2014-02-25 | 2014-02-25 | Manufacture of an electronic module |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104867863A true CN104867863A (en) | 2015-08-26 |
CN104867863B CN104867863B (en) | 2018-07-10 |
Family
ID=53782414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510067672.9A Active CN104867863B (en) | 2014-02-25 | 2015-02-09 | The manufacture of electronic module |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN104867863B (en) |
DE (1) | DE102014203306A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108112217A (en) * | 2016-11-24 | 2018-06-01 | 现代自动车株式会社 | For the inverter structure of vehicle |
CN109863595A (en) * | 2016-10-06 | 2019-06-07 | 柏狮电子(德国)有限公司 | For electronic component, in particular for the shell of semiconductor chip |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11476127B2 (en) | 2018-03-23 | 2022-10-18 | Mitsubishi Materials Corporation | Manufacturing method of electronic-component-mounted module |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070200250A1 (en) * | 2004-08-24 | 2007-08-30 | Infineon Technologies Ag | Semiconductor Device with a Semiconductor Chip Using Lead Technology and Method of Manufacturing the Same |
US20070246808A1 (en) * | 2005-03-16 | 2007-10-25 | Henrik Ewe | Power semiconductor module having surface-mountable flat external contacts and method for producing the same |
CN101842887A (en) * | 2007-09-04 | 2010-09-22 | 西门子公司 | Method for the production and contacting of electronic components by means of a substrate plate, particularly a DCB ceramic substrate plate |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102010044709B4 (en) * | 2010-09-08 | 2015-07-02 | Vincotech Holdings S.à.r.l. | Power semiconductor module with metal sintered connections and manufacturing process |
DE102012215656B4 (en) * | 2012-09-04 | 2015-05-21 | Semikron Elektronik Gmbh & Co. Kg | Method for producing a power semiconductor module |
-
2014
- 2014-02-25 DE DE102014203306.3A patent/DE102014203306A1/en active Pending
-
2015
- 2015-02-09 CN CN201510067672.9A patent/CN104867863B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070200250A1 (en) * | 2004-08-24 | 2007-08-30 | Infineon Technologies Ag | Semiconductor Device with a Semiconductor Chip Using Lead Technology and Method of Manufacturing the Same |
US20070246808A1 (en) * | 2005-03-16 | 2007-10-25 | Henrik Ewe | Power semiconductor module having surface-mountable flat external contacts and method for producing the same |
CN101842887A (en) * | 2007-09-04 | 2010-09-22 | 西门子公司 | Method for the production and contacting of electronic components by means of a substrate plate, particularly a DCB ceramic substrate plate |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109863595A (en) * | 2016-10-06 | 2019-06-07 | 柏狮电子(德国)有限公司 | For electronic component, in particular for the shell of semiconductor chip |
CN109863595B (en) * | 2016-10-06 | 2023-07-18 | 柏狮电子(德国)有限公司 | Housing for electronic components, in particular for semiconductor chips |
CN108112217A (en) * | 2016-11-24 | 2018-06-01 | 现代自动车株式会社 | For the inverter structure of vehicle |
CN108112217B (en) * | 2016-11-24 | 2021-03-05 | 现代自动车株式会社 | Inverter structure for vehicle |
Also Published As
Publication number | Publication date |
---|---|
CN104867863B (en) | 2018-07-10 |
DE102014203306A1 (en) | 2015-08-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9530707B2 (en) | Semiconductor module | |
US9966327B2 (en) | Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device | |
JP4438489B2 (en) | Semiconductor device | |
CN105765716B (en) | Power semiconductor modular and composite module | |
CN105612613B (en) | Semiconductor device | |
US20120061815A1 (en) | Power semiconductor module having sintered metal connections, preferably sintered silver connections, and production method | |
US20110100681A1 (en) | Substrate-mounted circuit module having components in a plurality of contacting planes | |
US20100134979A1 (en) | Power semiconductor apparatus | |
JP6319137B2 (en) | Semiconductor device and manufacturing method thereof | |
CN107078127B (en) | Power semiconductor device and method for manufacturing the same | |
JP6358129B2 (en) | Power converter | |
US20120044656A1 (en) | Electronic package structure and method for making the same | |
US9324684B2 (en) | Semiconductor device and manufacturing method thereof | |
US10249558B2 (en) | Electronic part mounting heat-dissipating substrate | |
US10763244B2 (en) | Power module having power device connected between heat sink and drive unit | |
US9579746B2 (en) | Thermocompression bonding structure and thermocompression bonding method | |
JPH11204724A (en) | Power module | |
JP7196047B2 (en) | ELECTRICAL CIRCUIT, POWER CONVERTER, AND METHOD OF MANUFACTURING ELECTRICAL CIRCUIT | |
WO2019064775A1 (en) | Semiconductor device and production method therefor | |
JP2021521628A (en) | Power modules and how to manufacture power modules | |
CN105814682A (en) | Semiconductor device | |
CN104867863A (en) | Manufacture Of Electronic Module | |
WO2022123870A1 (en) | Electrical circuit body, power conversion device, and electrical circuit body manufacturing method | |
JP5201085B2 (en) | Semiconductor device | |
JP6948855B2 (en) | Power semiconductor device and power conversion device using it |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |