CN104852750A - Data stream processing circuit used for short wave positioning - Google Patents
Data stream processing circuit used for short wave positioning Download PDFInfo
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- CN104852750A CN104852750A CN201510187195.XA CN201510187195A CN104852750A CN 104852750 A CN104852750 A CN 104852750A CN 201510187195 A CN201510187195 A CN 201510187195A CN 104852750 A CN104852750 A CN 104852750A
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Abstract
The present invention discloses a data stream processing circuit used for short wave positioning. The circuit comprises a radio frequency unit, an ADC sampling unit, an FPGA unit and a CPU unit, which are connected in turn, wherein an input end of the radio frequency unit is connected with an output end of a short wave antenna. Through direct radio frequency low-pass sampling of signals, a radio frequency front end analog circuit may be simplified, and the cost is lowered. A large part of the signals may be processed in a numeric field, analog filed influences are reduced, and the performance is raised.
Description
Technical field
The invention belongs to shortwave field of locating technology, be specifically related to a kind of Data Stream Processing circuit for shortwave location.
Background technology
Radio monitoring whether measures radio station according to the program specified and the project work appraised and decided for reaching, search radio interference source and illegal signals source, that measures radio-frequency spectrum takies situation, utilizes radio monitoring equipment and related software to implement monitoring, parameter measurement and feature identification, target localization, measurement of electromagnetic environment etc. to radio signal.Wherein, be one of Core Feature of radio monitoring to the location in radio interference and unknown signal source.Current shortwave field, positioning equipment is bulky, and antenna field is taken up an area wide, and the analog receiver that many employings are traditional, adopts multistage mixing system, easily causes local oscillator leakage, there is IQ channel imbalance, signal to noise ratio declines, and filter exists passband ripple and nonlinear problem; And system connects complicated, Operation and Maintenance difficulty; And it is higher for the coherence request of equipment and antenna; Traditional monitoring means can not meet current for device miniaturization, convenient, flexible and high-precision location requirement.And traditional data channel adc data sampling rate is lower, the not temporary mechanism of data, namely Transmission is lost, and cannot ensure contiguity and the validity of data.And for digital signal many employings digital filtering chip and the digital down converter of ADC sampling, the flexibility of the signal transacting that cannot realize.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of Data Stream Processing circuit for shortwave location.
For achieving the above object, technical scheme of the present invention is achieved in that
The embodiment of the present invention provides a kind of Data Stream Processing circuit for shortwave location, and this circuit comprises the radio frequency unit, ADC sampling unit, FPGA unit, the CPU element that connect successively, and the input of described radio frequency unit is connected with the output of short-wave antenna.
In such scheme, described radio frequency unit comprises band pass filter, LNA LNA, AGC automatic gain amplifier, ADC match circuit; Radiofrequency signal from short-wave antenna is linked into band pass filter, signal after bandpass filtering is linked into LNA and is with noise to carry out signal amplification process, described AGC automatic gain amplifier further adjusts amplification to the signal from LNA LNA, then inputs to after ADC match circuit carries out impedance transformation and anti-aliasing filter and exports to ADC sampling unit.
In such scheme, ADC sampling unit is made up of chip U16, the chip model of described U16 is AD9642BCPZ, 29th, 30 pins of described U16 chip access the signal from radio frequency unit, and the digital difference signal that the 4th, 5,6,7,9,10,11,12,13,14,15,16,18,19 pins export exports to FPGA unit.
In such scheme, described FPGA unit comprises DDR buffer unit, FPGA data processing unit, too net debugging interface, and described DDR buffer unit is connected with FPGA data processing unit, and described FPGA data processing unit is connected with Ethernet debugging interface; Described Ethernet debugging interface is connected by IFC interface with between CPU element.
In such scheme, described CPU element comprises CPU processor unit, PHY unit, SATA hard disc unit, IFC unit, DDR buffer unit, EPLD Interface Expanding unit; Described CPU processor unit is connected with the Ethernet debugging interface of FPGA unit, and described CPU processor unit is connected with PHY unit, SATA hard disc unit, IFC unit, DDR buffer unit, EPLD Interface Expanding unit respectively.
Compared with prior art, beneficial effect of the present invention:
The present invention, by the direct radio frequency low pass sampling to signal, can simplify radio-frequency front-end analog circuit, reduce costs; Also by the process of most of signal at numeric field, analog domain impact can be reduced, improves performance.The wide ADC device of high speed multidigit be system band in data acquisition, dynamic range, sensitivity enhancement provide guarantee; FPGA provides the processing hardware platform of digital signal in programmable band flexibly, by corresponding digital signal processing algorithm and hardware design technique, can realize filtering and the down-converted of digital signal easily, thus obtain required base band data; And tcp data segment adopts PCIE interface and FPGA to carry out data interaction, ensure that the transmission rate of data, adopt CPU to carry out data temporary storage and forwarding mechanism, ensure continuity and the validity of data.
Accompanying drawing explanation
The connection diagram of a kind of Data Stream Processing circuit for shortwave location that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 is the connection diagram of the radio frequency unit in the present invention;
Fig. 3 is the band pass filter of radio frequency unit in the present invention and the circuit diagram of LNA low noise amplifier;
Fig. 4 is the circuit diagram of the AGC automatic gain amplifier of radio frequency unit in the present invention;
Fig. 5 is the circuit diagram of the ADC match circuit of radio frequency unit in the present invention;
Fig. 6 is the circuit diagram of the ADC sampling unit in the present invention;
Fig. 7 is the connection diagram of FPGA unit in the present invention;
Fig. 8 is the circuit diagram of the DDR buffer unit of FPGA unit in the present invention;
Fig. 9 is the circuit diagram of the too net debugging interface of FPGA unit in the present invention;
Figure 10 is the connection diagram of CPU element in the present invention;
Figure 11 is the circuit diagram of the PHY unit 402 of CPU element in the present invention;
Figure 12 is the circuit diagram of the IFC unit 404 of CPU element in the present invention;
Figure 13 is the circuit diagram of the DDR buffer unit of CPU element in the present invention;
Figure 14 is the circuit diagram of the EPLD Interface Expanding unit of CPU element in the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
The embodiment of the present invention provides a kind of Data Stream Processing circuit for shortwave location, as shown in Figure 1, this circuit comprises the radio frequency unit 1, ADC sampling unit 2, FPGA unit 3, the CPU element 4 that connect successively, and the described input of radio frequency unit 1 is connected with the output of short-wave antenna.
As shown in Figure 2, described radio frequency unit 1 comprises band pass filter 101, LNA low noise amplifier 102, AGC automatic gain amplifier 103, ADC match circuit 104; Radiofrequency signal from short-wave antenna is linked into band pass filter 101, signal after bandpass filtering is linked into LNA and is with noise 102 to carry out signal amplification process, described AGC automatic gain amplifier 103 further adjusts amplification to the signal from LNA LNA 102, then inputs to after ADC match circuit 104 carries out impedance transformation and anti-aliasing filter and exports to ADC sampling unit 2.
As seen in figures 3-5, described band pass filter 101 is made up of chip U7, and the model of described U7 is BPF-E15, and the 18th pin of described U7 accesses the radiofrequency signal from short-wave antenna, and filtered radiofrequency signal is exported to LNA LNA 102 by the 9th pin; Described LNA LNA 102 is made up of chip D2, and its chip model is ADC8432, and the 1st pin of described D2 accesses the signal from described U7, and its 17th and the 22nd pin exports and passes through the difference radio-frequency signal of amplification to VGA automatic gain amplifier 103; Described VGA automatic gain amplifier 103 is made up of chip D11, its chip model is AD8370ARE, 1st and the 16th pin of described D11 receives the difference radio-frequency signal from LNA LNA 102, and the radiofrequency signal of amplifying through gain is exported to ADC match circuit 104 by the 8th and the 9th pin; Described ADC match circuit 104, for carrying out impedance matching and anti-aliasing filter, receives the signal from VGA automatic gain amplifier 103 by pin VGA1_OUT-and VGA1_OUT+, signal RX1_ADCIN-and RX1_ADCIN+ is exported to ADC simultaneously and adopts 2.
As shown in Figure 6, described ADC sampling unit 2, for carrying out digital sample to corresponding radio frequency analog signal, is converted to the digital signal of two-forty, is transferred to FPGA unit 3; Described ADC sampling unit 2 is made up of chip U16, the chip model of described U16 is AD9642BCPZ, 29th, 30 pins of described U16 chip access the signal from radio frequency unit 1, and the digital difference signal that the 4th, 5,6,7,9,10,11,12,13,14,15,16,18,19 pins export exports to FPGA unit 3.
Described ADC sampling unit 2, corresponding short frequency scope is 2MHz---30MHz, and signal bandwidth is 10KHz, according to nyquist sampling theorem and bandpass sample theory, and corresponding dynamic range requirement, choose the sampling rate of 125MHz; Dynamic range due to input signal is 70dBm, according to formula S NR=6.02*N+1.76 (1), and considers certain noise coefficient and dynamic margin, selects the ADC of 14; And in view of sampling bandwidth is close to 30MHz, according to Nyquist first Sampling Theorem, in order to provide the processing gain of numerical portion, reduce quantizing noise, alleviate the complexity of frequency overlapped-resistable filter, strengthen useful signal frequency spectrum and other can distance between aliasing signal, over-sampling is adopted to signal, selects 125MHz as the sample frequency of ADC.
As shown in Figure 7, described FPGA unit 3 comprises DDR buffer unit 301, FPGA data processing unit 302, too net debugging interface 303, described DDR buffer unit 301 is connected with FPGA data processing unit 302, and described FPGA data processing unit 302 is connected with Ethernet debugging interface 303; Described Ethernet debugging interface 303 is connected by IFC interface with between CPU element 4.
Described FPGA unit 3 carries out feature extraction by receiving from the digital signal of ADC, leaches the data of corresponding band, and carries out down-converted to it, thus obtain IQ base band data, transfer data to CPU element 4 by PCIE interface.
As shown in Figure 8, described DDR buffer unit 301 is made up of chip U8, and its chip model is K4B2G0846C; Its major function is that the data of FPGA data processing unit 302 carry out buffer memory, and its K3, L7 (DD3_A<0..14>) pin is connected with FPGA data processing unit 302.
As shown in Figure 9, described Ethernet debugging interface 303 is made up of chip U1, and its chip model is 88E1111_117TFBGA, and it is as the external debugging interface of FPGA data processing unit 303.
Described FPGA data processing unit 302 is made up of chip D4, and its chip model is EP2AGX65DF29I3N; For carrying out FFT conversion to sampled data, extract the frequency domain data of corresponding frequency, by ADC interface B15, C16 ... (ADC_DA12 ... 00) data sampling completed between ADC sampling unit 2 transmits; And corresponding data are issued CPU element 4 processed by its PCIE interface AH23, AG23, AF24, AE24 (PCIE_TX1_N, PCIE_TX1_P, PCIE_RX1_N, PCIE_RX1_P); And its J22, K22, K24, H22 (ASD0, DATA0, DCLK, NCS0) are as its AS start-up loading interface; And the jtag interface of L24, H24, L23, J23 (FPGA_TCLK, TDI, TDO, TMS) pin is as FPGA on-line debugging interface, and and by IFC interface C4, D4 ... between CPU element 4. (IFC_AD<23..0>) pin exchanges some control commands, as information such as frequency configuration, VGA gain controls.
As shown in Figure 10, described CPU element 4 comprises CPU processor unit 401, PHY unit 402, SATA hard disc unit 403, IFC unit 404, DDR buffer unit 405, EPLD Interface Expanding unit 406; Described CPU processor unit 401 is connected with the Ethernet debugging interface 303 of FPGA unit 3, and described CPU processor unit 401 is connected with PHY unit 402, SATA hard disc unit 403, IFC unit 404, DDR buffer unit 405, EPLD Interface Expanding unit 406 respectively.
Described CPU element 4 is made up of CPU processor unit 401, PHY unit 402, SATA hard disc unit 403, IFC unit 404, DDR buffer unit 405, EPLD Interface Expanding unit 406; Described CPU processor unit 401 is for carrying out storage and the transmission of data, especially by the sampled signal of PCIE interface from FPGA, and by data temporary storage in SATA hard disc, and data packing is sent to host computer by PHY unit 402 interface, described packet is walked VPN passage by cable network or 3G router and is sent; Wherein IFC Bus Interface Unit 404 mainly plays more mutual control and state informations with FPGA unit 3; DDR buffer unit 405 mainly plays and starts cushioning effect to the deal with data of CPU.
Described CPU processor unit 401 is made up of chip D7, and its model is P1010XTENCDR; Be connected with FPGA unit 3 by PCIE interface Y10, AA10.. (PCIE_TX1_P, PCIE_TX1_N, PCIE_RX1_P, PCIE_RX1_N); By SGMII Ethernet interface AR15, Y14 ... (SGMII3, SGMII2) is connected with Ethernet interface unit 402; By IFC interface P21, R22 ... (IFC<0..15>) pin is connected with IFC Bus Interface Unit 404; By passing through corresponding ddr interface K4, M3 ... (DDR3_D1<0..31>) be connected with DDR buffer unit 405; By IFC controller, UART interface, SPI interface ... .. pin is connected with EPLD Interface Expanding unit 406.
As shown in figure 11, described PHY unit 402 is made up of U4 and U6, its model is all VSC8221XHH, by K9, K10 ... (SGMII2SGMII3) be connected with CPU processor unit 401, mainly the SGMII signal of network layer be converted to physical layer signal and export.SATA hard disc unit 403, primarily of SATA hard disc composition, is connected with CPU processor unit 401 by general-purpose interface, mainly carries out buffer memory to data.
As shown in figure 12, described IFC unit 404 is made up of chip U11, U14, U17, and wherein the model of the model of U11 to be the model of 74ALVT16373, U14 be SN74CBT16211DGGR, U17 is JS28F256M29EVL.U11 is by the 26th, 27 ... with the 37th, 38 ... pin (IFC_AD<0...15>), U14 by the 11st, 13.... pin (IFC_AD<16..23>), U17 is by the 35th, 37 ... (IFC_AD<15..0>), CPU processor unit 401 connects respectively, for carrying out the multiplexing and start-up loading of distribution to bus; In addition U11 by the 2nd, 3.... (IFC_ADDR<0..15>), and the 45th, 43 of U14 the ... pin (IFC_ADDR<16..23>), is connected with chip U17 respectively.
As shown in figure 13, described DDR buffer unit 405 is by chip U10, U12, U26, U18 forms, its model is all K4B2G0846C, U10 is by K3, L7 ... pin (DDR3_A<0..14>), B3, C7 ... pin (DDR3_DQ<0...7>), J2, K8, J3 pin (DDR3_BA0, BA1, BA2, ) (etc. the pin of U10 chip circumference, and its with three chips be connected with the ddr interface of CPU, 4 DDR chips have public pin as DDR3_A, and respective pin is as DDR3_DQS0 ... 3 grades are connected with CPU processor unit 401 respectively.
As shown in figure 14, described EPLD Interface Expanding unit 406, it is formed primarily of chip D6, and chip model is LCMXO1200C-3FTN256C.By B3, D6 ... (IFC_AD<24..0>) pin, A13, D13, E13, F15 pin (SPI_CLK, SPI_MISO, SPI_CS0_N, SPI_MOSI) connects with CPU processor unit 401, play and IFC bus is resolved, and SPI Interface Expanding is become multiple SPI interface.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (5)
1. the Data Stream Processing circuit for shortwave location, it is characterized in that, this circuit comprises the radio frequency unit (1), ADC sampling unit (2), FPGA unit (3), the CPU element (4) that connect successively, and the input of described radio frequency unit (1) is connected with the output of short-wave antenna.
2. the Data Stream Processing circuit for shortwave location according to claim 1, is characterized in that: described radio frequency unit (1) comprises band pass filter (101), LNA LNA (102), AGC automatic gain amplifier (103), ADC match circuit (104); Radiofrequency signal from short-wave antenna is linked into band pass filter (101), signal after bandpass filtering is linked into LNA and is with noise (102) to carry out signal amplification process, described AGC automatic gain amplifier (103) further adjusts amplification to the signal from LNA LNA (102), then inputs to after ADC match circuit (104) carries out impedance transformation and anti-aliasing filter and exports to ADC sampling unit (2).
3. the Data Stream Processing circuit for shortwave location according to claim 1 and 2, it is characterized in that: ADC sampling unit (2) is made up of chip U16, the chip model of described U16 is AD9642BCPZ, 29th, 30 pins of described U16 chip access the signal from radio frequency unit (1), and the digital difference signal that the 4th, 5,6,7,9,10,11,12,13,14,15,16,18,19 pins export exports to FPGA unit (3).
4. the Data Stream Processing circuit for shortwave location according to claim 3, it is characterized in that: described FPGA unit (3) comprises DDR buffer unit (301), FPGA data processing unit (302), too net debugging interface (303), described DDR buffer unit (301) is connected with FPGA data processing unit (302), and described FPGA data processing unit (302) is connected with Ethernet debugging interface (303); Described Ethernet debugging interface (303) is connected by IFC interface with between CPU element (4).
5. the Data Stream Processing circuit for shortwave location according to claim 4, is characterized in that: described CPU element (4) comprises CPU processor unit (401), PHY unit (402), SATA hard disc unit (403), IFC unit (404), DDR buffer unit (405), EPLD Interface Expanding unit (406); Described CPU processor unit (401) is connected with the Ethernet debugging interface (303) of FPGA unit (3), and described CPU processor unit (401) is connected with PHY unit (402), SATA hard disc unit (403), IFC unit (404), DDR buffer unit (405), EPLD Interface Expanding unit (406) respectively.
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| CN201510187195.XA CN104852750A (en) | 2015-04-20 | 2015-04-20 | Data stream processing circuit used for short wave positioning |
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| CN201510187195.XA CN104852750A (en) | 2015-04-20 | 2015-04-20 | Data stream processing circuit used for short wave positioning |
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Application publication date: 20150819 |