CN104835535B - A kind of solid-state disk adaptive error correction method and system - Google Patents
A kind of solid-state disk adaptive error correction method and system Download PDFInfo
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Abstract
The invention discloses adaptive LDPC error correction methods inside a kind of solid-state disk, including (1) initialization：Solid-state disk carries out block erasing operation before input data, and initializes the error correcting code identifier of all erasing blocks；(2) solid-state disk adaptive error correction coding：Coding generation code word is carried out to the initial data of write-in；(3) solid-state disk decoding process, including：(3.1) read operation is determined whether, if read operation then turns to (3.2), is otherwise terminated；(3.2) the error correcting code identifier B of block i where reading page is judgediWhether it is 0；(3.3) if BiFor 0, then the weak LDPC code of all pages of uses carries out error correction in block i；(3.4) the adaptive error correcting code handover operation of solid-state disk；(3.5) if BiFor 1, then the strong LDPC code of all pages of uses carries out error correction in block i.The present invention is applied to solid-state disk field of error correction, and lifting LDPC error-correcting performances give full play to the reliability with data storage.
Description
Technical field
The invention belongs to solid-state disk error correcting technique field, in particular it relates to which a kind of solid-state disk adaptive error correction method is with being
System.
Background technology
With the popularization of various electronic equipments in daily life, solid-state disk is widely used as a kind of storage device, is protected
The safety of data, which seems, in card solid-state disk becomes more and more important.How error correcting code as the important measures that guarantee data security plays maximum
Efficiency is extremely important.
Flash chip manufacturing process inside solid-state disk has evolved to 10 nanometers of level, it is meant that inside flash chip
Unit size it is less and less, noise also accordingly increases the error correcting code, it is necessary to more powerful.Flash chip has multiple structure sheafs
Secondary composition, minimum read/write unit are page (Page), and multiple pages form a block (Block).Flash chip is before data are write
Erasing operation is first carried out, erasure unit is block.Block after erasing turns into white space, can write the data message of correlation.
Error correcting code decoding process is had to pass through when reading data from flash memory, to ensure that the data read are reliable data.If data
There is mistake, then carry out error correction correction with error correcting code.In addition, it is also different in the noise jamming that different times flash chip is subject to,
Thus corrupt data rate is also different.Under universal law, the flash chip error rate of early stage is very low, to the later stage with erasable number
Increase, the growth of data retention over time, corrupt data rate also increases accordingly.
Low density parity check code (Low-Density Parity-Check code, LDPC) has powerful error correction energy
Power.LDPC is mainly made up of encoder and decoder.Encoder is responsible for the data for writing flash memory carrying out coding generation LDPC code
Word.LDPC code word is made up of initial data and LDPC check informations.Decoder is then responsible for entering row decoding error correction to LDPC code word.Translate
Code device mainly has two kinds of result outputs：First, successfully decoded, illustrating the data of output does not have mistake；Second, decoding failure, explanation
Ldpc decoder can not correct the mistake in LDPC code word, and the data of output contain error message.Different LDPC code rates have
Different error-correcting performances, code check is higher, and error correcting capability is weaker.High code rate LDPC code is as weak LDPC code, and its error correcting capability is not as low
Code rate LDPC code.Under normal circumstances, solid-state disk uses the LDPC code of most strong error correcting capability, to ensure solid-state disk in the worst cases
Data safety, most strong LDPC error correcting codes error correcting capability redundancy phenomena thus be present, can also influence the readwrite performance of solid-state disk,
Cause the waste of solid-state disk error correction energy consumption.
The content of the invention
The purpose of the present invention is different according to solid-state disk internal flash chip data error situation, using suitable error correcting capability
LDPC code carry out error correction, reach the purpose for improving LDPC code error correction efficiency, reduce the redundancy of single LDPC code error-correcting performance, together
The reading performance of Shi Tigao solid-state disks simultaneously reduces its decoding energy consumption.
To achieve these goals, the present invention constructs a kind of method of automatically switch weak LDPC code and strong LDPC code, subtracts
Lack the only redundancy of caused LDPC error-correcting performances using strong LDPC code, while reduce the error correction that solid-state disk uses LDPC code
Energy consumption, and the degree of accuracy that solid-state disk carries out error correction using different LDPC codes is improved, it ensure that the reliable of solid-state disk internal data
Property.The present invention is using high code rate LDPC code as weak LDPC code, and low code rate LDPC code is as strong LDPC code.
According to one aspect of the present invention, there is provided a kind of solid-state disk adaptive error correction method, comprise the following steps：
(1) initialize：Solid-state disk carries out block erasing operation before input data, to write data, and initializes all
Wipe the error correcting code identifier B of blocki=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erasing block；
(2) solid-state disk adaptive error correction coding, including：
(2.1) when one page initial data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code1It is right
Initial data R is encoded to obtain code word C1=R × G1, code word C1Remove initial data R and obtain weak LDPC code check information P1；
(2.2) by the generator matrix G of strong LDPC code2Generation code word is encoded to one page initial data R
C2=R × G2, code word C2Remove initial data R and obtain strong LDPC code check information P2；
(2.3) one page initial data R and P1, P2Form code word C=(R, P of one page1, P2)；
(2.4) by the code word C write-in flash chips of generation；
(3) solid-state disk decoding process, including：
(3.1) read operation is determined whether, if read operation then turns to (3.2), is otherwise terminated；
(3.2) the error correcting code identifier B of block i where reading page is judgediWhether it is 0；
(3.3) if BiFor 0, then the weak LDPC code of all pages of uses carries out error correction in block i；
(3.4) the adaptive error correcting code handover operation of solid-state disk, including：
One page is failed using weak LDPC code error correction in (3.4.1) such as fruit block i, assignment block i error correcting code identifier Bi=1,
And go to step (3.5)；
(3.4.2) after such as fruit block i carries out error correction using strong LDPC code, as fruit block i is wiped free of, assignment block i error correcting code mark
Know symbol Bi=0, and go to step (3.2)；
(3.5) if BiFor 1, then the strong LDPC code of all pages of uses carries out error correction in block i.
It is another aspect of this invention to provide that additionally providing a kind of adaptive error correction system of solid-state disk, the system is included such as
Lower module：Solid-state disk initialization module, adaptive error correction coding module, solid-state disk decoding module, wherein：
The solid-state disk initialization module, for before input data, block erasing operation being carried out to solid-state disk, to write
Data, and initialize the error correcting code identifier B of all erasing blocksi=0, wherein i=0,1 ..., n, n represent solid-state disk erasing block
Quantity；
The solid-state disk adaptive error correction coding module, for carrying out adaptive error correction coding to initial data, specifically：
When one page initial data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code1Initial data R is carried out
Coding obtains code word C1=R × G1, code word C1Remove initial data R and obtain weak LDPC code check information P1；By the life of strong LDPC code
Into matrix G2Generation code word C is encoded to one page initial data R2=R × G2, code word C2Remove initial data R and obtain strong LDPC code school
Test information P2；One page initial data R and P1, P2Form code word C=(R, P of one page1, P2)；The code word C of generation is write into flash memory core
In piece；
The solid-state disk decoding module, including read judge module, error correcting code identification module, weak LDPC code correction module, from
Error correcting code handover module and strong LDPC code correction module are adapted to, wherein：
The reading judge module, for determining whether read operation, if read operation then turns to (3.2), otherwise terminate；
The error correcting code identification module, for judging the error correcting code identifier B of block i where reading pageiWhether it is 0；
The weak LDPC code correction module, if for BiFor 0, then all pages of weak LDPC codes of use in block i are entangled
It is wrong；
The adaptive error correcting code handover module, for performing the adaptive error correcting code handover operation of solid-state disk, it is specially：Such as
One page is failed using weak LDPC code error correction in fruit block i, assignment block i error correcting code identifier Bi=1, and go to the strong LDPC code
Correction module；After error correction being carried out such as fruit block i using strong LDPC code, as fruit block i is wiped free of, assignment block i error correcting code identifier Bi
=0, and go to the error correcting code identification module；
The strong LDPC code correction module, if for BiFor 1, then all pages of strong LDPC codes of use in block i are entangled
It is wrong.
In summary, the beneficial effect of technical solution of the present invention is：
A kind of adaptive LDPC error correction optimization method of solid-state disk is proposed, this method can be according to solid-state disk error rate not
Automatically switched with strong and weak two kinds of LDPC error correction intersymbols.With it is traditional only use single LDPC error correction code approach compared with,
The error-correcting performance of different LDPC error correcting codes can be effectively played, reduces error-correcting performance redundancy caused by single LDPC error correcting codes,
Reading performance can be effectively improved by carrying out error correction to solid-state disk with the method.Because during using high code check LDPC error correcting codes, generation
Code word size substantially diminishes, and caused threshold voltage detecting period, the codeword transmission time, decoding time has corresponding reduction.Together
When also can significantly be reduced relative to single LDPC error correcting codes, the decoding energy consumption of adaptive LDPC error correction methods.
Brief description of the drawings
Fig. 1 is the handling process schematic diagram of the adaptive error correction algorithm of the present invention；
Fig. 2 is weak LDPC code and strong LDPC code cataloged procedure schematic diagram；
Fig. 3 is that weak LDPC code and strong LDPC code decode process schematic；
Fig. 4 is solid-state disk block error correcting code adaptive handoff algorithms schematic diagram；
Fig. 5 is the adaptive error correction system structural representation of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
The LDPC code of high code check represents weak LDPC code in the present invention, and the LDPC code of low bit- rate represents strong LDPC code.
As shown in figure 1, for the handling process schematic diagram of adaptive error correction algorithm of the invention, the error correction algorithm includes as follows
Step：
(1) initialize and be specially：
Solid-state disk will carry out block erasing operation, to write data before input data.Initialize entangling for all erasing blocks
Error code identifier Bi=0 (i=0,1 ..., n), n represent the quantity of solid-state disk block；
(2) the specific coding process of solid-state disk adaptive error correction method is：
(2.1) as shown in Fig. 2 when one page initial data R is written into solid-state disk flash chip, according to the life of weak LDPC code
Into matrix G1Initial data R is encoded to obtain code word C1=R × G1, code word C1Remove initial data R and obtain weak LDPC code school
Test information P1；
(2.2) by the generator matrix G of strong LDPC code2Generation code word is encoded to one page initial data R
C2=R × G2, code word C2Remove initial data R and obtain strong LDPC code check information P2；
(2.3) one page initial data R and P1, P2Form code word C=(R, P of one page1, P2)；
(2.4) by the code word C write-in flash chips of generation；
(3) solid-state disk decoding process comprises the following steps：
(3.1) read operation is determined whether, if read operation then turns to (3.2), otherwise terminates this algorithm；
(3.2) the error correcting code identifier B of block i where reading page is judgediWhether it is 0；
(3.3) if BiFor 0, then the weak LDPC code of all pages of uses carries out error correction in block i, and weak LDPC code error correction is specific such as
Under：
(3.3.1) is as shown in figure 3, obtain by one page initial data R and weak LDPC code verification data P1The code word C of composition1；
(3.3.2) is to code word C1In each binary digit biCalculate log-likelihood ratio LLRiValue
Wherein ViRepresent to perceive magnitude of voltage, AiRepresent to perceive the regional extent value where voltage, P(i)(x) i-th of threshold is represented
Threshold voltage perceives Gaussian function；
Obtained LLR information is input to weak LDPC check matrix Hs by (3.3.3)1In variable node in, as LDPC solve
The initial information of code；
(3.3.4) check matrix H1In each variable node be iterated processing decoding letter between each other with check-node
Breath, iterative information is only in variable node and check-node in check matrix H1In transmit each other between the node of annexation；
(3.3.5) is if the weak LDPC that decoding obtains decodes vectorial C '1With the code word C of input1It is equal, export successfully decoded
And success output data.If the iterations of maximum but the vectorial C ' of decoding are reached1With inputting code word C1, then export and translate
Code failure simultaneously terminates weak LDPC decodings process；
(3.3.6) goes to step (3.4) and performs the adaptive error correcting code switching of solid-state disk if weak LDPC code error correction fails
Operation；
(3.4) the adaptive error correcting code handover operation of solid-state disk, it is specific as follows：
(3.4.1) is as shown in figure 4, one page uses weak LDPC code error correction failure, assignment block i error correcting code mark in such as fruit block i
Know symbol Bi=1, and go to step (3.5)；
(3.4.2) after such as fruit block i carries out error correction using strong LDPC code, as fruit block i is wiped free of, assignment block i error correcting code mark
Know symbol Bi=0, and go to step (3.2)；
(3.5) if BiFor 1, then the strong LDPC code of all pages of uses carries out error correction in block i, and strong LDPC code error correction is specific such as
Under：
(3.5.1) is obtained by initial data R and strong LDPC code verification data P2The code word C of composition2；
(3.5.2) is to code word C2In each binary digit bjCalculate log-likelihood ratio LLRjValue
Wherein VjRepresent to perceive magnitude of voltage, AjRepresent to perceive the regional extent value where voltage, P(j)(x) j-th of threshold is represented
Threshold voltage perceives Gaussian function；
Obtained LLR information is input to strong LDPC check matrix Hs by (3.5.3)2In variable node in, as LDPC solve
The initial information of code；
(3.5.4) check matrix H2In each variable node be iterated processing decoding letter between each other with check-node
Breath, iterative information is only in variable node and check-node in check matrix H2In transmit each other between the node of annexation；
(3.5.5) is if the strong LDPC that decoding obtains decodes vectorial C '2With the code word C of input2It is equal, export successfully decoded
And success output data.If the iterations of maximum but the vectorial C ' of decoding are reached2With inputting code word C2, then export and translate
Code failure simultaneously terminates strong LDPC decodings process.
Further, as shown in figure 5, present invention also offers a kind of adaptive error correction system of solid-state disk, the system bag
Include following module：Solid-state disk initialization module, adaptive error correction coding module, solid-state disk decoding module, wherein：
The solid-state disk initialization module, for before input data, block erasing operation being carried out to solid-state disk, to write
Data, and initialize the error correcting code identifier B of all erasing blocksi=0, wherein i=0,1 ..., n, n represent solid-state disk erasing block
Quantity；
The solid-state disk adaptive error correction coding module, for carrying out adaptive error correction coding to initial data, specifically：
When one page initial data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code1Initial data R is carried out
Coding obtains code word C1=R × G1, code word C1Remove initial data R and obtain weak LDPC code check information P1；By the life of strong LDPC code
Into matrix G2Generation code word C is encoded to one page initial data R2=R × G2, code word C2Remove initial data R and obtain strong LDPC code school
Test information P2；One page initial data R and P1, P2Form code word C=(R, P of one page1, P2)；The code word C of generation is write into flash memory core
In piece；
The solid-state disk decoding module, including read judge module, error correcting code identification module, weak LDPC code correction module, from
Error correcting code handover module and strong LDPC code correction module are adapted to, wherein：
The reading judge module, for determining whether read operation, if read operation then turns to (3.2), otherwise terminate；
The error correcting code identification module, for judging the error correcting code identifier B of block i where reading pageiWhether it is 0；
The weak LDPC code correction module, if for BiFor 0, then all pages of weak LDPC codes of use in block i are entangled
It is wrong；
The adaptive error correcting code handover module, for performing the adaptive error correcting code handover operation of solid-state disk, it is specially：Such as
One page is failed using weak LDPC code error correction in fruit block i, assignment block i error correcting code identifier Bi=1, and go to the strong LDPC code
Correction module；After error correction being carried out such as fruit block i using strong LDPC code, as fruit block i is wiped free of, assignment block i error correcting code identifier Bi
=0, and go to the error correcting code identification module；
The strong LDPC code correction module, if for BiFor 1, then all pages of strong LDPC codes of use in block i are entangled
It is wrong.
Further, the weak LDPC code correction module specifically includes weak LDPC code word acquisition submodule, weak LDPC code seemingly
Right ratio calculation submodule, weak LDPC code initial information generation submodule, weak LDPC code iterative processing submodule, weak LDPC code are translated
Code success judging submodule and weak LDPC code error correction switching submodule, wherein：
The weak LDPC code word acquisition submodule, for obtaining by one page initial data R and weak LDPC code verification data P1
The code word C of composition1；
The weak LDPC code likelihood ratio calculating sub module, for code word C1In each binary digit biCalculate logarithm seemingly
So compare LLRiValue
Wherein：ViRepresent to perceive magnitude of voltage, AiRepresent to perceive the regional extent value where voltage, P(i)(x) i-th of threshold is represented
Threshold voltage perceives Gaussian function；
The weak LDPC code initial information generation submodule, square is verified for obtained LLR information to be input into weak LDPC
Battle array H1In variable node in, as LDPC decoding initial information；
The weak LDPC code iterative processing submodule, for performing check matrix H1In each variable node and check-node
Processing decoding information is iterated between each other, and iterative information is only in variable node and check-node in check matrix H1In each other
Transmitted between the node of annexation；
The successfully decoded judging submodule of weak LDPC code, if for judging that the weak LDPC that decoding obtains decodes vector
C′1With the code word C of input1It is equal, export successfully decoded and output data.If reached maximum iterations but decode to
Measure C '1With inputting code word C1, then export decoding failure and terminate weak LDPC decodings process；
The weak LDPC code error correction switching submodule, if failed for weak LDPC code error correction, go to described adaptive
Error correcting code handover module simultaneously performs the adaptive error correcting code handover operation of solid-state disk.
Further, the strong LDPC code correction module specifically includes strong LDPC code word acquisition submodule, strong LDPC code seemingly
Right ratio calculation submodule, strong LDPC code initial information generation submodule, strong LDPC code iterative processing submodule, strong LDPC code are translated
Code success judging submodule, wherein：
The strong LDPC code word acquisition submodule, for obtaining by initial data R and strong LDPC code verification data P2Composition
Code word C2；
The strong LDPC code likelihood ratio calculating sub module, for code word C2In each binary digit bjCalculate logarithm seemingly
So compare LLRjValue
Wherein VjRepresent to perceive magnitude of voltage, AjRepresent to perceive the regional extent value where voltage, P(j)(x) j-th of threshold is represented
Threshold voltage perceives Gaussian function；
The strong LDPC code initial information generation submodule, square is verified for obtained LLR information to be input into strong LDPC
Battle array H2In variable node in, as LDPC decoding initial information；
The strong LDPC code iterative processing submodule, for performing check matrix H2In each variable node and check-node
It is iterated processing decoding information between each other.Iterative information is only in variable node and check-node in check matrix H2In each other
Transmitted between the node of annexation；
The successfully decoded judging submodule of the strong LDPC code, if decoding vectorial C ' for decoding obtained strong LDPC2With
The code word C of input2It is equal, export successfully decoded and output data.If the iterations of maximum but the vectorial C ' of decoding are reached2
With inputting code word C2, then export decoding failure and terminate strong LDPC decodings process.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., all should be included
Within protection scope of the present invention.
Claims (6)
1. a kind of solid-state disk adaptive error correction method, it is characterised in that methods described comprises the following steps：
(1) initialize：Solid-state disk carries out block erasing operation, to write data, and initializes all erasings before input data
The error correcting code identifier B of blocki=0, wherein i=0,1 ..., n, n represent the quantity of solid-state disk erasing block；
(2) solid-state disk adaptive error correction coding, including：
(2.1) when one page initial data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code1To original
Data R is encoded to obtain code word C1=R × G1, code word C1Remove initial data R and obtain weak LDPC code check information P1；
(2.2) by the generator matrix G of strong LDPC code2Generation code word C is encoded to one page initial data R2=R × G2, code word C2Remove
Initial data R obtains strong LDPC code check information P2；
(2.3) one page initial data R and P1, P2Form code word C=(R, P of one page1, P2)；
(2.4) by the code word C write-in flash chips of generation；
(3) solid-state disk decoding process, including：
(3.1) read operation is determined whether, if read operation then turns to (3.2), is otherwise terminated；
(3.2) the error correcting code identifier B of block i where reading page is judgediWhether it is 0；
(3.3) if BiFor 0, then the weak LDPC code of all pages of uses carries out error correction in block i；
(3.4) the adaptive error correcting code handover operation of solid-state disk, including：
One page is failed using weak LDPC code error correction in (3.4.1) such as fruit block i, assignment block i error correcting code identifier Bi=1, and go to
Step (3.5)；
(3.4.2) after such as fruit block i carries out error correction using strong LDPC code, as fruit block i is wiped free of, assignment block i error correcting code identifier Bi
=0, and go to step (3.2)；
(3.5) if BiFor 1, then the strong LDPC code of all pages of uses carries out error correction in block i.
2. the method as described in claim 1, it is characterised in that the step (3.3) specifically includes：
(3.3.1) is obtained by one page initial data R and weak LDPC code verification data P1The code word C of composition1；
(3.3.2) is to code word C1In each binary digit biCalculate log-likelihood ratio LLRiValue
Wherein ViRepresent to perceive magnitude of voltage, AiRepresent to perceive the regional extent value where voltage, P(i)(x) i-th threshold electricity is represented
Pressure sensitivity knows Gaussian function；
Obtained LLR information is input to weak LDPC check matrix Hs by (3.3.3)1In variable node in, as LDPC decoding
Initial information；
(3.3.4) check matrix H1In each variable node be iterated processing decoding information, iteration between each other with check-node
Information is only in variable node and check-node in check matrix H1In transmit each other between the node of annexation；
(3.3.5) is if the weak LDPC that decoding obtains decodes vectorial C1' and code word C1It is equal, export successfully decoded and successfully export
Data；If the iterations of maximum but the vectorial C of decoding are reached1' and code word C1, then export decoding failure and terminate weak
LDPC decodes process；
(3.3.6) goes to step (3.4) and performs the adaptive error correcting code switching behaviour of solid-state disk if weak LDPC code error correction fails
Make.
3. method as claimed in claim 1 or 2, it is characterised in that the step (3.5) specifically includes：
(3.5.1) is obtained by initial data R and strong LDPC code verification data P2The code word C of composition2；
(3.5.2) is to code word C2In each binary digit bjCalculate log-likelihood ratio LLRjValue
Wherein VjRepresent to perceive magnitude of voltage, AjRepresent to perceive the regional extent value where voltage, P(j)(x) j-th of threshold value electricity is represented
Pressure sensitivity knows Gaussian function；
Obtained LLR information is input to strong LDPC check matrix Hs by (3.5.3)2In variable node in, as LDPC decoding
Initial information；
(3.5.4) check matrix H2In each variable node be iterated processing decoding information between each other with check-node；Iteration
Information is only in variable node and check-node in check matrix H2In transmit each other between the node of annexation；
(3.5.5) is if the strong LDPC that decoding obtains decodes vectorial C2' and code word C2It is equal, export successfully decoded and successfully export
Data；If the iterations of maximum but the vectorial C of decoding are reached2' and code word C2, then export decoding failure and terminate strong
LDPC decodes process.
4. a kind of adaptive error correction system of solid-state disk, it is characterised in that the system includes following module：Solid-state disk initializes mould
Block, adaptive error correction coding module, solid-state disk decoding module, wherein：
The solid-state disk initialization module, for before input data, block erasing operation being carried out to solid-state disk, to write number
According to, and initialize the error correcting code identifier B of all erasing blocksi=0, wherein i=0,1 ..., n, n represent solid-state disk erasing block
Quantity；
The solid-state disk adaptive error correction coding module, for carrying out adaptive error correction coding to initial data, specifically：When one
When page initial data R is written into solid-state disk flash chip, according to the generator matrix G of weak LDPC code1Initial data R is encoded
Obtain code word C1=R × G1, code word C1Remove initial data R and obtain weak LDPC code check information P1；By the generation square of strong LDPC code
Battle array G2Generation code word C is encoded to one page initial data R2=R × G2, code word C2Remove initial data R and obtain strong LDPC code verification letter
Cease P2；One page initial data R and P1, P2Form code word C=(R, P of one page1, P2)；The code word C of generation is write into flash chip
In；
The solid-state disk decoding module, including read judge module, error correcting code identification module, weak LDPC code correction module, adaptive
Error correcting code handover module and strong LDPC code correction module, wherein：
The reading judge module, for determining whether read operation, if read operation then turns to (3.2), otherwise terminate；
The error correcting code identification module, for judging the error correcting code identifier B of block i where reading pageiWhether it is 0；
The weak LDPC code correction module, if for BiFor 0, then error correction is carried out to the weak LDPC code of all pages of uses in block i；
The adaptive error correcting code handover module, for performing the adaptive error correcting code handover operation of solid-state disk, it is specially：Such as fruit block
One page is failed using weak LDPC code error correction in i, assignment block i error correcting code identifier Bi=1, and go to the strong LDPC code error correction
Module；After error correction being carried out such as fruit block i using strong LDPC code, as fruit block i is wiped free of, assignment block i error correcting code identifier Bi=0,
And go to the error correcting code identification module；
The strong LDPC code correction module, if for BiFor 1, then error correction is carried out to the strong LDPC code of all pages of uses in block i.
5. system as claimed in claim 4, it is characterised in that the weak LDPC code correction module specifically includes weak LDPC code word
Acquisition submodule, weak LDPC code likelihood ratio calculating sub module, weak LDPC code initial information generation submodule, weak LDPC code iteration
Submodule, the successfully decoded judging submodule of weak LDPC code and weak LDPC code error correction switching submodule are handled, wherein：
The weak LDPC code word acquisition submodule, for obtaining by one page initial data R and weak LDPC code verification data P1Composition
Code word C1；
The weak LDPC code likelihood ratio calculating sub module, for code word C1In each binary digit biCalculate log-likelihood ratio
LLRiValueWherein：ViRepresent to perceive magnitude of voltage, AiRepresent to perceive the area where voltage
Domain value range, P(i)(x) represent that i-th threshold voltage perceives Gaussian function；
The weak LDPC code initial information generation submodule, for obtained LLR information to be input into weak LDPC check matrix Hs1In
Variable node in, as LDPC decoding initial information；
The weak LDPC code iterative processing submodule, for performing check matrix H1In each variable node and check-node it is mutual
Between be iterated processing decoding information, iterative information is only in variable node and check-node in check matrix H1In connect each other
Transmitted between the node of relation；
The successfully decoded judging submodule of weak LDPC code, if for judging that the LDPC that decoding obtains decodes vectorial C1' and code word
C1It is equal, successfully decoded and success output data is exported, if having reached the iterations of maximum but the vectorial C of decoding1' and code word
C1, then export decoding failure and terminate weak LDPC decodings process；
The weak LDPC code error correction switching submodule, if failed for weak LDPC code error correction, go to the adaptive error correction
Code handover module simultaneously performs the adaptive error correcting code handover operation of solid-state disk.
6. the system as described in claim 4 or 5, it is characterised in that the strong LDPC code correction module specifically includes strong LDPC
Code word acquisition submodule, strong LDPC code likelihood ratio calculating sub module, strong LDPC code initial information generation submodule, strong LDPC code
Iterative processing submodule, the successfully decoded judging submodule of strong LDPC code, wherein：
The strong LDPC code word acquisition submodule, for obtaining by initial data R and strong LDPC code verification data P2The code word of composition
C2；
The strong LDPC code likelihood ratio calculating sub module, for code word C2In each binary digit bjCalculate log-likelihood ratio
LLRjValueWherein VjRepresent to perceive magnitude of voltage, AjRepresent to perceive the area where voltage
Domain value range, P(j)(x) represent that j-th of threshold voltage perceives Gaussian function；
The strong LDPC code initial information generation submodule, for obtained LLR information to be input into strong LDPC check matrix Hs2In
Variable node in, as LDPC decoding initial information；
The strong LDPC code iterative processing submodule, for performing check matrix H2In each variable node and check-node it is mutual
Between be iterated processing decoding information；Iterative information is only in variable node and check-node in check matrix H2In connect each other
Transmitted between the node of relation；
The successfully decoded judging submodule of the strong LDPC code, if decoding vectorial C for decoding obtained strong LDPC2' and code word C2
It is equal, export successfully decoded and success output data；If the iterations of maximum but the vectorial C of decoding are reached2' and code word C2
, then export decoding failure and terminate strong LDPC decodings process.
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