CN104811164A - Triangular wave generating circuit with clock signal synchronization - Google Patents
Triangular wave generating circuit with clock signal synchronization Download PDFInfo
- Publication number
- CN104811164A CN104811164A CN201410041775.3A CN201410041775A CN104811164A CN 104811164 A CN104811164 A CN 104811164A CN 201410041775 A CN201410041775 A CN 201410041775A CN 104811164 A CN104811164 A CN 104811164A
- Authority
- CN
- China
- Prior art keywords
- signal
- current source
- constant current
- clock signal
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Disclosed is a triangular wave generating circuit with clock signal synchronization. The triangular wave generating circuit with clock signal synchronization comprises a capacitor, a first constant current source, a second constant current source, a third constant current source, a fourth constant current source, a first switching unit, a second switching unit, a high and low electrical level limiting unit, a clock signal generator and a phase detecting unit, wherein the first constant current source and the second constant current source are used for charging the capacitor; the third constant current source and the fourth constant current source are used for discharging the capacitor; the phase detecting unit is used for receiving an externally-supplied clock signal and an internal clock signal and generating a first phase signal and a second phase signal according to the phase difference of the externally-supply clock signal and the internal clock signal; the second switching unit comprises a third switch and a fourth switch, the third switch is used for responding to the first phase signal to control the coupling state of the second constant current source and the capacitor, and the fourth switch is used for responding to the second phase signal to control the coupling state of the fourth constant current source and the capacitor.
Description
Technical field
The present invention relates to a kind of circuit for generating triangular wave, particularly relate to a kind of circuit for generating triangular wave synchronous with external timing signal.
Background technology
Circuit for generating triangular wave by charging and discharging one electric capacity to produce triangular signal.Circuit for generating triangular wave can be applied in many circuit, and wherein namely a kind of application converts analog voice signal to pulse-width signal in D type (class-D) power amplifier.
Fig. 1 is the known circuit 10 utilizing square-wave signal VIN to produce triangular signal VOUT.The accuracy of triangular signal can have influence on the usefulness of the device using this triangular signal, the usefulness of such as pulse-width modulation (PWM) device.The switching frequency fsw of triangular signal VOUT equals 1/ (TU+TD) in this figure, and wherein TU is the rise time of triangular signal VOUT by VL to VH, and TD is the fall time of triangular signal VOUT by VH to VL.Rise time TU equals C × (VH-VL)/IC, and wherein C is the capacitance of the capacitor C1 across operational amplifier 12, the charging current that IC provides for current source I1.In like manner, fall time, TD equaled C × (VH-VL)/ID, wherein the discharging current that provides for current source I2 of ID.Suppose that IC and ID is equal, then switching frequency fsw equals IC/ (2 × C × (VH-VL)).Equation learns that triangular wave switching frequency fsw and IC and ID is directly proportional thus, and is inversely proportional to triangular signal amplitude (VH-VL).
Fig. 2 is the potential problems schematic diagram of the circuit for generating triangular wave 10 of Fig. 1.As shown in Figure 2, in problem 1, if current source does not mate, namely electric current I C is greater than ID or electric current I D when being greater than IC, then triangular signal VOUT would not locate conversion at predetermined peak limiting VH and VL.In like manner, the responsibility cycle that problem 2 discloses when square wave is not triangular wave waveform during ideal value, and problem 2 can the normal reason occurred be that internal clock signal and external timing signal are asynchronous.Synchronously be very important something by internal clock signal with external timing signal, as applied the D type amplifier voice system of 5.1 sound channels or 7.1 sound channels.If switching frequency is not identical, then beating of frequency just appears in voiceband.
Accordingly, be necessary that proposition one circuit for generating triangular wave is to improve the problems referred to above.
Summary of the invention
The invention provides a kind of circuit for generating triangular wave with clock signal synchronization.This circuit for generating triangular wave comprises a capacitor, one first constant current source, one second constant current source, one the 3rd constant current source, one the 4th constant current source, one first switch unit, one second switch unit, one high/low level limiting unit, a clock signal generator, and a phase detection unit.These first and second constant current sources are in order to charge to this capacitor.These third and fourth constant current sources are in order to this capacitor discharge.This first switch unit comprises one first switch and a second switch, this first switch unit in order in response to an internal clock signal with control this first and the coupling access status of the 3rd constant current source and this capacitor.This high/low level limiting unit comprises one first and 1 second comparing unit, this first comparing unit is in order to compare this triangular signal and a high level reference voltage, and produce an output signal when this triangular signal arrives this high level reference voltage, this second comparing unit in order to compare this triangular signal and a low level reference voltage, and produces an output signal when this triangular signal arrives this low level reference voltage.This clock signal generator in order in response to this output signal of this first comparing unit and this output signal of this second comparing unit to produce this internal clock signal.This phase detection unit, in order to receive an outside supply clock signal and this internal clock signal, and produces a first phase signal and a second phase signal according to the phase difference value of this outside supply clock signal and this internal clock signal.This second switch unit comprises one the 3rd switch and one the 4th switch, 3rd switch in order in response to this first phase signal to control the coupling access status of this second constant current source and this capacitor, and the 4th switch in order in response to this second phase signal to control the coupling access status of the 4th constant current source and this capacitor.
Accompanying drawing explanation
Fig. 1 is the known circuit utilizing square-wave signal to produce triangular signal.
Fig. 2 is the potential problems schematic diagram of the circuit for generating triangular wave of Fig. 1.
Fig. 3 display is in conjunction with the circuit diagram of the triangular signal generator of one embodiment of the invention.
Fig. 4 shows one of this phase detection unit shown in Fig. 3 may operate oscillogram.
Fig. 5 show this phase detection unit shown in Fig. 3 another may operate oscillogram.
Fig. 6 display is in conjunction with an oscillogram of this triangular signal generator of one embodiment of the invention.
Fig. 7 display is in conjunction with an oscillogram of this triangular signal generator of another embodiment of the present invention.
Fig. 8 display is in conjunction with the circuit diagram of the triangular signal generator of one embodiment of the invention.
Fig. 9 display is in conjunction with the circuit diagram of these switch current arrays of one embodiment of the invention.
Figure 10 display is in conjunction with the operation workflow figure of this triangular signal generator of one embodiment of the invention.
[symbol description]
10 circuit for generating triangular wave
12 operational amplifiers
30,30 ' triangular signal generator
32 switch units
33 second drive circuits
34 low and high level limiting circuits
342 comparators
344 comparators
36 internal clock signal generators
38 phase detection units
82 switch current arrays
84 switch current arrays
86 comparison circuits
C1 capacitor
I1-IN constant current source
M1, M2, M3, M4 switch
SW1-SWN switch
S100-S110 step
Embodiment
Some vocabulary is employed to censure specific element in the middle of specification and appending claims.Those skilled in the art should understand, and same element may be called with different nouns by manufacturer.This specification and appending claims are not used as the mode of distinguish one element from another with the difference of title, but are used as the criterion of differentiation with element difference functionally." comprising " mentioned in the middle of specification and appending claims is in the whole text an open term, therefore should be construed to " comprise but be not limited to ".In addition, " couple " word comprise directly any at this and be indirectly electrically connected means.Therefore, if describe a first device in literary composition to be coupled to one second device, then represent this first device and directly can be electrically connected in this second device, or be indirectly electrically connected to this second device by other devices or connection means.
Fig. 3 display is in conjunction with the circuit diagram of the triangular signal generator 30 of one embodiment of the invention.As shown in Figure 3, this triangular signal generator 30 comprises a capacitor C1, charge/discharge constant current source I1 and I2 of a pair coupling and a switch unit 32.The current value that what is called " coupling " word herein means charge/discharge constant current source I1 with I2 is identical in fact.This switch unit 32 comprises two switch M1 and M2 controlled by an internal clock signal.This two switch M1 and M2 switches in a complementary fashion, and therefore when switch M1 opens, switch M2 is closed condition, and vice versa.In addition, when switch M1 opens, this constant current source I1 can be coupled to this electric capacity C1.When switch M2 opens, this constant current source I2 can be coupled to this electric capacity C1.
With reference to Fig. 3, this triangular signal generator 30 also comprises a low and high level limiting circuit 34, and it comprises two comparators 342 and 344.This comparator 342 compares a signal VTRI on this electric capacity C1 and high level reference voltage VH, and this comparator 342 compares this signal VTRI and low level reference voltage VL.The output signal CPH of this comparator 342 and output signal CPL of this comparator 344 can be provided to an internal clock signal generator 36.In the present embodiment, this signal generator 36 is that a RS fastens lock device.This signal generator 36 provides an internal clock signal ICK to control this two switch M1 and M2 in this switch unit 32 according to comparative result.
With reference to Fig. 3, this triangular signal generator 30 also comprises charge/discharge constant current source I3 and I4 and a switch unit 33 of a pair coupling.This switch unit 33 comprises two switch M3 and M4.This switch M3 controlled by an output signal DP of a phase detection unit 38, and this switch M4 is controlled by an output signal DN of this phase detection unit 38.When switch M3 opens, switch M4 is closed condition, and vice versa.In addition, when switch M3 opens, this constant current source I3 can be coupled to this electric capacity C1.When switch M4 opens, this constant current source I4 can be coupled to this electric capacity C1.
As mentioned above, the running of this switch unit 33 is controlled by this phase detection unit 38.This phase detection unit 38 receives an outside supply clock signal ECK and this internal clock signal ICK, and produces these phase signals DP and DN according to the phase difference value of this clock signal ECK and this clock signal ICK.When this signals DP is logical zero level, the switch M3 conducting in this switch unit 33.When this signal DN is logical one level, the switch M4 conducting in this switch unit 33.
Fig. 4 shows one of this phase detection unit 38 shown in Fig. 3 may operate oscillogram, in the diagram, the phase place of this internal clock signal of phase-lead ICK of this external timing signal ECK, that is, the rising edge of rising edge this internal clock signal leading ICK of this external timing signal ECK, and the trailing edge of trailing edge this internal clock signal leading ICK of this external timing signal ECK.When the rising edge of rising edge this internal clock signal leading ICK of external timing signal ECK, this phase detection unit 38 produces this phase signal DP.When the trailing edge of trailing edge this internal clock signal leading ICK of external timing signal ECK, this phase detection unit 38 produces this phase signal DN.Therefore, the width W 1 of this phase signal DP and the width W 2 of this phase signal DN can be determined by this external timing signal ECK and the phase difference value of this internal clock signal ICK.
Fig. 5 show this phase detection unit 38 shown in Fig. 3 another may operate oscillogram, in Figure 5, the phase place of this external timing signal ECK falls behind the phase place of this internal clock signal ICK, that is, the rising edge of this external timing signal ECK falls behind the rising edge of this internal clock signal ICK, and the trailing edge of this external timing signal ECK falls behind the trailing edge of this internal clock signal ICK.When the rising edge of external timing signal ECK falls behind the rising edge of this internal clock signal ICK, this phase detection unit 38 produces this phase signal DP.When the trailing edge of external timing signal ECK falls behind the trailing edge of this internal clock signal ICK, this phase detection unit 38 produces this phase signal DN.Therefore, the width W 3 of this phase signal DP and the width W 4 of this phase signal DN can be determined by this external timing signal ECK and the phase difference value of this internal clock signal ICK.
The function mode of triangular signal generator 30 of the present invention is described referring now to Fig. 3 to Fig. 7, and wherein Fig. 6 display is in conjunction with an oscillogram of this triangular signal generator 30 of one embodiment of the invention.In the present embodiment, the phase place of this internal clock signal of phase-lead ICK of this external timing signal ECK.
With reference to Fig. 6, before time t1, when this clock signal ICK is logical zero level, this electric capacity C1 can by the current charges flowing through this constant current source I1, makes the rising that the voltage VTRI on this electric capacity C1 can be linear.At time t1, when this phase detection unit 38 detects the phase difference value between this external timing signal ECK and this internal clock signal ICK, can in response to the situation of the phase place of this internal clock signal of phase-lead ICK of this external timing signal ECK to produce this phase signal DP, this can make constant current source I3 charge to this electric capacity C1.Slope due to the ascent stage of triangular signal is proportional to the direct current flowing through electric capacity, this high level reference voltage of arrival VH that this signal VTRI can be very fast when time t2.After this signal VTRI arrives reference voltage VH, the output signal CPH of this comparator 342 can output logic 1 level, RS latch 36 is exported clock signal ICK that one has logical one level.
After time t 2, switch M1 and M3 can close, and this switch M2 can the conducting in response to clock signal ICK, and this electric capacity can by the current discharge flowing through constant current source I2.Therefore, the voltage VTRI on this electric capacity C1 can be linear decline.At time t3, when this phase detection unit 38 detects the phase difference value between this external timing signal ECK and this internal clock signal ICK, can in response to the situation of the phase place of this internal clock signal of phase-lead ICK of this external timing signal ECK to produce this phase signal DN, this can make constant current source I4 add constant current source I2 to discharge to this electric capacity C1.Higher DC current values produces shorter ramp time interval.Therefore, this low level reference voltage of arrival VL that this signal VTRI can be very fast when time t4.After this signal VTRI arrives reference voltage VL, the output signal CPL of this comparator 344 can output logic 1 level, RS latch 36 is exported clock signal ICK that one has logical zero level.
Above-mentioned running can repeatedly be implemented, and the voltage VTRI therefore on this capacitor C1 can produce in a triangular wave mode.As mentioned above, this internal clock signal ICK by the phase difference value detected between this external timing signal ECK and this internal clock signal ICK, can be synchronized with the clock signal ECK of this outside supply by this triangular signal generator 30.When the phase place of this internal clock signal of phase-lead ICK of this external timing signal ECK, the slope of this signal VTRI can increase according to testing result, therefore shortens ramp cycle.Mode according to this, this internal clock signal ICK can be synchronized with the clock signal ECK of this outside supply after several circulation.
Fig. 7 display is in conjunction with an oscillogram of this triangular signal generator 30 of another embodiment of the present invention.In the present embodiment, the phase place of this external timing signal ECK falls behind the phase place of this internal clock signal ICK.
With reference to Fig. 7, before time t1, this clock signal ICK is logical zero level, and this electric capacity C1 can by the current charges flowing through this constant current source I1, and this makes the voltage VTRI on this electric capacity C1 to rise linearly.When time t1, this signal VTRI can arrive high level reference voltage VH, and this makes output signal CPH output logic 1 level of this comparator 342, and allow RS latch 36 export clock signal ICK that one has logical one level.Therefore, this switch M1 can end and this switch M2 meeting conducting, makes current source I2 can be coupled to this capacitor C1.After time t1, this phase detection unit 38 detects to have phase difference value between this external timing signal ECK and this internal clock signal ICK, and produces this phase signal DP according to this testing result, and this can make constant current source I3 be coupled to this electric capacity C1.In the present embodiment, the current value of this current source I3 is greater than the current value of this current source I2.Therefore, this electric capacity C1 can be charged by net current I3-I2.
Clock signal ECK enters logical one level when time t2, and therefore this phase signal DP also gets back to logical one level.Then, this switch M3 can end, and this capacitor C1 can by the current discharge flowing through constant current source I2, and this can make the voltage VTRI on this capacitor C1 linearly decline.When time t3, this signal VTRI can arrive low level reference voltage VL, and this makes output signal CPL output logic 1 level of this ground comparator 344, and allow RS latch 36 export clock signal ICK that one has logical zero level.Therefore, this switch M2 can end and this switch M1 meeting conducting, makes current source I1 can be coupled to this electric capacity C1.After time t3, this phase detection unit 38 detects to have phase difference value between this external timing signal ECK and this internal clock signal ICK, and produce this phase signal DN according to testing result, this can make constant current source I4 start to discharge to this electric capacity C1.In the present embodiment, the current value of this current source I4 is greater than the current value of this current source I1.Therefore, this electric capacity C1 can be charged by net current I4-I1.
This clock signal ECK enters logical zero level when time t4, and therefore this phase signal DN also gets back to logical zero level.Then, this switch M4 can end, and this electric capacity can by the current charges flowing through constant current source I1.This electric capacity can carry out charging and discharging according to similar mode after time t5, and the voltage VTRI on this electric capacity C1 can be produced in a triangular wave mode.
As mentioned above, this internal clock signal ICK by the phase difference value detected between this external timing signal ECK and this internal clock signal ICK, can be synchronized with the clock signal ECK of this outside supply by this triangular signal generator 30.When the phase place of this external timing signal ECK falls behind the phase place of this internal clock signal ICK, this electric capacity C1 can keep previous charge/discharge state in phase difference interval.Because the slope entirety of signal VTRI slows down, therefore ramp cycle increases.Mode according to this, this internal clock signal ICK can be synchronized with the clock signal ECK of this outside supply after several circulation.
In the above-described embodiments, this capacitor C1 can carry out extra charging and discharging by constant current source I3 and I4.But in various embodiments, this capacitor C1 also can carry out extra charging and discharging by variable current source in phase difference interval.Fig. 8 display is in conjunction with the circuit diagram of the triangular signal generator 30 ' of one embodiment of the invention.With reference to Fig. 8, a comparison circuit 86 compares pulse duration and a predetermined time interval TSET of this phase signal DP, to produce the digital code be made up of multiple C0 to CN.Meanwhile, this comparison circuit 86 compares pulse duration and this predetermined time interval TSET of this phase signal DN, to produce the digital code be made up of multiple B0 to BN.
With reference to Fig. 8, after a switching current array 82 receives these digit order numbers C0 to CN, provide charging current according to these digit order numbers C0 to CN.After one switching current array 84 receives these digit order numbers B0 to BN, provide discharging current according to these digit order numbers B0 to BN.Fig. 9 display is in conjunction with the circuit diagram of these switch current arrays 82 and 84 of one embodiment of the invention.With reference to Fig. 9, this switch current array 82 comprises multiple identical current source I1 to IN, and each current source transmits identical electric current I.This switch current array 82 comprises multiple interrupteur SW 1 to the SWN corresponding to multiple current source I1 to IN further.For example, interrupteur SW 1 is responsible for the coupling access status controlling current source I1 and electric capacity C1.The Circnit Layout of this switch current array 84 is similar to this current array 82.With reference to Fig. 9, this switch current array 84 comprises multiple identical current source I1 to IN, and each current source transmits identical electric current I.This switch current array 84 comprises multiple interrupteur SW 1 to the SWN corresponding to multiple current source I1 to IN further.
Figure 10 display is in conjunction with the operation workflow figure of this triangular signal generator 30 ' of one embodiment of the invention.This flow process starts from step S100.Below illustrate and please refer to Fig. 8 to Figure 10.In step s 102, this phase detection unit 38 can receive this external timing signal ECK and this internal clock signal ICK, and produces this phase signal DP according to phase difference value between the two.In step S104, this comparison circuit 86 compares pulse duration and the predetermined time interval TSET of this phase signal DP, to produce by multiple digit order number C0 to CN.In one embodiment, these digit order numbers C0 to CN reacts on the difference between the pulse duration of this phase signal DP and this predetermined time interval TSET.In another embodiment, this comparison circuit 86 compares the pulse duration of this phase signal DP and multiple predetermined time interval TSET1 to TSETN, to produce by multiple digit order number C0 to CN.
Then, in step s 106, if the pulse duration of this phase signal DP is greater than this predetermined time interval TSET, the total current value flowing through this current array 82 can increase to charge to electric capacity C1.Then, this flow process gets back to step S104.If the pulse duration of this phase signal DP is less than this predetermined time interval TSET after charging current increases, then terminate this flow process.
With reference to Fig. 8 to Figure 10, in an embodiment of the present invention, this electric capacity C1 only can carry out charging and discharging by a current source in a current source in this current array 82 and this current array 84 when initial.Then, in step s 106, if the pulse duration of this phase signal DP is still greater than this predetermined time interval TSET (such as 100ns) after several clock cycle, another current source in this current array 82 can be coupled to this electric capacity C1 to increase charging current.After several clock cycle, this comparison circuit 86 can compare pulse duration and this predetermined time interval TSET of this phase signal DP again.If the pulse duration of this phase signal DP is still greater than this predetermined time interval TSET, represent that the total charging current flowing through this current array 82 still cannot reduce the phase difference value between this external timing signal ECK and this internal clock signal ICK, the another switch therefore in this current array 82 can be opened and make another current source be coupled to this electric capacity C1 to increase charging current.If be still greater than this predetermined time interval TSET in the pulse duration of several this phase signal of all after dates DP, then the switch again in this current array 82 can be opened and make a current source again be coupled to this electric capacity C1 to increase charging current.These switches can continue to open makes different current sources sequentially be coupled to this electric capacity C1 to increase charging current, until the pulse duration of this phase signal DP is less than this predetermined time interval TSET.Mode according to this, the pulse duration of this phase signal DP can be less than this predetermined time interval TSET.
In the above-described embodiments, these interrupteur SW 1 to the SWN in this current array 82 can sequentially open to increase total charging current, and this current array 84 only has interrupteur SW 1 conducting to increase discharging current.In another embodiment, these interrupteur SW 1 to the SWN in this current array 84 can sequentially open to increase total discharging current, and this current array 82 only has interrupteur SW 1 conducting to increase charging current.But, in another embodiment, interrupteur SW 1 to SWN in interrupteur SW 1 to SWN in this current array 82 and this current array 84 all can turn in order, to increase total charging and total discharging current according to the phase difference value between this external timing signal ECK and this internal clock signal ICK.Mode according to this, the pulse duration of this phase signal DP can reduce gradually, until be less than this predetermined time interval TSET.
Although the present invention with preferred embodiment openly as above; so itself and be not used to limit the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum.
Technology contents of the present invention and technical characterstic disclose as above, but those skilled in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement.Therefore, protection scope of the present invention should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present invention and modification, and is contained by claims subsequently.
Claims (9)
1. there is a circuit for generating triangular wave for clock signal synchronization, comprising:
One capacitor, has an output to provide a triangular signal;
First and second constant current sources, in order to charge to this capacitor;
Third and fourth constant current source, in order to this capacitor discharge;
One first switch unit, comprises one first switch and a second switch, this first switch unit in order in response to an internal clock signal with control this first and the coupling access status of the 3rd constant current source and this capacitor;
One high/low level limiting unit, comprise one first and 1 second comparing unit, this first comparing unit is in order to compare this triangular signal and a high level reference voltage, and produce an output signal when this triangular signal arrives this high level reference voltage, this second comparing unit in order to compare this triangular signal and a low level reference voltage, and produces an output signal when this triangular signal arrives this low level reference voltage;
One clock signal generator, in order in response to this output signal of this first comparing unit and this output signal of this second comparing unit to produce this internal clock signal;
One phase detection unit, in order to receive an outside supply clock signal and this internal clock signal, and produces a first phase signal and a second phase signal according to the phase difference value of this outside supply clock signal and this internal clock signal; And
One second switch unit, comprise one the 3rd switch and one the 4th switch, 3rd switch in order in response to this first phase signal to control the coupling access status of this second constant current source and this capacitor, and the 4th switch in order in response to this second phase signal to control the coupling access status of the 4th constant current source and this capacitor.
2. circuit for generating triangular wave according to claim 1, wherein when the rising edge of rising edge this internal clock signal leading of this outside supply clock signal, this phase detection unit produces this first phase signal.
3. circuit for generating triangular wave according to claim 1, wherein when the trailing edge of trailing edge this internal clock signal leading of outside supply clock signal, this phase detection unit produces this second phase signal.
4. circuit for generating triangular wave according to claim 1, wherein the current value of this second constant current source is greater than the current value of the 3rd constant current source, and when the rising edge of outside supply clock signal falls behind the rising edge of this internal clock signal, this phase detection unit produces this first phase signal.
5. circuit for generating triangular wave according to claim 1, wherein the current value of the 4th constant current source is greater than the current value of this first constant current source, and when the trailing edge of outside supply clock signal falls behind the trailing edge of this internal clock signal, this phase detection unit produces this second phase signal.
6. circuit for generating triangular wave according to claim 1, also comprises:
One first comparing unit, in order to compare the pulse duration of this first phase signal and multiple predetermined time interval, and produces one first digital code when the pulse duration of this first phase signal is greater than described predetermined time interval; And
One first switch current array, comprises multiple identical constant current source and the multiple switches corresponding to described constant current source;
Described constant current source wherein in this first switch current array in response to this first digital code to be sequentially coupled to this capacitor.
7. circuit for generating triangular wave according to claim 1, also comprises:
One second comparing unit, in order to compare the pulse duration of this second phase signal and multiple predetermined time interval, and produces one second digital code when the pulse duration of this second phase signal is greater than described predetermined time interval; And
One second switch current array, comprises multiple identical constant current source and the multiple switches corresponding to described constant current source;
Described constant current source wherein in this second switch current array in response to this second digital code to be sequentially coupled to this capacitor.
8. circuit for generating triangular wave according to claim 1, also comprises:
One first comparing unit, in order to compare pulse duration and a predetermined time interval of this first phase signal, and produces one first digital code according to the pulse duration of this first phase signal and the phase difference value of this predetermined time interval; And
One first switch current array, comprises multiple identical constant current source and the multiple switches corresponding to described constant current source;
Described constant current source wherein in this first switch current array in response to this first digital code to be sequentially coupled to this capacitor.
9. circuit for generating triangular wave according to claim 1, also comprises:
One second comparing unit, in order to compare pulse duration and a predetermined time interval of this second phase signal, and produces one second digital code according to the pulse duration of this second phase signal and the phase difference value of this predetermined time interval; And
One second switch current array, comprises multiple identical constant current source and the multiple switches corresponding to described constant current source;
Described constant current source wherein in this second switch current array in response to this second digital code to be sequentially coupled to this capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410041775.3A CN104811164B (en) | 2014-01-28 | 2014-01-28 | Circuit for generating triangular wave with clock signal synchronization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410041775.3A CN104811164B (en) | 2014-01-28 | 2014-01-28 | Circuit for generating triangular wave with clock signal synchronization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104811164A true CN104811164A (en) | 2015-07-29 |
| CN104811164B CN104811164B (en) | 2017-10-24 |
Family
ID=53695720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410041775.3A Active CN104811164B (en) | 2014-01-28 | 2014-01-28 | Circuit for generating triangular wave with clock signal synchronization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104811164B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911323A (en) * | 2015-12-23 | 2017-06-30 | 联芯科技有限公司 | Triangular-wave generator and triangular wave generation system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114177A (en) * | 2006-07-27 | 2008-01-30 | 硕颉科技股份有限公司 | Voltage controlled current source and frequency sweep device using same |
| CN101325408A (en) * | 2007-06-12 | 2008-12-17 | 上海沙丘微电子有限公司 | Circuit for generating triangular wave |
| CN101404487A (en) * | 2008-06-05 | 2009-04-08 | 美芯晟科技（北京）有限公司 | Triangular wave generation method and its circuit |
| US20100007387A1 (en) * | 2008-07-14 | 2010-01-14 | Elite Semiconductor Memory Technology Inc. | Triangular wave generating circuit having synchronization with external clock |
| CN102237859A (en) * | 2010-05-07 | 2011-11-09 | 旺宏电子股份有限公司 | Oscillator with frequency determined by relative magnitudes of current sources |
-
2014
- 2014-01-28 CN CN201410041775.3A patent/CN104811164B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114177A (en) * | 2006-07-27 | 2008-01-30 | 硕颉科技股份有限公司 | Voltage controlled current source and frequency sweep device using same |
| CN101325408A (en) * | 2007-06-12 | 2008-12-17 | 上海沙丘微电子有限公司 | Circuit for generating triangular wave |
| CN101404487A (en) * | 2008-06-05 | 2009-04-08 | 美芯晟科技（北京）有限公司 | Triangular wave generation method and its circuit |
| US20100007387A1 (en) * | 2008-07-14 | 2010-01-14 | Elite Semiconductor Memory Technology Inc. | Triangular wave generating circuit having synchronization with external clock |
| CN102237859A (en) * | 2010-05-07 | 2011-11-09 | 旺宏电子股份有限公司 | Oscillator with frequency determined by relative magnitudes of current sources |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106911323A (en) * | 2015-12-23 | 2017-06-30 | 联芯科技有限公司 | Triangular-wave generator and triangular wave generation system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104811164B (en) | 2017-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8044690B2 (en) | System and method for clock-synchronized triangular waveform generation | |
| CN105094197B (en) | Current modulating circuit | |
| US7986256B2 (en) | A/D converter | |
| CN101847982B (en) | Triangle wave generating circuit | |
| US9252655B2 (en) | Phase shift circuit and power factor correction circuit including the same | |
| US20190190505A1 (en) | Delay control circuits | |
| CN103346740B (en) | Class D audio power amplifier for suppressing noise and audio signal processing method thereof | |
| US8742833B2 (en) | Charge pump circuit and method thereof | |
| CN101478306A (en) | Driving circuit slew rate compensation apparatus and method | |
| US20190393786A1 (en) | Two-stage multi-phase switching power supply with ramp generator dc offset for enhanced transient response | |
| CN105706368A (en) | Asynchronous successive approximation resister analog-to-digital converter and an inner clock generator included therein | |
| CN103620961A (en) | Duty cycle correction apparatus | |
| CN106787687B (en) | A kind of charge pump circuit | |
| US20200177081A1 (en) | Power converter | |
| US9300281B2 (en) | Triangular wave generating circuit to provide clock synchronization | |
| US20080186075A1 (en) | Level shifter of semiconductor device and method for controlling duty ratio in the device | |
| US8248131B2 (en) | Timing generating circuit and phase shift circuit | |
| CN104811164B (en) | Circuit for generating triangular wave with clock signal synchronization | |
| JP2008252251A (en) | Switch circuit, signal output unit, and testing device | |
| US8368431B2 (en) | Pulse edge selection circuit, and pulse generation circuit, sample-hold circuit, and solid-state image sensor using the same | |
| US7391242B1 (en) | Sawtooth waveform generator | |
| KR100806295B1 (en) | Output voltage adaptive converter and method thereof | |
| CN115459720A (en) | Audio power amplifier circuit and duty ratio modulation circuit and noise suppression circuit thereof | |
| US9385700B2 (en) | Clock monitoring for sequential logic circuits | |
| CN101355349A (en) | Circuit and method for generating triangular wave |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |