CN104809043A - Connection test method and device of motherboard CPU (Central Processing Unit) slot based on boundary scan - Google Patents
Connection test method and device of motherboard CPU (Central Processing Unit) slot based on boundary scan Download PDFInfo
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- CN104809043A CN104809043A CN201510210644.8A CN201510210644A CN104809043A CN 104809043 A CN104809043 A CN 104809043A CN 201510210644 A CN201510210644 A CN 201510210644A CN 104809043 A CN104809043 A CN 104809043A
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Abstract
The invention provides a connection test method of a motherboard CPU (Central Processing Unit) slot based on boundary scan, which comprises the following steps of analyzing a to-be-tested motherboard schematic diagram and a boundary scan description language file of a motherboard CPU, a virtual DIMM (dual In-line memory module) jig and a virtual PCIE jig, and extracting scan chain information of the to-be-tested motherboard; extracting scan unit information corresponding to a to-be-tested motherboard CPU slot connecting line; a to-be-tested motherboard CPU, the virtual DIMM jig and the virtual PCIE jig are controlled on a test control motherboard through a TAP controller to enter a boundary scan mode; running multiple types of boundary scan child tests, and collecting and analyzing a responding result; judging whether the to-be-tested motherboard is fault or not and locating the fault position according to the responding result. According to a connection test device and the method, a CPU signal transfer jig is no need to be designed and manufactured, although the virtual DIMM jig and the virtual PCIE jig are needed to be used, the design and the manufacturing process are both simple. Outage for switching hardware in the testing process is not needed. Once the inserting connection of the hardware is finished, all tests can be completed at one time.
Description
Technical field
The present invention relates to computer motherboard field tests, particularly relate to a kind of mainboard CPU slot test method based on boundary scan and device.
Background technology
The test that on computer motherboard, each chip device connects is one of industry focus of seeking to raise the efficiency always.Wherein, the connecting test of CPU slot is a difficult point always.Because CPU pin closeness is high, and the contact pilotage on slot is all in tilted layout, and cannot test by the mode of lower thimble.Current industry adopts following two kinds of testing schemes usually to the connecting test of CPU slot.
The first testing scheme is: grafting CPU, start up system, tests connection by carrying out functional test.The shortcoming of this testing scheme is: functional test cannot be accurate to the connective rank of pin, and particularly for differential signal, the open circuit/short circuit fault of single circuit is difficult to display.
Another kind of testing scheme is: use tool, produced respectively by CPU pin, then concentrates and do continuity testing.The shortcoming of this testing scheme is: (1) due to CPU pin numerous, it is limited that single tool produces pin number, and test a CPU slot, need multiple tool, each tool completes the test of a part of pin, and change tool time need power-off.(2) for the CPU of difference encapsulation, such as, LGA1155, LGA1356, LGA1567, LGA2011, need to make different tool.(3) tool is very high to the requirement of manufacture craft, makes difficulty.(4) be limited to manufacture craft, it is limited that tool produces pin, even if use multiple tool, test coverage is still very low, usually only has about 11%.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The above-mentioned shortcoming existed in view of prior art and restriction, the present invention proposes a kind of connecting test method of the mainboard CPU slot based on boundary scan, and the method comprises the following steps:
Analyze the Boundary Sweep Description Language file of mainboard schematic diagram to be measured and mainboard CPU, extract the scan chain information of mainboard to be measured;
Extract the scanning element information corresponding to mainboard CPU slot connecting line on mainboard to be measured;
Testing and control main frame controls mainboard CPU to be measured by TAP controller and enters boundary scan pattern;
Run the test of polytype boundary scan, collect and analyzing responding result;
According to response results, judge whether mainboard to be measured exists fault and fault location.
The present invention also provides a kind of connecting test device of the mainboard CPU slot based on boundary scan, and this connecting test device comprises: testing and control main frame, TAP controller, mainboard to be measured;
This mainboard to be measured comprises mainboard CPU, and mainboard CPU can work in boundary scan pattern;
Testing and control main frame is used for test instruction and test data to be sent to TAP controller;
TAP controller is sent to each scan chain on mainboard to be measured for test data and test instruction being converted to JTAG signal, and sends to testing and control main frame to carry out collection analysis scan chain response data;
The JTAG signal that mainboard CPU is used for according to receiving works in boundary scan pattern, and in response to test data to TAP controller feedback scan chain response data;
Testing and control main frame judges whether mainboard CPU slot exists and connects fault and fault location.
Connecting test apparatus and method according to the mainboard CPU slot based on boundary scan of the present invention do not need to design and produce cpu signal adapting fixture, even if need to use virtual DIMM tool, Virtual PC IE tool, but tool designs, manufacture craft is all simpler.Do not need power-off to switch hardware in test process, after a hardware grafting completes, once complete whole test yet.Testing efficiency is improved, and whole test can complete within 30 seconds.And connecting test is the test of pin connectivity-level, connection fault accurately can be navigated to pin, and greatly promote test coverage.
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 illustrates the structured flowchart of the connecting test device of the mainboard CPU slot based on boundary scan provided according to one embodiment of present invention;
Fig. 2 illustrates the process flow diagram of the connecting test method of the mainboard CPU slot based on boundary scan provided according to one embodiment of present invention.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of embodiment and feature can combine with the element shown in one or more other accompanying drawing or embodiment and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.
Fig. 1 illustrates the structured flowchart of the connecting test device of the mainboard CPU slot based on boundary scan provided according to one embodiment of present invention.This connecting test device comprises: testing and control main frame 1, test access port controller (being called for short TAP controller) 2, mainboard 3 to be measured.Mainboard 3 to be measured comprises mainboard CPU 4, virtual DIMM tool 5 and Virtual PC IE tool 6, and CPU 4, virtual DIMM tool 5 and Virtual PC IE tool 6 all support boundary scan pattern.During test, grafting CPU 4 on the CPU slot 7 of mainboard, further, dimm socket and PCIE slot can distinguish the virtual DIMM tool 8 of grafting and Virtual PC IE tool 9, are carried out the connecting test of CPU slot by the connection testing CPU slot and virtual DIMM tool and Virtual PC IE tool.Testing and control main frame is connected with TAP controller 2 by usb 10, input test data, and all Test data generation, scheduling, collection, analysis all run with software mode on testing and control main frame 1.Testing and control main frame 1 can be personal computer (being called for short PC), server or workstation.TAP controller 2 is responsible for testing and control main frame 1 to become JTAG signal to be sent to each scan chain on mainboard 3 to be measured by the test data conversion that usb 10 sends, and JTAG response signal is sent to testing and control main frame 1 to carry out collection analysis.CPLD element (not shown) controls powering on of mainboard 3 to be measured, and powers to virtual DIMM 8 tool, Virtual PC IE 9 tool.CPU4, virtual DIMM tool 5 and Virtual PC IE tool 6 work in boundary scan pattern according to the jtag instruction signal received, and to TAP controller 2 feedback scan chain response data.Testing and control main frame 1 analyzing responding data, judge whether CPU slot 7 exists and connect fault and fault location.Testing and control main frame 1 and TAP controller 2 also can be connected by other communication modes, such as RS-232, RS-485 etc.
Fig. 2 illustrates the process flow diagram of the connecting test method of the mainboard CPU slot based on boundary scan provided according to one embodiment of the invention.For the Xeon E5-2620v3CPU of grafting on server DL360G9, this method of testing is also applicable to other server model and other CPU model.
The CPU of grafting on server DL360G9 adopts LGA2011 encapsulation, and comprise 2011 pins altogether, its pin can be divided into Types Below:
Storage channel (direct-connected between CPU and DDR) pin: 656;
Express passway interconnected (be called for short QPI, what refer between two CPU is direct-connected) pin: 168,84 groups of DC coupling differential signals can be divided into;
DMI (connecting through electric capacity between CPU and PCH) pin: 16,8 groups of AC coupling differential signals can be divided into;
PCI (connecting through electric capacity between CPU and PCIE slot) pin: 160,80 groups of AC coupling differential signals can be divided into;
Retain (be called for short Reserved, it does not connect) pin: 80;
Control inputs exports (CPU is to the control signal of the various circuit in outside) pin: 67;
Power supply (Power) pin: 233;
Ground (GND) pin: 631.
In above-mentioned pin, except Power, GND cannot use boundary scan means to test, all the other 1147 pins can be tested, and account for the total number of pins 57% of CPU.
In order to make, connecting test covering is above-mentioned all can survey pin, needs to use multiple boundary scan testing type, and often kind of test-types is tested as a son of whole CPU slot testing scheme, and cover part pin, multiple sub-testing sequence performs successively.The sub-test-types related to comprises:
(1) scan chain integrity test: check the whether stable effectively work of mainboard multi-strip scanning chain.
(2) pin sampling test: check whether CPU pin currency meets default, comprises the test to following pin, such as, part control inputs output pin, comprises the part pin of direct pullup/pulldown and checks the part pin of power supply status value.
(3) direct-connected interconnected test: follow IEEE 1149.1 specification (IEEE 1149.1Stand TestAccess Port and Boundary-Scan Architecture), comprise following pin, storage channel pin, QPI pin, and part control inputs output pin.The pin that the such as control pin of CPU and PCH, CPLD element is directly connected.
(4) autoexcitation is tested from response mode: comprise the test to Reserved pin.Such as, test Reserved pin A, then suppose that A is a gauze, excitation end is all A with responder.Can whether to be short-circuited with all the other gauzes fault by test pin A.
(5) the interconnected test of difference: follow IEEE 1149.6 specification, comprises DMI pin and PCI pin.
During test, first analyze the circuit diagram of mainboard to be measured, extract the link information of CPU slot.Then analyze the Boundary Sweep Description Language file of CPU on mainboard to be measured, virtual DIMM tool and Virtual PC IE tool, extract the scan chain information S201 on mainboard.According to above-mentioned scan chain information, extract the scanning element information S202 of CPU, virtual DIMM tool, Virtual PC IE tool.Testing and control main frame make test procedure enter boundary scan Mode S 203 by TAP controller control CPU and virtual DIMM tool and Virtual PC IE tool.According to the sub-test-types of above-mentioned multiple boundary scan, carry out connecting test to pin all can be surveyed, and collect, analyzing responding result S204.In above-mentioned test process, mainboard needs grafting CPU, and virtual DIMM tool, Virtual PC IE tool.According to response results, judge whether to there is fault and fault location S205.
Above-mentioned method of testing has the following advantages: do not need to design and produce cpu signal adapting fixture, although also need to use virtual DIMM, Virtual PC IE tool, tool designs, manufacture craft is all simpler.Do not need power-off to switch hardware in test process, after a hardware grafting completes, once complete whole test yet.Testing efficiency is improved, and whole test can complete within 30 seconds.And connecting test is the test of pin connectivity-level, connection fault accurately can be navigated to pin.Utilize boundary scan also to make test coverage greatly promote, the CPU pin of about 57% can be covered.
Above embodiment, although using virtual DIMM and Virtual PC IE as the connecting test parts with CPU slot, is not limited to virtual DIMM and Virtual PC IE.Also can using other chip pocket parts on mainboard to be measured as connecting test parts, if its scan chain meet can with the scan chain connecting test of grafting CPU connecting line on mainboard to be measured.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (7)
1., based on a connecting test method for the mainboard CPU slot of boundary scan, it is characterized in that, the method comprises the following steps:
Analyze the Boundary Sweep Description Language file of mainboard schematic diagram to be measured and mainboard CPU, virtual DIMM tool, Virtual PC IE tool, extract the scan chain information of mainboard to be measured;
Extract the scanning element information corresponding to described mainboard CPU slot connecting line to be measured;
Testing and control main frame enters boundary scan pattern by the described mainboard CPU to be measured of TAP controller control, virtual DIMM tool, Virtual PC IE tool;
Run the test of polytype boundary scan, collect and analyzing responding result;
According to response results, judge whether described mainboard to be measured exists fault and fault location.
2. connecting test method according to claim 1, it is characterized in that, the method also comprises, dimm socket during test on mainboard to be measured and PCIE slot be the virtual DIMM tool of grafting and Virtual PC IE tool respectively, testing and control main frame controls mainboard CPU to be measured by TAP controller, described virtual DIMM tool, described Virtual PC IE tool enter boundary scan pattern.
3. connecting test method according to claim 1, it is characterized in that, the test of described polytype boundary scan comprises: scan chain integrity test, pin sampling test, direct-connected interconnected test, autoexcitation are from response mode test, the interconnected test of difference.
4., based on a connecting test device for the mainboard CPU slot of boundary scan, this connecting test device comprises: testing and control main frame, TAP controller, mainboard to be measured;
This mainboard to be measured comprises mainboard CPU, and mainboard CPU can work in boundary scan pattern;
When connecting test, described testing and control main frame is used for test instruction and test data to be sent to described TAP controller,
Described TAP controller is sent to each scan chain on mainboard to be measured for described test data and test instruction being converted to JTAG signal, and the response data of each scan chain is sent to described testing and control main frame to carry out collection analysis,
The described JTAG signal that mainboard CPU is used for according to receiving works in boundary scan pattern, and in response to described test data to described TAP controller feedback scan chain response data,
Described testing and control main frame also connects fault and fault location for judging whether CPU slot exists.
5. connecting test device according to claim 4, it is characterized in that, described mainboard to be measured is also plugged with virtual DIMM tool and Virtual PC IE tool, for being connected with dimm socket and PCIE slot respectively, controlling mainboard CPU to be measured when testing by TAP controller, described virtual DIMM tool, described Virtual PC IE tool enter boundary scan pattern.
6. the connecting test device according to claim 4 or 5, it is characterized in that, described connecting test device is used for, to the test of described mainboard exercise boundary scanning to be measured, comprising: scan chain integrity test, pin sampling test, direct-connected interconnected test, autoexcitation are from response mode test, the interconnected test of difference.
7. the connecting test device according to any one of claim 4 to 6, is characterized in that, described connecting test device also comprises USB interface, and described testing and control main frame is connected with the communication of described TAP controller by described USB interface.
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Cited By (11)
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| CN106443086A (en) * | 2016-11-01 | 2017-02-22 | 郑州云海信息技术有限公司 | Test base plate |
| CN107480017A (en) * | 2017-08-02 | 2017-12-15 | 郑州云海信息技术有限公司 | The batch-testing device and method of PCIE outer plug-in cards |
| CN109813992A (en) * | 2017-11-21 | 2019-05-28 | 英业达科技有限公司 | Continuity testing method |
| CN109901045A (en) * | 2017-12-08 | 2019-06-18 | 英业达科技有限公司 | The connector plugging slot pin conduction detecting system and its method of circuit board |
| CN109901048A (en) * | 2017-12-09 | 2019-06-18 | 英业达科技有限公司 | With the system and method for different scanning chain test differential line |
| CN110794289A (en) * | 2019-11-26 | 2020-02-14 | 英业达科技有限公司 | Boundary scanning and function testing method and device for mainboard |
| CN112462246A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Boundary scan test system and method thereof |
| CN112882452A (en) * | 2019-11-29 | 2021-06-01 | 英业达科技有限公司 | Function verification system and method for boundary scan test controller |
| CN112882873A (en) * | 2019-11-30 | 2021-06-01 | 英业达科技有限公司 | System and method for testing memory module through internal circuit of memory module |
| TWI759379B (en) * | 2017-12-13 | 2022-04-01 | 英業達股份有限公司 | Central processing units of multi-circuit board differential detection system and method thereof |
| CN115859161A (en) * | 2023-02-20 | 2023-03-28 | 国家海洋技术中心 | Fault prediction method, device, terminal and storage medium |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106443086A (en) * | 2016-11-01 | 2017-02-22 | 郑州云海信息技术有限公司 | Test base plate |
| CN107480017A (en) * | 2017-08-02 | 2017-12-15 | 郑州云海信息技术有限公司 | The batch-testing device and method of PCIE outer plug-in cards |
| CN109813992A (en) * | 2017-11-21 | 2019-05-28 | 英业达科技有限公司 | Continuity testing method |
| CN109813992B (en) * | 2017-11-21 | 2021-04-27 | 英业达科技有限公司 | Connectivity test method |
| CN109901045A (en) * | 2017-12-08 | 2019-06-18 | 英业达科技有限公司 | The connector plugging slot pin conduction detecting system and its method of circuit board |
| CN109901048B (en) * | 2017-12-09 | 2021-04-27 | 英业达科技有限公司 | System and method for testing differential line by different scan chains |
| CN109901048A (en) * | 2017-12-09 | 2019-06-18 | 英业达科技有限公司 | With the system and method for different scanning chain test differential line |
| TWI759379B (en) * | 2017-12-13 | 2022-04-01 | 英業達股份有限公司 | Central processing units of multi-circuit board differential detection system and method thereof |
| CN112462246A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Boundary scan test system and method thereof |
| CN110794289B (en) * | 2019-11-26 | 2021-12-24 | 英业达科技有限公司 | Boundary scanning and function testing method and device for mainboard |
| CN110794289A (en) * | 2019-11-26 | 2020-02-14 | 英业达科技有限公司 | Boundary scanning and function testing method and device for mainboard |
| CN112882452A (en) * | 2019-11-29 | 2021-06-01 | 英业达科技有限公司 | Function verification system and method for boundary scan test controller |
| CN112882873A (en) * | 2019-11-30 | 2021-06-01 | 英业达科技有限公司 | System and method for testing memory module through internal circuit of memory module |
| CN115859161A (en) * | 2023-02-20 | 2023-03-28 | 国家海洋技术中心 | Fault prediction method, device, terminal and storage medium |
| CN115859161B (en) * | 2023-02-20 | 2023-07-28 | 国家海洋技术中心 | Fault prediction method, device, terminal and storage medium |
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