CN103558544A - Digital-analog hybrid circuit built-in test device based on boundary scan - Google Patents
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Abstract
The invention belongs to testability technologies, and relates to a digital-analog hybrid circuit BIT device based on boundary scan. The device is composed of a link scanning module, a boundary scan controller, a master controller, a test vector storage and a tested digital-analog hybrid circuit, the boundary scan controller and the master controller are needed in scan test execution, the test vector storage is loaded with test vectors, the device can achieve a BIT based on the boundary scan according to the characteristic of a digital-analog hybrid complex circuit, and therefore the test problem caused by the structure and cross link complexity of the digital-analog hybrid circuit can be effectively solved, and universal and reliable testability design is provided for the device. The fault detection and locating of the circuit can be facilitated, testing efficiency and reliability are improved, development and maintenance cost is lowered, and operational effectiveness and overall economic benefits are improved.
Description
Technical field
The present invention is a kind of Digital Analog Hybrid Circuits built-in test equipment based on boundary scan, belongs to testability technical field.
Background technology
Along with development and the application of large scale integrated circuit, the integrated level of Digital Analog Hybrid Circuits is more and more higher, structure is compacter, function becomes increasingly complex, Digital Analog Hybrid Circuits especially, and the complicacy of its circuit feature and crosslinked relation is increasing.This is when having promoted circuit engineering index; also the variation of fault mode, high coupling, high associated have been brought; and the reduction of test accessibility; thereby cause test cost shared ratio in Digital Analog Hybrid Circuits development overhead constantly to rise; the testability of Digital Analog Hybrid Circuits sharply declines; traditional testability designing technique can not meet the demand of Digital Analog Hybrid Circuits far away, and this has proposed stern challenge to fault diagnosis and the maintenance of equipment electronic equipment.
Built-in test (Built-in test, BIT) technology is that system or equipment relies on its inner testing circuit and detects the important means that software comes completion status monitoring, fault detect and isolation.But equip at present BIT design and exist the problems such as trouble diagnosibility is poor, false alarm rate is high, can not meet request for utilization far away.And be the method for additional testing circuit by increasing circuit test access point, can only promote Test coverage to sacrifice the cost of cost and resource, fundamentally do not improve traditional built-in test mentality of designing, very limited to improving the effect of testability, and realizability and versatility also poor.
Boundary scan testing (BST---Boundary Scan Test) technical development is eighties of last century nineties, by JTAG (Joint Test Action Group, be called for short JTAG) propose, it is by being present in boundary scan cell (the Boundary Scan Cell between device input and output pin and kernel circuitry, be called for short BSC) device and peripheral circuit thereof are tested, with " virtual probe ", replace physical probe to test and fault diagnosis.This Boundary-scan test technology has improved controllability and the ornamental of device, overcome the technology barrier in physical access restriction of complicated integrated circuit testing, a test difficult problem that improves the chip that brings and circuit for chip integration provides effectively and solution cheaply.Meanwhile, Boundary-scan test technology has realized in the situation that not affecting circuit normal operation, with very little hardware spending, completes test.
1988, IEEE and JTAG organize the joint development boundary scan testing framework of reaching an agreement, and formed IEEE1149.1 standard (IEEE test access port and boundary-scan architecture standard) in nineteen ninety, also referred to as JTAG standard, and follow-up constantly improve and the process of standard in, in 1993,1994 and calendar year 2001, announced standard revision version.Its latest edition is IEEE1149.1-2001, has comprised IEEE1149.1a and IEEE1149.1b standard, has defined test access port and boundary-scan architecture.The suggestion of standardization description boundary-scan architecture language has been proposed simultaneously.Meanwhile, IEEE1149.1 standard has derived IEEE1149.4, IEEE1149.5, IEEE1149.6 and the brand-new Series correlation standards such as IEEE1149.7.Current more than 90% complex chip all, with boundary scan mechanism, support JTAG standard, and these chips has all obtained supporting widely and applying.The testability design being applied as based on boundary scan of these chips provides the foundation.
Summary of the invention
The present invention designs a kind of Digital Analog Hybrid Circuits built-in test equipment based on boundary scan is provided for above-mentioned prior art situation just; its objective is that solving equipment BIT design at present exists that trouble diagnosibility is poor, false alarm rate is high, and traditional built-in test design optimization thinking cost is high, realizability and the poor problem of versatility.
The object of the invention is to be achieved through the following technical solutions:
The Digital Analog Hybrid Circuits built-in test equipment of this kind based on boundary scan, is characterized in that: this device comprises:
Scan chain circuit module (1), effect is according to IEEE1149 boundary scan standard, will in tested Digital Analog Hybrid Circuits (2), treat that the mode that diagnosing chip mixes with series, parallel or connection in series-parallel couples together, scan chain circuit module (1) comprising:
Simulating boundary module (6), simulating boundary module (6) is for mimic channel configuration in tested Digital Analog Hybrid Circuits (2), by scan chain (8), be connected with tested Digital Analog Hybrid Circuits (2), boundary scan controller (3) and digital boundary module (7), effect is the control based on boundary scan controller (3), realize the configuration of different switch, the boundary scan cell that meets IEEE1149 standard is connected to respectively the treating on diagnosing chip of artificial circuit part of tested Digital Analog Hybrid Circuits (2);
Digital boundary module (7), digital boundary module (7) is for digital circuit partial configuration in tested Digital Analog Hybrid Circuits (2), by scan chain (8), be connected with tested Digital Analog Hybrid Circuits (2), boundary scan controller (3) and simulating boundary module (6), effect is to meet the boundary scan cell of IEEE1149 standard for each requires the digit chip configuration of diagnosis;
Scan chain (8), the effect of scan chain (8) is to realize being connected of tested Digital Analog Hybrid Circuits (2) and simulating boundary module (6), digital boundary module (7), boundary scan controller (3) is connected with simulating boundary module (6), digital boundary module (7), and the connection between simulating boundary module (6) and digital boundary module (7);
This device also comprises:
Boundary scan controller (3), be connected with master controller (4) with scan chain circuit module (1), effect is that test vector is loaded into and is respectively treated in diagnosing chip by scan chain circuit module (1), and by the test rreturn value of scan chain circuit module (1) back production boundary scan, send to master controller (4) to diagnose;
Master controller (4), be connected with test vector storer (5) with boundary scan controller (3), effect is the test vector that calls storage in test vector storer (5), loading is to boundary scan controller (3), and receive the boundary scan testing rreturn value that boundary scan controller (3) sends, carry out fault diagnosis, generate diagnostic result;
Test vector storer (5), is connected with master controller (4), and effect is storage test vector, by master controller (4), is called; For the test vector of boundary scan fault detect, be according to the circuit meshwork list file of tested Digital Analog Hybrid Circuits (2) and respectively treat the BSDL(Boundary-Scan Description Language of diagnosing chip, Boundary Sweep Description Language) file generated.
Boundary scan controller (3) consists of system-level boundary scan controller and plate level boundary scan controller, wherein, it is core that system-level boundary scan controller be take MTM master control kernel, it is core from module kernel and TAP controller kernel that plate level boundary scan controller be take MTM, between system-level boundary scan controller and plate level boundary scan controller, with MTM bus, connects.
Switch matrix module (6) adopts STA400M chip.
Test vector is according to the circuit meshwork list file of tested Digital Analog Hybrid Circuits (2) and the BSDL file generated for the treatment of diagnosing chip.According to circuit meshwork list file and the BSDL file for the treatment of diagnosing chip, by net, show analytical algorithm and BSDL analytical algorithm, parsing obtains the required intermediate data of vector generation and comprises interconnect information, boundary scan instructions and the structural information existing between identification information, pinout information and each chip of respectively treating diagnosing chip, and in conjunction with net meter file and BSDL file, according to the scanning first-in-chain(FIC) chip of appointment, identify whole link structure; Combination algorithm generates intermediate data information and the link structure obtain, generates the test vector of storage in test vector storer (5) for node one by one.
The feature of apparatus of the present invention is the different characteristics for digital circuit in Digital Analog Hybrid Circuits and artificial circuit part; design switch matrix module and additional scanning structure; structure is applicable to the scan chain circuit module of Digital Analog Hybrid Circuits; and take scan chain circuit module as basis and medium; by master controller, system-level and plate level boundary scan controller, realize the built-in test based on boundary scan to hybrid digital analog circuit.
Advantage and beneficial effect that the present invention has are that apparatus of the present invention are the boundary scan techniques based on meeting IEEE1149 standard, in conjunction with electrical specification and the design feature of Digital Analog Hybrid Circuits, provide a kind of built-in test equipment towards Digital Analog Hybrid Circuits.It can realize general, standard, the built-in test reliably of logarithmic mode hybrid circuit, the problems such as accuracy of effectively solve that traditional insurmountable detecting information of testability designing technique and position are difficult to obtain, monitoring accuracy and diagnosis being located, facilitate the localization of fault of chip, the inhibition of support to false-alarm, fault coverage is high, Diagnostic Time is short, and the efficiency of test and with a high credibility is particularly suitable for the demand of product on-site maintenance; Simultaneously; the built-in test that can realize digital circuit and mimic channel designs the Uniting on software and hardware; realize reusable and the portable of built-in test design; reduced the complexity of Digital Analog Hybrid Circuits built-in test design; simplified the built-in test design effort of product, reduced and designed and developed cost.The present invention can improve product usefulness to a certain extent, reduces research and development and the maintenance cost of electronic equipment, improves whole economic efficiency.
Accompanying drawing explanation
Fig. 1 is composition and the structural representation of apparatus of the present invention
Fig. 2 is composition and the structural representation of apparatus of the present invention embodiment
Fig. 3 is the circuit diagram of system-level boundary scan controller in apparatus of the present invention
Fig. 4 is the software flow pattern of system-level boundary scan controller in apparatus of the present invention
Fig. 5 is the circuit diagram of plate level boundary scan controller in apparatus of the present invention
Fig. 6 is inner structure and the composition diagram of plate level boundary scan controller in apparatus of the present invention
Fig. 7 is the circuit diagram of digital boundary module in apparatus of the present invention
Fig. 8 is the circuit diagram of simulating boundary module in apparatus of the present invention
Fig. 9 is the inner structure schematic diagram of the STA400M chip that meets IEEE1149.4 standard that uses in apparatus of the present invention
Figure 10 is the scan chain schematic diagram building in apparatus of the present invention
Figure 11 is master controller software flow pattern in apparatus of the present invention
Figure 12 is the circuit diagram of test vector storer in apparatus of the present invention
Figure 13 is the process flow diagram of test vector generating algorithm
Figure 14 is step S1 in the generating algorithm process flow diagram of test vector: the software flow pattern of net meter file analytical algorithm
Figure 15 is the software flow pattern of step S2:BSDL document analysis algorithm in the generating algorithm process flow diagram of test vector
Figure 16 is step S3 in the generating algorithm process flow diagram of test vector: the software flow pattern of link structure recognizer
Figure 17 is step S4 in the generating algorithm process flow diagram of test vector: the software flow pattern of test vector generating algorithm
Embodiment
Below with reference to drawings and Examples, technical solution of the present invention is further described:
Shown in Figure 1, the Digital Analog Hybrid Circuits built-in test equipment of this kind based on boundary scan, is characterized in that: this device comprises:
Scan chain circuit module (1), effect is according to IEEE1149 boundary scan standard, will in tested Digital Analog Hybrid Circuits (2), treat that the mode that diagnosing chip mixes with series, parallel or connection in series-parallel couples together, scan chain circuit module (1) comprising:
Simulating boundary module (6), simulating boundary module (6) is for mimic channel configuration in tested Digital Analog Hybrid Circuits (2), by scan chain (8), be connected with tested Digital Analog Hybrid Circuits (2), boundary scan controller (3) and digital boundary module (7), effect is the control based on boundary scan controller (3), realize the configuration of different switch, the boundary scan cell that meets IEEE1149 standard is connected to respectively the treating on diagnosing chip of artificial circuit part of tested Digital Analog Hybrid Circuits (2);
Digital boundary module (7), digital boundary module (7) is for digital circuit partial configuration in tested Digital Analog Hybrid Circuits (2), by scan chain (8), be connected with tested Digital Analog Hybrid Circuits (2), boundary scan controller (3) and simulating boundary module (6), effect is to meet the boundary scan cell of IEEE1149 standard for each requires the digit chip configuration of diagnosis;
Scan chain (8), the effect of scan chain (8) is to realize being connected of tested Digital Analog Hybrid Circuits (2) and simulating boundary module (6), digital boundary module (7), boundary scan controller (3) is connected with simulating boundary module (6), digital boundary module (7), and the connection between simulating boundary module (6) and digital boundary module (7);
This device also comprises:
Boundary scan controller (3), be connected with master controller (4) with scan chain circuit module (1), effect is that test vector is loaded into and is respectively treated in diagnosing chip by scan chain circuit module (1), and by the test rreturn value of scan chain circuit module (1) back production boundary scan, send to master controller (4) to diagnose;
Master controller (4), be connected with test vector storer (5) with boundary scan controller (3), effect is the test vector that calls storage in test vector storer (5), loading is to boundary scan controller (3), and receive the boundary scan testing rreturn value that boundary scan controller (3) sends, carry out fault diagnosis, generate diagnostic result;
Test vector storer (5), is connected with master controller (4), and effect is storage test vector, by master controller (4), is called; For the test vector of boundary scan fault detect, be according to the circuit meshwork list file of tested Digital Analog Hybrid Circuits (2) and respectively treat the BSDL(Boundary-Scan Description Language of diagnosing chip, Boundary Sweep Description Language) file generated.
Boundary scan controller (3) consists of system-level boundary scan controller and plate level boundary scan controller, wherein, it is core that system-level boundary scan controller be take MTM master control kernel, it is core from module kernel and TAP controller kernel that plate level boundary scan controller be take MTM, between system-level boundary scan controller and plate level boundary scan controller, with MTM bus, connects.
Switch matrix module (6) adopts STA400M chip.
Test vector is according to the circuit meshwork list file of tested Digital Analog Hybrid Circuits (2) and the BSDL file generated for the treatment of diagnosing chip.According to circuit meshwork list file and the BSDL file for the treatment of diagnosing chip, by net, show analytical algorithm and BSDL analytical algorithm, parsing obtains the required intermediate data of vector generation and comprises interconnect information, boundary scan instructions and the structural information existing between identification information, pinout information and each chip of respectively treating diagnosing chip, and in conjunction with net meter file and BSDL file, according to the scanning first-in-chain(FIC) chip of appointment, identify whole link structure; Combination algorithm generates intermediate data information and the link structure obtain, generates the test vector of storage in test vector storer (5) for node one by one.
For temperature monitoring control system, the embodiment of apparatus of the present invention is shown in Figure 2, and described temperature monitoring control system is tested Digital Analog Hybrid Circuits (2), and it,, by sensor, gathers ambient temperature information; And by the processing to Information Monitoring, realize the monitoring of environment temperature, control and show, and the unit remaining under system failure state is switched.This system is typical Digital Analog Hybrid Circuits; by the output valve (analog quantity) of Comprehensive Control unit collecting temperature sensor and collection signal carried out to the conditionings such as filtering, noise reduction, finally pass through analog to digital conversion; the temperature signal that overall treatment unit receives after conversion carries out comprehensive analysis judgement, and when fault, indicates Comprehensive Control unit to carry out remaining switching.
While adopting apparatus of the present invention to carry out the built-in test based on boundary scan to system:
Boundary scan controller (3), comprises system-level boundary scan controller and plate level boundary scan controller, wherein:
System-level boundary scan controller selects the STM32F103ZET6 chip of ST company to realize, shown in Figure 3, and its kernel adopts standard C language design to realize, and its software flow pattern is shown in Figure 4;
Plate level boundary scan controller is realized with FPGA, and what select is the EP2C8Q208C8 chip of ALTERA company, shown in Figure 5.Its kernel is realized based on VerilogHDL hardware description language, inner structure is shown in Figure 6, mainly comprise MTM from module kernel and TAP controller kernel, the former has the RAM of a 32X32, TAP controller kernel is by RD, WR, DATA bus read-write RAM, realizes mutual between module kernel and TAP controller kernel of MTM.
System-level boundary scan controller is connected with master controller (4) by scan chain circuit module (1); plate level boundary scan controller is connected with tested Digital Analog Hybrid Circuits (2) by scan chain circuit module (1), and system-level boundary scan controller is connected by MTM bus with plate level boundary scan controller.
Scan chain circuit module (1), comprise simulating boundary module (6), digital boundary module (7) and scan chain (8), circuit structure, diagnostic requirements and device electrical specification that can be based on temperature monitoring control system, for dissimilar device, design realization by following mode:
1) for the built-in digit chip to be diagnosed of boundary scan cell in temperature monitoring control system, as the fpga chip EP2C8Q208C8 in master control borad, owing to itself including boundary scan cell and boundary scan dedicated pin, by scan chain (8), the boundary scan dedicated pin of itself and functional pin to be diagnosed are connected on the plate level boundary scan controller of boundary scan controller (3), have realized the function of scan chain circuit module (1);
2) for the digit chip to be diagnosed of built-in boundary scan cell not in temperature monitoring control system, as bus driver chip SN74HC8245, can be replaced with and there is identical function characteristic and with the bus driver SN74BCT8245 of boundary scan cell, form the digital boundary module (7) that this treats diagnosing chip.By scan chain (8), the boundary scan dedicated pin of SN74BCT8245 and functional pin to be diagnosed are connected on the plate level boundary scan controller of boundary scan controller (3), realized the function of scan chain circuit module (1).
3) in digit chip to be diagnosed, chip that is cannot be with functional characteristic identical and that replace with the chip of boundary scan cell, as STM32F103 chip, can be it and increase by one piece of SN74BCT8245 chip, and be connected in series on the fuction output pin of STM32F103 chip, by the SN74BCT8245 chip and the peripheral circuit thereof that increase, realized the design of digital boundary module (7), shown in Figure 7, by scan chain (8), the boundary scan dedicated pin of SN74BCT8245 and functional pin to be diagnosed are connected on the plate level boundary scan controller of boundary scan controller (3), realized the function of scan chain circuit module (1).
4) for analog device to be diagnosed, as amplifier, resistance, electric capacity etc., need design simulation boundary module (7), in this example, simulating boundary module (7) adopts the chip STA400M of NI company to realize, shown in Figure 8.By scan chain (8), the boundary scan dedicated pin of STA400M and functional pin to be diagnosed are connected on the plate level boundary scan controller of boundary scan controller (3) of design, realized the function of scan chain circuit module (1).STA400M is the chip that meets IEEE1149.4 standard, and it can be used as multiplexer switch by configuration in normal operation; And under test pattern, chip can provide the pin that meets IEEE1149.4 standard for mixed signal test, can complete interconnecting test, parameter testing and functional test to mixed signal circuit, its inner structure schematic diagram is shown in Figure 9.
Scan chain (8), design shown in Figure 10, it has been realized and has treated that diagnosing chip comprises between STM32F103ZET6, SN74BCT8245 and the digital boundary module (7) of 429 level transferring chip BD429, AD conversion chip ADS8317 and the simulating boundary module (6) of operational amplifier TLE2072, and being connected of simulating boundary module (6) and digital boundary module (7) and boundary scan controller (3).
Master controller (4), the STM32F103ZET6 chip of the Ye Shi ST company selecting, adopts C Programming with Pascal Language to realize.Its software flow pattern is shown in Figure 11.
Test vector storer (5), selects M25P64-VMF6P chip design to realize, shown in Figure 12.In test vector storer (5), the generation of the test vector of storage adopts host computer procedure to realize, and this host computer procedure is realized based on C Programming with Pascal Language, and the software flow pattern of its program is referring to shown in Figure 13-Figure 17.
This host computer procedure is by resolving the net meter file (Protel Netlist form) of being derived by circuit system schematic diagram and the BSDL file for the treatment of diagnosing chip, by net, show analytical algorithm and BSDL analytical algorithm, parsing obtains the required intermediate data of vector generation and comprises interconnect information, boundary scan instructions and the structural information existing between identification information, pinout information and each chip of respectively treating diagnosing chip, as shown in Figure 14 and Figure 15, and according to the scanning first-in-chain(FIC) chip of appointment, in conjunction with the information parsing, identify whole link structure, as shown in figure 16; Combination algorithm generates intermediate data information and the link structure obtain, generates test vector, as shown in figure 17 for node one by one.The test vector packing generating transfers to apparatus of the present invention by RS485/RS232 interface after downloading, and is stored in the test vector storer (5) of apparatus of the present invention.
During real work, master controller (4), after initialization, judges whether there is download request at time delay state, as Figure 11 step a1; If have, proceed to serial ports and interrupt, receive test vector data and write test vector storer (5), as Figure 11 step a2; Otherwise, after reaching duration, the test vector in read test vector memory (5), as Figure 11 step a3; And plate number is judged: if plate number is 0, be master control borad, load test vector to the plate level boundary scan controller of master control borad; If plate number is not 0, load test vector to system-level boundary scan controller, as Figure 11 step a4; Load after test vector, electric scanning self check in master controller (4) execution, enters while circulation, as Figure 11 step a5.
System-level boundary scan controller is after receiving master control instruction and test vector, and initialization MTM communication, as Fig. 4 step a1; And MTM instruction and test vector are sent to plate level boundary scan controller, as Fig. 4 step a2.
Plate level boundary scan controller receives test vector by MTM bus; by scan chain (8), test vector is passed to and respectively treats diagnosing chip in tested Digital Analog Hybrid Circuits (2); and the test rreturn value of being transmitted back by scan chain (8) reception; by MTM bus, return to system-level boundary scan controller, as shown in Figure 6.The test rreturn value of system-level boundary scan controller retaking of a year or grade plate level boundary scan controller passback, and return to master controller (4), as Fig. 4 step a3.
Master controller (4) the test rreturn value that periodically retaking of a year or grade boundary scan controller (3) feeds back in while circulation, by test rreturn value and test expectation value are analyzed, identify and locate the faults at different levels of temperature monitor control system, carry out fault diagnosis, as Figure 11 step a6; Master controller (4), when work, according to the result of fault diagnosis, judges whether to carry out remaining and switches, as Figure 11 step a7.
Claims (4)
1. the Digital Analog Hybrid Circuits built-in test equipment based on boundary scan, is characterized in that: this device comprises:
Scan chain circuit module (1), effect is according to IEEE1149 boundary scan standard, will in tested Digital Analog Hybrid Circuits (2), treat that the mode that diagnosing chip mixes with series, parallel or connection in series-parallel couples together, scan chain circuit module (1) comprising:
Simulating boundary module (6), simulating boundary module (6) is for mimic channel configuration in tested Digital Analog Hybrid Circuits (2), by scan chain (8), be connected with tested Digital Analog Hybrid Circuits (2), boundary scan controller (3) and digital boundary module (7), effect is the control based on boundary scan controller (3), realize the configuration of different switch, the boundary scan cell that meets IEEE1149 standard is connected to respectively the treating on diagnosing chip of artificial circuit part of tested Digital Analog Hybrid Circuits (2);
Digital boundary module (7), digital boundary module (7) is for digital circuit partial configuration in tested Digital Analog Hybrid Circuits (2), by scan chain (8), be connected with tested Digital Analog Hybrid Circuits (2), boundary scan controller (3) and simulating boundary module (6), effect is to meet the boundary scan cell of IEEE1149 standard for each requires the digit chip configuration of diagnosis;
Scan chain (8), the effect of scan chain (8) is to realize being connected of tested Digital Analog Hybrid Circuits (2) and simulating boundary module (6), digital boundary module (7), boundary scan controller (3) is connected with simulating boundary module (6), digital boundary module (7), and the connection between simulating boundary module (6) and digital boundary module (7);
This device also comprises:
Boundary scan controller (3), be connected with master controller (4) with scan chain circuit module (1), effect is that test vector is loaded into and is respectively treated in diagnosing chip by scan chain circuit module (1), and by the test rreturn value of scan chain circuit module (1) back production boundary scan, send to master controller (4) to diagnose;
Master controller (4), be connected with test vector storer (5) with boundary scan controller (3), effect is the test vector that calls storage in test vector storer (5), loading is to boundary scan controller (3), and receive the boundary scan testing rreturn value that boundary scan controller (3) sends, carry out fault diagnosis, generate diagnostic result;
Test vector storer (5), is connected with master controller (4), and effect is storage test vector, by master controller (4), is called; For the test vector of boundary scan fault detect, be according to the circuit meshwork list file of tested Digital Analog Hybrid Circuits (2) and respectively treat the BSDL(Boundary-Scan Description Language of diagnosing chip, Boundary Sweep Description Language) file generated.
2. the Digital Analog Hybrid Circuits built-in test equipment based on boundary scan according to claim 1; it is characterized in that: boundary scan controller (3) consists of system-level boundary scan controller and plate level boundary scan controller; wherein; it is core that system-level boundary scan controller be take MTM master control kernel; it is core from module kernel and TAP controller kernel that plate level boundary scan controller be take MTM, between system-level boundary scan controller and plate level boundary scan controller, with MTM bus, connects.
3. the Digital Analog Hybrid Circuits built-in test equipment based on boundary scan according to claim 1, is characterized in that: switch matrix module (6) adopts STA400M chip.
4. the Digital Analog Hybrid Circuits built-in test equipment based on boundary scan according to claim 1, is characterized in that: test vector is according to the circuit meshwork list file of tested Digital Analog Hybrid Circuits (2) and the BSDL file generated for the treatment of diagnosing chip.According to circuit meshwork list file and the BSDL file for the treatment of diagnosing chip, by net, show analytical algorithm and BSDL analytical algorithm, parsing obtains the required intermediate data of vector generation and comprises interconnect information, boundary scan instructions and the structural information existing between identification information, pinout information and each chip of respectively treating diagnosing chip, and in conjunction with net meter file and BSDL file, according to the scanning first-in-chain(FIC) chip of appointment, identify whole link structure; Combination algorithm generates intermediate data information and the link structure obtain, generates the test vector of storage in test vector storer (5) for node one by one.
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| CN103941175A (en) * | 2014-04-01 | 2014-07-23 | 无锡市同翔科技有限公司 | Boundary scan test system and method |
| CN104977523A (en) * | 2014-04-11 | 2015-10-14 | 瑞萨电子株式会社 | Semiconductor device, diagnostic test, and diagnostic test circuit |
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| CN107729276A (en) * | 2017-09-24 | 2018-02-23 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of method that classification built-in test is realized using boundary scan technique |
| CN108362370A (en) * | 2017-12-14 | 2018-08-03 | 中国航空工业集团公司上海航空测控技术研究所 | A method of improving airborne vialog built-in test coverage rate |
| CN109557458A (en) * | 2018-12-26 | 2019-04-02 | 中国电子科技集团公司第四十研究所 | One kind being suitable for electronic equipment digital-to-analog circuit embedded test system |
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| CN108362370A (en) * | 2017-12-14 | 2018-08-03 | 中国航空工业集团公司上海航空测控技术研究所 | A method of improving airborne vialog built-in test coverage rate |
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