CN104779202B - 一种制作阵列基板的方法及其阵列基板和显示装置 - Google Patents
一种制作阵列基板的方法及其阵列基板和显示装置 Download PDFInfo
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- 229910052719 titanium Inorganic materials 0.000 claims abstract description 34
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- 239000010703 silicon Substances 0.000 claims description 15
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 11
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910008479 TiSi2 Inorganic materials 0.000 description 3
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- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- -1 TiSi2 Chemical compound 0.000 description 1
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Abstract
本发明涉及一种制作阵列基板的方法及其阵列基板和显示装置,其中制作阵列基板的方法可以包括:形成包括源漏极和数据线的图形;形成非晶半导体薄膜层;退火,以便仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物。通过仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物,形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu或Ti层表面在后续工艺中的氧化腐蚀,有助于制造使用Cu或Ti的金属氧化物薄膜晶体管结构。
Description
技术领域
本发明涉及显示领域,特别涉及一种制作阵列基板的方法、使用该制作阵列基板的方法制作的阵列基板、和包括该阵列基板的显示装置。
背景技术
在现有的制作用于显示装置的薄膜晶体管的过程中,其中的电极(如栅极、源极、漏极)或电极引线(如栅线、数据线)通常需要使用低电阻金属(如Cu等)。但在使用这种金属的情况下,存在金属表面因氧化腐蚀而在诸多工序中受到制约的问题。换句话说,由于金属表面出现氧化腐蚀现象,而在诸多工序中限制了该金属的使用。
因此,在现有技术中迫切需要一种新的技术,来防止在制作包括薄膜晶体管的显示装置的过程中出现的金属电极表面氧化腐蚀。
发明内容
有鉴于此,本发明提供一种制作阵列基板的方法、使用该制作阵列基板的方法制作的阵列基板、和包括该阵列基板的显示装置,其能够解决或者至少缓解现有技术中存在的至少一部分缺陷。
根据本发明的第一个方面,提供一种制作阵列基板的方法,该方法可以包括下面的步骤:形成包括源漏极和数据线的图形;形成非晶半导体薄膜层;退火,以便仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物。
借助于本发明的制作阵列基板的方法,通过仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物,形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu层表面在后续工艺中的氧化腐蚀。本发明的制作阵列基板的方法使得在使用Cu的氧化物薄膜晶体管的制造工序中既可以防止源漏处低电阻金属Cu表面的氧化,又可以制造例如氧化铟镓锌InGaZnO(IGZO)、氧化铟锡锌InSnZnO(ITZO)、氮掺杂的氧化锌ZnON等的金属氧化物薄膜晶体管。
在本发明的一个实施例中,制作阵列基板的方法还可以包括下面的步骤:在形成包括源漏极和数据线的图形之前,在衬底上形成栅极和栅线、覆盖在栅极和栅线上的栅绝缘层、以及覆盖在栅绝缘层上的对应于栅极区域的有源层。
在本发明的另一个实施例中,其中形成包括源漏极和数据线的图形的步骤包括:形成金属薄膜层;通过构图工艺,将源漏极和数据线之外位置的金属薄膜层去除。
在本发明的再一个实施例中,制作阵列基板的方法还可以包括下面的步骤:将源漏极和数据线之外位置的非晶半导体薄膜层去除。
与申请人曾经提出的首先形成作为源漏极和数据线的金属薄膜层,然后在该金属薄膜层上形成非晶半导体薄膜层,接着退火,以便将至少部分该非晶半导体薄膜层转换成金属半导体化合物的方法相比,本发明的不同之处在于,在形成金属薄膜层之后,通过构图工艺,将源漏极和数据线之外位置的金属薄膜层去除,即,将未被源漏极和数据线占据的衬底表面上的金属薄膜层选择性去除,仅仅保留了作为源漏极和数据线位置的金属薄膜层。然后形成非晶半导体薄膜层,该非晶半导体薄膜层覆盖了源漏极和数据线位置的金属薄膜层以及未被源漏极和数据线位置的金属薄膜层占据的衬底其他区域的上表面。这里仅仅是为了形成非晶半导体薄膜层的方便,也可以仅仅在源漏极和数据线位置的金属薄膜层上直接形成非晶半导体薄膜层。随后的退火步骤仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物,因为覆盖在作为源漏极和数据线金属薄膜层上的非晶半导体薄膜层会与其下的金属薄膜层反应,从而形成金属半导体化合物层。在除了源漏极和数据线之外的其他位置由于并不存在金属薄膜层,因此并不存在将非晶半导体薄膜层转换成金属半导体化合物层的情况,例如覆盖在其他位置的非晶半导体薄膜层在退火过程中不与栅绝缘层(例如SiO2)和有源层(例如IGZO、ITZO、或ZnON等)反应。
采用本发明的制作阵列基板的方法与申请人曾经提出的上述制作阵列基板的方法相比,是另外一种防止金属薄膜层例如Cu层在后续工艺中的氧化腐蚀的思路,两者并不存在矛盾之处。
在本发明的又一个实施例中,制作阵列基板的方法还可以包括下面的步骤:形成钝化层,并且在与漏极、栅线和数据线对应的位置刻蚀钝化层以形成对应的通孔。
在本发明的再一个实施例中,制作阵列基板的方法还可以包括下面的步骤:在栅绝缘层上对应栅线位置,形成栅绝缘层过孔。
在本发明的一个实施例中,制作阵列基板的方法还可以包括下面的步骤:形成透明导电薄膜,通过构图工艺,在形成有通孔的钝化层上形成包括像素电极、栅线连接线以及数据线连接线的图形,其中漏极上的金属半导体化合物通过对应漏极的位置形成的通孔与像素电极电连接。
在本发明的另一个实施例中,其中金属薄膜层包括铜层或钛层。
在本发明的再一个实施例中,其中非晶半导体薄膜层包括α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层。
在本发明的又一个实施例中,其中金属半导体化合物包括铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、钛与α-硒的化合物。
在本发明的一个实施例中,其中金属薄膜层包括铜层。
在本发明的另一个实施例中,其中非晶半导体薄膜层包括α-硅层。
在本发明的再一个实施例中,其中金属半导体化合物包括铜的硅化物。
在本发明的又一个实施例中,其中非晶半导体薄膜层的厚度为10Å-50Å。
在本发明的一个实施例中,其中退火温度在200℃-280℃之间。
在本发明的另一个实施例中,其中退火步骤是在氮气气氛下进行的。
在本发明的再一个实施例中,其中有源层为金属氧化物层。
在本发明的又一个实施例中,其中金属氧化物层包括InGaZnO、InSnZnO或ZnON半导体层。
根据本发明的第二个方面,提供一种使用上述的制作阵列基板的方法制作的阵列基板。
通过使用上述的制作阵列基板的方法制作的阵列基板,仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物,形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu层表面在后续工艺中的氧化腐蚀。本发明的制作阵列基板的方法使得在使用Cu的氧化物薄膜晶体管的制造工序中既可以防止源漏处Cu的氧化,又可以制造例如氧化铟镓锌InGaZnO(IGZO)、氧化铟锡锌InSnZnO(ITZO)、氮掺杂的氧化锌ZnON等的金属氧化物薄膜晶体管。
根据本发明的第三个方面,提供一种显示装置,包括上述的阵列基板。
附图说明
图1示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图2示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图3示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图4示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图5示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图6示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图7示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
图8示意性示出了根据本发明一个实施例的制作阵列基板的方法的其中一个步骤。
附图标记说明
12-衬底;14-栅极;16-栅线;18-栅绝缘层;20-有源层;22a-源极;22b-漏极;22c-数据线;24-非晶半导体薄膜层;26a-源极金属半导体化合物层;26b-漏极金属半导体化合物层;26c-数据线区域的金属半导体化合物层;30-钝化层;32a-位于漏极对应位置的通孔;32b-位于栅线对应位置的通孔;32c-位于数据线对应位置的通孔;34-像素电极;36-栅线连接线;38-数据线连接线。
具体实施方式
下面结合本发明的附图1-8详细地描述本发明的各个实施例。
在本发明中提到的术语“形成”,应当包括广义地理解,例如可以采用化学气相沉积、分子束外延等本领域常用的方式进行。由于这些形成薄膜的方式有很多种,针对于不同的材料,有相对更加适合的形成工艺,因此在这里不再具体指出形成每种薄膜的工艺方法,因为这些方法并不是本发明的发明点所在。
图1示意性示出了根据本发明一个实施例的制作阵列基板的方法的步骤,在例如硅衬底的衬底12上首先形成栅极14、栅线16。栅线16在后续的工艺中用于连接各个晶体管的栅极14。即,在形成作为源漏极和数据线的金属薄膜层之前,在衬底12上形成栅极14和栅线16。至于作为源漏极和数据线的金属薄膜层,后面还将详细描述。
接着,如在图2中示出的,在栅极14、栅线16和未被栅极14、栅线16覆盖的衬底12的其余部分上形成栅绝缘层18,即形成了至少覆盖在栅极14和栅线16上的栅绝缘层18。在对应于栅极14区域的上方,在栅绝缘层18上形成有源层20,即形成了覆盖在栅绝缘层18上的对应于栅极14区域的有源层20。有源层20可以为金属氧化物层,例如氧化铟镓锌InGaZnO(IGZO)、氧化铟锡锌InSnZnO(ITZO)、或氮掺杂的氧化锌ZnON、或者非晶硅(α-硅)等半导体层。
然后,形成包括源漏极和数据线的图形,如在图3中示出的,在栅绝缘层18和有源层20的相应位置形成源极22a、漏极22b、数据线22c。其中形成包括源漏极和数据线的图形的步骤可以包括:形成金属薄膜层;在图3中没有示出完整的金属薄膜层,为了制作的便利,该金属薄膜层可以是覆盖整个有源区20和未被有源区20占据的整个栅绝缘层18的上表面(暴露的)。然后,通过构图工艺,将源漏极和数据线之外位置的金属薄膜层去除。在图3所示的附图中,已经通过构图工艺去除了源漏极和数据线之外位置的金属薄膜层,仅仅保留了将作为源极22a、漏极22b、数据线22c的金属薄膜层。金属薄膜层可以是铜层或钛层。备选的,也可以直接形成作为源极22a、漏极22b、数据线22c的金属薄膜层,这样可以省略构图工艺。
接着,形成非晶半导体薄膜层24,如在图4中示出的。为了制作方便,在将作为源极22a、漏极22b、数据线22c的金属薄膜层以及暴露的栅绝缘层18上表面和有源层20的上表面上形成非晶半导体薄膜层24。这里仅仅是为了形成非晶半导体薄膜层24的方便,在作为源极22a、漏极22b、数据线22c的金属薄膜层以及暴露的栅绝缘层18上表面和有源层20的上表面上形成非晶半导体薄膜层24。备选的,也可以仅仅在作为源极22a、漏极22b、数据线22c的金属薄膜层上直接形成非晶半导体薄膜层24。非晶半导体薄膜层24可以是α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层。优选的,非晶半导体薄膜层24的厚度为10Å-50Å。
然后退火,以便仅仅将源漏极和数据线上的非晶半导体薄膜层24转换成金属半导体化合物,如在图5中示出的。例如,图5中所示的源极金属半导体化合物层26a、漏极金属半导体化合物层26b、数据线区域的金属半导体化合物层26c。由于仅仅源漏极和数据线上的非晶半导体薄膜层24转换成金属半导体化合物,其余位置的非晶半导体薄膜层24并没有转换成金属半导体化合物,这是因为例如α-硅的非晶半导体薄膜层24与覆盖在其下的源极22a、漏极22b、数据线22c的金属薄膜层反应,形成了相应的金属半导体化合物,而其余位置的例如α-硅的非晶半导体薄膜层24不与覆盖在其下的栅绝缘层18、或有源层20反应。在本领域中,栅绝缘层18可以是低介电率非结晶氟化树脂或者高介电率金属氧化物例如SiO2等等。这些栅绝缘层18的材料在退火的过程中,不会与覆盖在其上的例如α-硅的非晶半导体薄膜层24反应。同样,有源层(例如IGZO、ITZO、或ZnON等)也不会与覆盖在其上的例如α-硅的非晶半导体薄膜层24反应。相反,α-硅的非晶半导体薄膜层24会与覆盖在其下的源极22a、漏极22b、数据线22c的金属薄膜层反应。在退火过程中,作为源极22a、漏极22b、数据线22c的金属薄膜层例如Cu层中的Cu原子将会扩散到非晶半导体薄膜层24例如α-硅层中,使得Cu原子与Si原子结合形成铜的硅化物,例如Cu5Si。Cu与Si之间具有较强的结合力,Cu5Si的粘合性很强,以致能够防止Cu与氧的结合,从而能够解决Cu的氧化腐蚀问题。为了形成更厚一些的铜的硅化物,例如Cu5Si,优选的,退火步骤是在氮气气氛下进行。优选的,在大约200℃-280℃之间的温度下进行退火。
优选的,金属半导体化合物,例如源极金属半导体化合物层26a、漏极金属半导体化合物层26b、数据线区域的金属半导体化合物层26c包括铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、钛与α-硒的化合物。本领域技术人员知晓的是,术语α指的是非晶态(amorphous)。
需要指出的是,作为源极22a、漏极22b、数据线22c的金属薄膜层也可以是钛Ti层,在这样的情况下,在退火过程中,Ti层中的Ti原子将会扩散到非晶半导体薄膜层24例如α-硅层中,使得Ti原子与Si原子结合形成钛的硅化物,例如硅化钛TiSi2。同样,Ti与Si之间具有较强的结合力,TiSi2的粘合性很强,以致能够防止Ti与氧的结合,从而能够解决Ti的氧化腐蚀问题。为了形成更厚一些的钛的硅化物,例如TiSi2,优选的,退火步骤是在氮气气氛下进行。
还需要指出的是,由于作为源极22a、漏极22b、数据线22c的金属薄膜层可以是铜层或钛层,非晶半导体薄膜层24可以是α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层,相应退火后形成的源极金属半导体化合物层26a、漏极金属半导体化合物层26b、数据线区域的金属半导体化合物层26c可以是铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、或者钛与α-硒的化合物,如在上面已经提到的,这一点本领域技术人员是不难理解的。
接着可以将源漏极和数据线之外位置的非晶半导体薄膜层24去除,如在图6中示出的。在图6中,在将源漏极和数据线之外位置的非晶半导体薄膜层24去除之后,将至少部分有源层20以及栅绝缘层18直接暴露。
然后,可以形成钝化层30,并且在与漏极、栅线和数据线对应的位置刻蚀钝化层30以形成对应的通孔,例如形成分别位于漏极、栅线和数据线对应位置的通孔32a、32b、32c,如在图7中示出的。在本发明的一个实施例中,在栅绝缘层18上对应栅线位置,形成栅绝缘层过孔。如在图7所示的附图中,可以看到对应于栅线位置形成的通孔32b贯穿了钝化层30和栅绝缘层18,直接将栅线16暴露。
在将钝化层30平坦化之后,形成透明导电薄膜,通过构图工艺,在形成有通孔的钝化层30上形成包括像素电极34、栅线连接线36以及数据线连接线38的图形,其中漏极上的金属半导体化合物26b通过对应漏极的位置形成的通孔与像素电极34电连接。
借助于本发明的制作阵列基板的方法,通过仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物,形成的金属半导体化合物可以防止金属薄膜层例如低电阻金属Cu或Ti层表面在后续工艺中的氧化腐蚀。本发明的制作阵列基板的方法使得在使用Cu或Ti的氧化物薄膜晶体管的制造工序中既可以防止源漏处Cu或Ti表面的氧化,又可以制造金属氧化物薄膜晶体管。然而如果采用本发明的制作阵列基板的方法,则既可以轻易解决这个问题,同时又可以有助于制造使用Cu或Ti的金属氧化物薄膜晶体管结构。
根据本发明的第二个方面,提供一种使用上述的制作阵列基板的方法制作的阵列基板。
通过使用上述的制作阵列基板的方法制作的阵列基板,通过仅仅将源漏极和数据线上的非晶半导体薄膜层转换成金属半导体化合物,形成的金属半导体化合物可以防止金属薄膜层例如Cu或Ti层表面在后续工艺中的氧化腐蚀。然而如果采用本发明的阵列基板,则既可以轻易解决这个问题,同时又可以有助于制造使用Cu或Ti的金属氧化物薄膜晶体管结构。
根据本发明的第三个方面,提供一种显示装置,其包括上述的阵列基板。
虽然已经参考目前考虑到的实施例描述了本发明,但是应该理解本发明不限于所公开的实施例。相反,本发明旨在涵盖所附权利要求的精神和范围之内所包括的各种修改和等同布置。以下权利要求的范围符合最广泛解释,以便包含每个这样的修改及等同结构和功能。
Claims (20)
1.一种制作阵列基板的方法,包括:
形成作为源漏极和数据线的金属薄膜层的图形;
在所述金属薄膜层的图形上形成非晶半导体薄膜层;
退火,以便仅仅将源漏极和数据线上的所述非晶半导体薄膜层转换成金属半导体化合物。
2.根据权利要求1所述的方法,还包括:
在形成包括源漏极和数据线的图形之前,在衬底上形成栅极和栅线、覆盖在所述栅极和栅线上的栅绝缘层、以及覆盖在所述栅绝缘层上的对应于所述栅极区域的有源层。
3.根据权利要求2所述的方法,其中形成作为源漏极和数据线的金属薄膜层的图形的步骤包括:
形成金属薄膜层;
通过构图工艺,将源漏极和数据线之外位置的金属薄膜层去除。
4.根据权利要求3所述的方法,还包括:
将源漏极和数据线之外位置的非晶半导体薄膜层去除。
5.根据权利要求4所述的方法,还包括:
形成钝化层,并且在与漏极、栅线和数据线对应的位置刻蚀所述钝化层以形成对应的通孔。
6.根据权利要求5所述的方法,还包括:
在栅绝缘层上对应所述栅线位置,形成栅绝缘层过孔。
7.根据权利要求6所述的方法,还包括:
形成透明导电薄膜,通过构图工艺,在所述形成有通孔的钝化层上形成包括像素电极、栅线连接线以及数据线连接线的图形,其中所述漏极上的金属半导体化合物通过对应漏极的位置形成的通孔与所述像素电极电连接。
8.根据权利要求1-6中任一项所述的方法,其中所述金属薄膜层包括铜层或钛层。
9.根据权利要求1-6中任一项所述的方法,其中所述非晶半导体薄膜层包括α-硅、α-锗、α-砷化镓、α-硫化砷或α-硒层。
10.根据权利要求1-6中任一项所述的方法,其中所述金属半导体化合物包括铜的硅化物、铜的锗化物、铜与α-砷化镓的化合物、铜与α-硫化砷的化合物、铜与α-硒的化合物、钛的硅化物、钛的锗化物、钛与α-砷化镓的化合物、钛与α-硫化砷的化合物、钛与α-硒的化合物。
11.根据权利要求8所述的方法,其中所述金属薄膜层包括铜层。
12.根据权利要求9所述的方法,其中所述非晶半导体薄膜层包括α-硅层。
13.根据权利要求10所述的方法,其中所述金属半导体化合物包括铜的硅化物。
14.根据权利要求1-6中任一项所述的方法,其中所述非晶半导体薄膜层的厚度为10Å-50Å。
15.根据权利要求1-6中任一项所述的方法,其中所述退火温度在200℃-280℃之间。
16.根据权利要求1-6中任一项所述的方法,其中所述退火步骤是在氮气气氛下进行的。
17.根据权利要求2-6中任一项所述的方法,其中所述有源层为金属氧化物层。
18.根据权利要求17所述的方法,其中所述金属氧化物层包括InGaZnO、InSnZnO或ZnON半导体层。
19.使用根据权利要求1-18中任一项所述的制作阵列基板的方法制作的阵列基板。
20.一种显示装置,包括根据权利要求19所述的阵列基板。
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