CN104777564B - A kind of chip support plate and preparation method thereof - Google Patents
A kind of chip support plate and preparation method thereof Download PDFInfo
- Publication number
- CN104777564B CN104777564B CN201510203362.5A CN201510203362A CN104777564B CN 104777564 B CN104777564 B CN 104777564B CN 201510203362 A CN201510203362 A CN 201510203362A CN 104777564 B CN104777564 B CN 104777564B
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- China
- Prior art keywords
- support plate
- glass
- chip support
- wafer
- light path
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4256—Details of housings
- G02B6/4257—Details of housings having a supporting carrier or a mounting substrate or a mounting plate
Abstract
The embodiments of the invention provide a kind of chip support plate and preparation method thereof, the electric interconnection circuit transmission loss that solves chip support plate in the prior art is big, glass through hole processing difficulties and the problem of poor radiation.The chip support plate includes：Silicon support plate and glass support plate；The glass support plate is bonded on the silicon support plate；The glass support plate surface is provided with electric interconnection circuit；Wherein, the glass support plate optimizes cell array provided with light path, and the silicon support plate is provided with via-hole array；The through hole of light path the optimization unit and the via-hole array of the light path optimization cell array is correspondingly arranged.
Description
Technical field
The present invention relates to technical field of electro-optical communication, more particularly to a kind of chip support plate and preparation method thereof.
Technical background
Chip in existing optical communications module need to be carried on a support plate, and by the electric interconnection circuit on support plate and
Through hole realizes the transmission and interconnection of photosignal.Chip support plate of the prior art generally uses silicon materials or glass material system
Into.However, larger transmission loss can be caused by preparing electric interconnection circuit on the chip support plate prepared using silicon materials.And if
Chip support plate is prepared using glass material, because glass material is difficult to, size is accurate, pattern is excellent leads to it is difficult to make
Hole；In addition, the heat dispersion of glass material is poor, it is unfavorable for the operation of optical communications module.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of chip support plate and preparation method thereof, solves prior art SMIS
The electric interconnection circuit transmission loss of piece support plate is big, glass through hole processing difficulties and the problem of poor radiation.
A kind of chip support plate provided in an embodiment of the present invention, including：Silicon support plate and glass support plate；The glass support plate bonding
On the silicon support plate；The glass support plate surface is provided with electric interconnection circuit；
Wherein, the glass support plate optimizes cell array provided with light path, and the silicon support plate is provided with via-hole array；It is described
The through hole of the lens and the via-hole array of light path optimization cell array is correspondingly arranged.
The embodiments of the invention provide a kind of preparation method of chip support plate, including：
Via-hole array is prepared on silicon support plate；
Light path optimization cell array is prepared in glass support plate；
The silicon support plate is bonded in the glass support plate, makes the light path optimization cell array and the via-hole array
Alignment, forms chip support plate；
Electric interconnection circuit is prepared in the glass support plate of the chip support plate.
A kind of chip support plate provided in an embodiment of the present invention and preparation method thereof, employs answering for silicon support plate and glass support plate
Close structure.By setting electric interconnection circuit in glass support plate, transmission loss is reduced.Meanwhile, prepared on silicon support plate logical
The technology difficulty in hole is low, and the clear size of opening prepared is accurate, pattern is excellent, and the good heat dispersion performance of silicon materials.Utilize this hair
The chip support plate and preparation method of bright embodiment, a kind of chip support plate are integrated with the advantage of two kinds of material support plates.
Brief description of the drawings
Fig. 1 is the structural representation for the chip support plate that one embodiment of the invention is provided.
Fig. 2 is the preparation flow schematic diagram for the chip support plate that one embodiment of the invention is provided.
Fig. 3 is the preparation flow schematic diagram for the chip support plate that one embodiment of the invention is provided.
Fig. 4 a~4e is the decomposing schematic representation for the chip support plate preparation flow that one embodiment of the invention is provided.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, further is made to the present invention below in conjunction with the accompanying drawings
Detailed description.
Fig. 1 is the structural representation for the chip support plate that one embodiment of the invention is provided.As shown in Figure 1：The chip support plate
Including：Silicon support plate 1 and glass support plate 2；Glass support plate 2 is bonded on silicon support plate 1；The surface of glass support plate 2 is provided with electric interconnection
Circuit 21；Wherein, glass support plate 2 optimizes cell array 22 provided with light path, and silicon support plate 1 is provided with via-hole array (via
array)11；The through hole of light path the optimization unit and via-hole array 11 of light path optimization cell array 22 is correspondingly arranged.The chip is carried
When in use, chip 3 is mounted in glass support plate 2 can form circuit with electric interconnection circuit 21 and be connected plate, in silicon support plate 1
On via-hole array 11 in insertion optical fiber can form optical path.
In an embodiment of the present invention, light path optimization cell array 22 is lens array (lens array).Now, in order to
The transmission loss in optical path is reduced, the refractive index of glass material at lens in lens working array, can be made to be higher than lens
The refractive index of surrounding glass material.Can so make transmission light be preferably limited in lens where passage in.Certain light path is excellent
Change cell array 22 can also using can improve the other forms of coupling efficiency between chip 3 and optical fiber, the present invention to this not
Limit.
In an alternative embodiment of the invention, in order to realize refractive index difference as described above at lens and around lens,
It can be adulterated in the glass material at lens and improve the dopant of refractive index, for example：ZrO2、TiO2、Al2O3、GeO2、P2O5
Deng；Or doping reduces the dopant of refractive index in the glass material around lens, for example：B2O3、F.The present invention is this to being formed
The specific method of refractive index difference and the species of dopant are not limited.
In an alternative embodiment of the invention, also antireflective optical film can be set in lens surface so that the printing opacity of lens
Effect more preferably, is reduced because of transmission loss caused by light reflection.In addition, setting antireflective optical film also to keep away in lens surface
Exempt from harmful effect of the reflected light to chip 3.For example, when chip 3 is the driving chip of vertical cavity laser (VCSEL), reflection
If light can deteriorate VCSEL luminescent properties into the driving chip, and by setting antireflective optical film to be prevented effectively from
This problem.
It will be understood by those skilled in the art that chip 3 can be any kind of an optical chip or electrical chip, this
The species for the chip 3 that invention is applicable chip support plate is not limited equally.
Fig. 2 is the preparation flow schematic diagram for the chip support plate that one embodiment of the invention is provided.As shown in Fig. 2 the chip
The preparation flow of support plate includes：
Step 201：Via-hole array is prepared on silicon support plate.
Step 202：Light path optimization cell array is prepared in glass support plate.
In an embodiment of the present invention, light path optimization cell array is lens array.Now, in order that transmission light it is more preferable
The passage being limited in where lens in, folding of the refractive index higher than glass material around lens of glass material at lens can be made
Penetrate rate.Specifically, it can be adulterated in the glass material at lens and improve the dopant of refractive index, or the glass around lens
The dopant of doping reduction refractive index in material.
Step 203：The silicon support plate is bonded in the glass support plate, make light path optimization cell array with it is described
Via-hole array is aligned, and forms chip support plate.
Step 204：Electric interconnection circuit is prepared in the glass support plate of the chip support plate.
The chip support plate for possessing silicon support plate and glass support plate composite construction is so just formd, electric interconnection circuit 21 is used for
Subsequently it is connected with chip formation circuit, via-hole array is used to insert optical fiber formation optical fibre channel, and light path optimization cell array is used for
Improve the coupling efficiency between chip and optical fiber.
In an embodiment of the present invention, in order to improve the preparation efficiency of chip support plate, it can be realized in wafer scale size
The batch production of chip support plate, is described in detail below by one embodiment.
Fig. 3 is the preparation flow schematic diagram for the chip support plate that one embodiment of the invention is provided.As shown in figure 3, the chip
The preparation flow of support plate includes：
Step 301：As shown in fig. 4 a, via-hole array 11 is prepared on Silicon Wafer (Silicon wafer), and delimited at least
One chip support plate region.The line of cut that at least one chip support plate region delimited in advance on Silicon Wafer is constituted.
Step 302：As shown in Figure 4 b, light path optimization cell array 22 is prepared on glass wafer (Glass wafer), and
At least one chip support plate region of chip support plate regional assignment on the correspondence Silicon Wafer.At least one chip support plate region
The line of cut delimited in advance on glass wafer is constituted.
It will be understood by those skilled in the art that operator can determine according to the size to be prepared chip support plate
The quantity in chip support plate region delimited on Silicon Wafer and glass wafer in advance.Operator both can be brilliant by whole Silicon Wafer and glass
Circle is prepared into a chip support plate, can also cut into Silicon Wafer and glass wafer according to the chip support plate region delimited many
Individual chip support plate.The present invention is not limited the quantity that chip support plate region delimited on Silicon Wafer and glass wafer.
It will be understood by those skilled in the art that as shown in Figure 4 b, light path optimizes the light path of cell array on glass wafer
Optimize number of openings of the element number fewer than via-hole array.Reason is, light path optimization unit is prepared on glass wafer
The technique of array is relative complex, therefore only needs to realize that making light path in the effective range of optical path optimizes unit in chip support plate
Array；For non-effective position, as light path optimization unit can not be made if being subsequently used for the scope of chip support plate cutting
Array.And making via-hole array technique is relatively simple on Silicon Wafer, directly through hole is made in the chip support plate region of delimitation
Array, this also contributes to the cutting speed of follow-up chip support plate.
Those skilled in the art are it is also understood that quantity and light path for through hole optimize the quantity of unit, Ke Yigen
Determined according to the demand of actual module, the present invention is equally not specifically limited to this.
Step 303：As illustrated in fig. 4 c, Silicon Wafer is bonded on glass wafer, light path is optimized cell array 22 with leading to
Hole array 11 is aligned.
In an embodiment of the present invention, for convenience by light path optimization cell array be aligned with via-hole array, such as Fig. 4 a with
Shown in 4b, alignment mark 41 and alignment mark 42 are pre-set respectively on Silicon Wafer and glass wafer.So when by silicon wafer
When circle is bonded on glass wafer, as long as making the alignment mark 41 on Silicon Wafer be aligned with the alignment mark 42 on glass wafer
.It is more convenient for using in the aligning process in order that obtaining these alignment marks, alignment mark may be designed to polygon.So only
Need each edge of the polygon alignment mark 42 on the polygon alignment mark 41 on Silicon Wafer and glass wafer and each
Angle is all aligned, and improves the matching on via-hole array 11 and glass wafer between light path optimization cell array 22 on Silicon Wafer
The degree of accuracy and alignment efficiency.
In an alternative embodiment of the invention, the alignment mark 41 on Silicon Wafer can be adopted with the alignment mark 42 on glass wafer
It is engaged with the mode of groove-projection.For example, when the alignment mark 41 on Silicon Wafer is groove, the alignment on glass wafer
Mark 42 is projection, when Silicon Wafer is bonded on glass wafer, as long as making the male cooperation enter the groove.Certainly
Can also be that alignment mark 41 on Silicon Wafer is that alignment mark 42 on projection, glass wafer is groove, the present invention to this not
Limit.In addition, when the groove/land is polygon, also further Silicon Wafer can be prevented to be moved with respect to glass wafer,
Improve the stability in chip support plate preparation process.
It will be understood by those skilled in the art that alignment mark on Silicon Wafer and glass wafer can be also used except upper described
Any form, the present invention is not limited the specific matched form of the alignment mark on Silicon Wafer and glass wafer.
It will be understood by those skilled in the art that multiple alignment marks can be also correspondingly arranged on Silicon Wafer and glass wafer, this
Invention is not limited the quantity of the alignment mark on Silicon Wafer and glass wafer.
Step 304：As shown in figure 4d, the electric interconnection in each chip support plate region of correspondence is prepared on the glass wafer
Circuit 21.
It is to be understood that, the quantity of electric interconnection circuit 21 is carried with the chip having on Silicon Wafer and glass wafer
The quantity in plate region is generally identical, i.e. the electric interconnection circuit 21 in each chip support plate region is independent.
Step 305：As shown in fig 4e, by the Silicon Wafer and glass wafer according at least one described chip support plate region
Cut at least one chip support plate.So just in the size of wafer scale once property batch form it is multiple possess silicon support plate and
The chip support plate of glass support plate composite construction, realizes the wafer scale batch production of chip support plate, had so both stabilized chip load
The quality of production of plate, reduces preparation cost again.
A kind of chip support plate provided in an embodiment of the present invention and preparation method, employ answering for silicon support plate and glass support plate
Close structure.By setting electric interconnection circuit in glass support plate, transmission loss is reduced.Meanwhile, prepared on silicon support plate logical
The technology difficulty in hole is relatively low, and the clear size of opening prepared is accurate, pattern is excellent, and the good heat dispersion performance of silicon materials.Utilize this
The chip support plate and preparation method of inventive embodiments, a kind of chip support plate can be with the advantages of integrated two kinds of material support plates.
These are only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution for being made etc. should be included in the scope of the protection.
Claims (12)
1. a kind of chip support plate, including：Silicon support plate and glass support plate；The glass support plate is bonded on the silicon support plate；Wherein,
The glass support plate optimizes cell array provided with light path, and the silicon support plate is provided with via-hole array；The light path optimizes unit
The through hole of light path the optimization unit and the via-hole array of array is correspondingly arranged, and the light path optimization cell array is lens array
Row, it is characterised in that the refractive index that the glass support plate surface is provided with glass material at electric interconnection circuit, the lens is high
The refractive index of glass material around the lens.
2. chip support plate according to claim 1, it is characterised in that be doped with raising folding at the lens in glass material
Penetrate the dopant of rate.
3. chip support plate according to claim 2, it is characterised in that the dopant of the raising refractive index includes following mix
One or more in miscellaneous dose：ZrO2、TiO2、Al2O3、GeO2、P2O5。
4. according to any described chip support plate in claims 1 to 3, it is characterised in that around the lens in glass material
It is doped with the dopant of reduction refractive index.
5. chip support plate according to claim 4, it is characterised in that the dopant of the reduction refractive index includes following doping
One or more in agent：B2O3、F。
6. chip support plate according to claim 1, it is characterised in that the lens surface sets antireflective optical film.
7. a kind of chip support plate preparation method, it is characterised in that including：
Via-hole array is prepared on silicon support plate；
Light path optimization cell array is prepared in glass support plate, wherein, the light path optimization cell array uses lens array, institute
State refractive index of the refractive index higher than glass material around the lens of glass material at lens；
The silicon support plate is bonded in the glass support plate, makes the light path optimization cell array and the via-hole array pair
Standard, forms chip support plate；
Electric interconnection circuit is prepared in the glass support plate of the chip support plate.
8. method according to claim 7, it is characterised in that produce the chip support plate in batches, then methods described includes：
Via-hole array is prepared on Silicon Wafer, and delimit at least one chip support plate region；
Prepare light path optimization cell array on glass wafer, and the chip support plate region on the correspondence Silicon Wafer also delimit to
A few chip support plate region；
The Silicon Wafer is bonded on the glass wafer, makes the light path optimization cell array and the via-hole array pair
It is accurate；
The electric interconnection circuit in each chip support plate region of correspondence is prepared on the glass wafer；
The Silicon Wafer and glass wafer are cut into at least one chip support plate according at least one described chip support plate region.
9. method according to claim 8, it is characterised in that the Silicon Wafer is bonded on the glass wafer, made
Light path optimization cell array be aligned with the via-hole array including：
Alignment mark is set respectively on the Silicon Wafer and the glass wafer；
Alignment mark on the Silicon Wafer is aligned with the alignment mark on the glass wafer.
10. method according to claim 9, it is characterised in that the alignment mark on the Silicon Wafer and glass wafer is adopted
Use polygon.
11. the method according to claim 9 or 10, it is characterised in that alignment mark and the glass on the Silicon Wafer
Alignment mark on glass wafer is engaged by the way of groove-projection.
12. the method according to claim 7 or 8, it is characterised in that preparing the lens array includes：
Doping improves the dopant of refractive index in the glass material at the lens；And/or,
The dopant of doping reduction refractive index in glass material around the lens.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510203362.5A CN104777564B (en) | 2015-04-24 | 2015-04-24 | A kind of chip support plate and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510203362.5A CN104777564B (en) | 2015-04-24 | 2015-04-24 | A kind of chip support plate and preparation method thereof |
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| CN104777564A CN104777564A (en) | 2015-07-15 |
| CN104777564B true CN104777564B (en) | 2017-08-11 |
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| US6737223B2 (en) * | 2000-08-07 | 2004-05-18 | Shipley Company, L.L.C. | Fiber optic chip with lenslet array and method of fabrication |
| JP2003215388A (en) * | 2002-01-25 | 2003-07-30 | Hitachi Metals Ltd | Optical fiber assembly with lens and manufacturing method therefor |
| US8265432B2 (en) * | 2008-03-10 | 2012-09-11 | International Business Machines Corporation | Optical transceiver module with optical windows |
| JP5877749B2 (en) * | 2012-03-29 | 2016-03-08 | 日東電工株式会社 | Manufacturing method of opto-electric hybrid board |
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