CN104766855B - 芯片装置及其制造方法 - Google Patents

芯片装置及其制造方法 Download PDF

Info

Publication number
CN104766855B
CN104766855B CN201410806933.XA CN201410806933A CN104766855B CN 104766855 B CN104766855 B CN 104766855B CN 201410806933 A CN201410806933 A CN 201410806933A CN 104766855 B CN104766855 B CN 104766855B
Authority
CN
China
Prior art keywords
chip
insulating layer
carrier
continuous insulating
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410806933.XA
Other languages
English (en)
Other versions
CN104766855A (zh
Inventor
J·马勒
P·施特罗贝尔
E·富尔古特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Publication of CN104766855A publication Critical patent/CN104766855A/zh
Application granted granted Critical
Publication of CN104766855B publication Critical patent/CN104766855B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/2957—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1426—Driver
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明的各个实施例涉及芯片装置及其制造方法。该芯片装置包括载体和被布置在载体之上的至少两个芯片，其中在该至少两个芯片之间以及在载体与至少两个芯片中的至少一个芯片之间布置有连续绝缘层。

Description

芯片装置及其制造方法
技术领域
各个实施例涉及一种芯片装置(chip arrangement)和制造芯片装置的方法。
背景技术
在本领域中，制造芯片装置的方法，尤其是制造多芯片装置的方法已经是众所周知的。在多芯片装置的情况下，通常多个芯片被侧对侧(side-by-side)地或者芯片对芯片(chip-by-chip)地布置，并且通过接触线、导体、键合接线等接触。在这类多芯片装置中，单个芯片之间的电绝缘非常重要，以便保持芯片装置的运行。因此，需要一种制造在不同芯片之间提供充分绝缘的多芯片装置的方法。
发明内容
各个实施例提供了一种芯片装置，该芯片装置包括：载体；以及，布置在载体之上的至少两个芯片；其中连续绝缘层布置在至少两个芯片之间并且布置在载体与至少两个芯片中的至少一个芯片之间。
此外，各个实施例提供了一种芯片装置，该芯片装置包括：载体；布置在载体上的第一芯片；以及，布置在连续绝缘层上并且布置在第一芯片旁边的第二芯片，其中连续绝缘层布置在第一芯片上。
而且，各个实施例提供了一种制造芯片装置的方法，该方法包括在载体上布置第一芯片；在连续绝缘层上布置第二芯片；以及，在布置在载体上的第一芯片上布置连续绝缘层。
附图说明
在附图中，贯穿不同的视图，相似的附图标记通常表示相同的部分。附图并不一定是按照比例绘制而成。相反，重点通常在于图示本发明的原理。在以下的说明中，将参考以下附图对各个实施例进行描述，在图中：
图1A至图1H示出了根据示例性实施例的制造芯片装置的方法步骤。
图2示出了制造芯片装置的方法的替代方法的一部分。
图3示出了制造芯片装置的方法的简化流程图。
具体实施方式
在以下说明中，将对半导体器件和制造半导体器件的方法的进一步示例性实施例进行阐释。应该注意，在一个具体示例性实施例的背景下描述的对具体特征的说明，也可以与其他示例性实施例结合。
词语“示例性”在本文中用于表示“用作示例、实例或者图示”。在本文中所描述的任何作为“示例性”的实施例或者设计不一定被解释为比其他实施例或者设计优选或有利。
各个实施例提供了一种芯片装置和制造芯片装置的方法，该芯片装置包括布置在载体或者芯片载体上的至少两个芯片，并且包括布置在该至少两个芯片中的第一芯片与该至少两个芯片中的第二芯片之间的连续绝缘层。
特别地，该至少两个芯片中的一个芯片可以是功率芯片，而另一个芯片可以是逻辑芯片。特别地，连续绝缘层可以是介电薄片，该介电薄片可以具有在2微米至100微米范围内的厚度，优选地，在5微米至50微米之范围内的厚度。例如，连续绝缘层可以通过化学气相沉积形成。
应该注意，连续绝缘层可以直接布置或者放置在第一芯片上，或者，附加元件或者层可以布置在第一芯片与连续绝缘层之间。
在制造芯片装置的方法中，具体地可以通过使连续绝缘层布置在第二芯片与载体之间的方式将连续绝缘层布置在第一芯片上。特别地，可以将多个第一芯片(例如，至少两个第一芯片)放置或者布置在载体上，例如，通过焊料或者粘合剂布置在载体上并且/或者固定至载体，并且/或者，可以将多个第二芯片放置在连续绝缘层(例如，介电薄片)上。优选地，可以将多个第一芯片和/或第二芯片彼此侧对侧地分别放置在载体和连续绝缘层上。应提及，术语“第一芯片”和“第二芯片”不一定意味着第一芯片和第二芯片在功能性上不同。这些术语确切地是指将一个或多个第一芯片放置在载体上而将一个或多个第二芯片放置在连续绝缘层上这一事实。例如，连续绝缘层可以是可扩展的或者有弹性的。
术语“连续层”可以特指例如绝缘材料的层，该层形成为单个连续均质层(例如，单个叠层(laminate layer))。在连续层中，不同分部(subsection)之间不存在不连续变化。由此，其必须与由不同分部或者不同子层(例如，包括粘合剂的分部和包括例如预浸料的另一分部)形成的层区分开来。
术语“在…之上”可以特指一个元件或者层布置在另一元件或者层的一侧上，但是，并不一定是直接在另一元件或者层上。即，术语“在…之上”不排除在其间布置有其他层或者元件。
根据芯片装置的示例性实施例，载体包括导电材料。
特别地，载体可以由导电材料组成。例如，载体可以是引线框架或者金属载体。可以使用的材料的示例是金属(例如，铜、银或者铝)、导电塑料和导电陶瓷等等。然而，作为替代方案，也可以使用非导电材料作为载体，例如(非导电)塑料或者(非导电)陶瓷。优选地，布置在载体之上或者布置在载体上的芯片电连至该载体。
根据芯片装置的示例性实施例，绝缘层包括具有200℃以上的熔化温度的材料。
特别地，熔化温度可以在250℃以上，例如，至少260℃，该温度通常用于焊接工艺。当使用具有在焊接温度以上的熔化温度或者分解温度的绝缘材料时，有可能可以在之后执行焊接步骤而不破坏绝缘层。
根据芯片装置的示例性实施例，绝缘层包括由下列各项组成的组中的至少一种材料：热固性材料、热塑性材料、橡胶材料、及其混合物。
通常，所使用的材料可以是具有在200℃以上的熔化温度或者分解温度的材料。特别地，热塑性材料或者塑性体材料可以是高质量材料。高质量材料可以特指具有在200℃以上(特别地，在250℃以上，例如，在260℃以上)的熔化温度或者分解温度的材料。
根据芯片装置的示例性实施例，连续绝缘体是叠层。
特别地，连续绝缘层可以由均质材料组成。由此，必须与拼接组成的层区分开来。
根据示例性实施例，芯片装置进一步包括布置在该至少两个芯片之上的包封层(encapsulation layer)。
特别地，包封层可以由模制材料形成，或者可以包括模制材料，并且/或者可以通过另外的(连续)层例如叠层形成，其布置在该至少两个芯片之上并且形成芯片装置的钝化的一部分。包封层可以具有在10微米至400微米范围内的厚度，优选地，在20微米至200微米范围内的厚度。
根据示例性实施例，芯片装置进一步包括延伸通过包封层的互连。
特别地，芯片装置可以仅仅包括延伸通过包封层的互连。即，载体可以不具有通过载体形成的任何互连。
根据芯片装置的示例性实施例，连续绝缘层适合于充当用于该至少两个芯片中的至少一个芯片的粘合材料。
根据芯片装置的示例性实施例，载体可以具有在100微米至1000微米范围内的厚度。
特别地，载体可以是引线框架或者叠层。然而，优选地，载体不是普通的印刷电路板。即，术语“载体”可以特指基本上二维的任何元件或支撑，其是自支撑的或者足够坚硬以支撑自身和布置在其上的芯片，但是其不由印刷电路板形成。
根据芯片装置的示例性实施例，连续绝缘层布置在第一芯片的至少三个侧处。
特别地，连续绝缘层在至少三个侧(例如，在五个侧)上覆盖第一芯片。例如，除了第一芯片布置在载体上的一侧之外，连续绝缘层可以在所有侧上覆盖第一芯片。
根据示例性实施例，芯片装置进一步包括包封层。
根据制造芯片装置的方法的示例性实施例，在将第二芯片布置在连续绝缘层上的情况下，连续绝缘层包括粘性的材料。
特别地，材料可以是预固化的材料。预固化的材料的示例可以是，例如，预固化的热固性材料、预固化的高质量热塑性塑性体材料。
根据示例性实施例，制造芯片装置的方法进一步包括：在将连续绝缘层布置在第一芯片上之前，在第二芯片的顶部上布置包封层。
根据示例性实施例，制造芯片装置的方法进一步包括：在将连续绝缘层布置在第一芯片上的期间，在第二芯片的顶部上布置包封层。
特别地，包封层可以是叠层或者叠片。根据本实施例，同时将包封层和连续绝缘层布置在第一芯片和载体上。
根的示例性实施例，制造芯片装置的方法进一步包括：在将包封层布置在载体之上以后，对包封层进行开口。
特别地，可以通过形成过孔、通孔、沟槽、阱等等来将包封层结构化，这些过孔、通孔、沟槽、阱等可以例如在后来通过金属化或者通过导电材料而被填充用于形成导体。
根据制造芯片装置的方法的示例性实施例，对包封层进行开口由激光器执行。
作为替代方案或者另外地，可以通过蚀刻或者适于设置延伸通过包封层的过孔或者通孔的任何其他工艺步骤，来执行该开口操作。
根据制造芯片装置的方法的示例性实施例，将多个第二芯片布置在连续绝缘层上。
例如，通过在连续绝缘层上布置包括多个芯片(例如，功率芯片和/或逻辑芯片)的晶片，可以同时执行布置多个第二芯片。作为替代方案，可以将多个芯片相继地或者彼此分开地放置在连续绝缘层上。在将多个第二芯片布置在连续绝缘层上之后，可以使相同的连续绝缘层扩展，从而使第二芯片彼此之间具有预定的距离。应提及，还可以将多个第一芯片同时地或者相继地放置在载体上。
根据示例性实施例，制造芯片装置的方法进一步包括单片化步骤。
通过单片化，可以形成多个芯片装置，每个芯片装置包括至少两个芯片，例如，至少一个或者两个功率芯片和至少一个逻辑芯片。特别地，单片化可以包括扩展工艺。例如，载体和/或连续绝缘层可以包括可扩展材料，或者可以由可扩展材料形成，可扩展材料可以扩展从而增加侧对侧布置的芯片之间的间距。
总结示例性实施例的要点可以是提供一种芯片装置，例如桥式电路，其包括至少一个半桥和至少一个驱动电路，包括在芯片的上主表面和下主表面上的叠层或者包封层，这些芯片布置或者放置在载体或者芯片载体上并且与也与布置在载体上的其他芯片电连接。由此，连续绝缘层可以在布置或者固定至载体的不同芯片之间形成绝缘层，以及此外，作为用于已经布置在载体上的芯片的保护或者覆盖层。特别地，可以形成多芯片装置。
各种芯片装置或者制造芯片装置的方法的示例性实施例可以提供下列优点中的一种或者多种优点。在使用连续绝缘层的情况下，不必使用附加的或者具体的粘合剂来将芯片固定在载体上。在使用预固化的热固性或者热塑性材料的情况下，这可以特别是真的。另外，有可能可以提供具有均质层厚度的绝缘层，由此提供均质隔离强度。另外，根据需要，有可能可以选择连续绝缘层的材料，例如，提供高隔离强度的材料。进一步有可能的是不同层的材料彼此适应，尤其是就热膨胀系数(CET)和/或就弹性系数而言。由此，有可能的是芯片装置可以具有改善的可靠性。如果芯片的侧壁被连续绝缘层覆盖，那么，有可能的是芯片的金属部件(例如，接触焊盘)可能不会与芯片装置的其他部件或者材料发生反应，例如，可以减少CuSi的形成。根据具体的实施例，有可能减少或者消除在芯片之间使用预浸料材料或者使用预浸料材料作为包封层的一部分。连续绝缘层还可以提供对芯片的底侧或者下侧的完全覆盖。此外，使用连续绝缘层可以实现并且简化制造方法的平行化。
下面的详细说明参考以图示的方式示出了可以实践本发明的具体细节和实施例的附图。
图1A示出了根据示例性实施例的芯片装置(例如，桥式电路)的制造方法的第一步骤150。特别地，将多个芯片101(例如，功率芯片)布置在载体102(例如，引线框架或者导电载体)上，并且将其电连至相同的载体102。可以通过导电材料103(例如，导电粘合剂、纳米膏等等)将芯片焊接或者键合(例如，在300℃以上的温度下)至载体或者固定至载体。
图1B示出了制造方法的第二步骤151。特别地，以预定距离或者间距将多个另外的芯片104(例如，应该与多个芯片101绝缘的逻辑芯片、驱动芯片、存储器芯片或者传感器芯片)布置或者放置在连续绝缘或者介电层105(例如，具有5微米至50微米的厚度的叠层薄片)上。介电层105可以包括或者可以由预固化的热固性材料或者高质量热塑性材料组成。介电层或者叠层薄片105可以被填充或者不填充并且/或者可以被纤维玻璃加固。
图1C示出了制造方法的第三步骤152。特别地，可以提供具有约20微米至200微米厚度的另外的叠层或者叠层片106，并且，该另外的叠层或者叠层片106可以包括与介电层105相同或者不同的材料。可选地，叠层106可以包括多个子层107。
图1D示出了制造方法的第四步骤153。特别地，将叠层106布置在多个另外的芯片104上，并且，通过锁合(positive fit)，以及/或者通过在压力(例如，100千帕到10,000千帕)和/或升高的温度(例如，150℃与300℃之间的温度)下的粘合连接，将其固定至介电层105。由此，将多个芯片104在两侧包封。
图1E示出了制造方法的第五步骤154。特别地，将图1D的多层结构(双侧叠层芯片或者器件)固定至载体101和布置在其上的多个芯片101，该多个芯片101通过锁合和/或通过在压力和/或升高的温度下粘合连接而布置在载体上。在图1F中示出了结果(该第五步骤的复合合成物107)。
图1G示出了制造方法的第六步骤155的结果。特别地，可以通过常用工艺步骤(例如，过孔、通孔和/或沟槽)进一步加工复合合成物107，这些过孔、通孔和/或沟槽可以形成并且在后来可以通过金属化108被填充，从而形成至包封的芯片的电连接、互连和/或再分布(redistribution)。
图1H示出了制造方法的第七步骤156的结果。特别地，可以使复合合成物107分开或单片化，从而形成多个多芯片装置109。优选地，每个芯片装置可以包括，布置在(导电)载体上并且电连至(导电)载体的至少两个第一芯片、以及布置在两个第一芯片之间并且通过连续绝缘层与两个第一芯片电隔离的至少一个第二芯片。两个第一芯片可以形成半桥，而第二芯片可以是驱动芯片或者包括驱动电路。
图2示出了芯片装置的制造方法的替代方法的一部分。从原理上说，替代方法可以与结合图1A至图1H所描述的方法相似。然而，第四和第五步骤153和154可以一起执行。即，将叠层片106布置到介电薄片105(在其上放置有多个芯片104)上、与将介电薄片105布置到载体102上，同时执行。其他制造方法可以与结合图1A至图1H所描述的示例性实施例相对应。
应该注意，可以通过拾取和放置工艺，将多个另外的芯片104和/或多个芯片101分别放置或者布置在介电薄片105和载体102上，即作为单个芯片。作为替代方案，可以在平行工艺中布置它们，例如以在介电薄片105或者载体102上放置晶片的形式。在使用该平行技术的情况下，可能优选的是，将可扩展的粘性叠层薄片布置到包括单片化(例如，通过扩展所谓的锯切薄片而被单片化)的芯片的晶片上，即，执行再叠层步骤。接着，可以使可扩展叠层薄片扩展，从而在单个芯片之间实现预定的间距。然后，可以将包括单片化的芯片的扩展叠层薄片连接至介电薄片105，并且然后连接至载体102。
图3示出了制造芯片装置300的方法的简化流程图。特别地，该方法可以包括：将第一芯片，特别地为半导体芯片(例如，逻辑芯片、功率芯片或者半桥电路)，布置或者固定在载体(例如，引线框架或者导电载体301)上。此外，该方法包括：将第二芯片(例如，驱动电路或者驱动芯片或者存储器芯片或者传感器芯片)布置在连续绝缘层302上，然后将连续绝缘层302布置在已经布置在载体303上的第一芯片上。可选地，例如通过将包封层布置到第二芯片上、在包封层中形成孔和/或沟槽、在孔和/或沟槽中形成互连等等，对多层结构进行进一步加工。由此，可以形成多芯片装置或者器件，其中芯片通过布置在芯片之间的连续绝缘层彼此电隔离。
应该注意，术语“包括”并不排除其他元件或者特征，并且，“一”或者“一个”并不排除复数。同样，结合不同实施例所描述的元件可以进行组合。还应该注意，参考符号不应该被解释为限制权利要求书的范围。虽然已经参考具体实施例对本发明进行了具体地示出和描述，但是本领域中的技术人员应该理解，在不脱离由所附权利要求书限定的本发明的精神和范围的情况下，可以对形式和细节进行各种改变。由此，本发明的范围由所附权利要求书指定，并且因此，旨在囊括落入权利要求书的等同物的意义和范围内的所有变化。

Claims (18)

1.一种芯片装置，包括：
载体；以及
被布置在所述载体之上的至少两个芯片，其中每个芯片都包括顶表面、底表面、以及在所述顶表面与所述底表之间延伸的横向侧壁；
其中连续绝缘层被布置在所述载体与所述至少两个芯片中的至少一个芯片之间，并且进一步地在所述至少两个芯片的所述横向侧壁之间竖直地延伸，
其中所述连续绝缘层适合于充当用于所述至少两个芯片中的所述至少一个芯片的粘合材料，并且所述连续绝缘层是可扩展的或者有弹性的。
2.根据权利要求1所述的芯片装置，其中所述载体包括导电材料。
3.根据权利要求1所述的芯片装置，其中所述绝缘层包括具有200℃以上的熔化温度的材料。
4.根据权利要求1所述的芯片装置，其中所述绝缘层包括由下列各项组成的组中的至少一种材料：
热固性材料；
热塑性材料；
橡胶材料；以及
上述几种材料的混合物。
5.根据权利要求1所述的芯片装置，
其中所述连续绝缘层是叠层。
6.根据权利要求1所述的芯片装置，进一步包括：被布置在所述至少两个芯片之上的包封层。
7.根据权利要求6所述的芯片装置，进一步包括：延伸通过所述包封层的互连。
8.根据权利要求1所述的芯片装置，
其中所述载体具有在100微米至1000微米范围内的厚度。
9.一种芯片装置，包括：
载体；
被布置在所述载体上的第一芯片；
被布置在连续绝缘层上并且在所述第一芯片旁边的第二芯片，其中所述连续绝缘层被布置在所述第一芯片之上，
其中所述连续绝缘层适合于充当用于所述第二芯片的粘合材料，并且所述连续绝缘层是可扩展的或者有弹性的。
10.根据权利要求9所述的芯片装置，
其中所述连续绝缘层被布置在所述第一芯片的至少三个侧上。
11.根据权利要求9所述的芯片装置，进一步包括包封层。
12.一种制造芯片装置的方法，所述方法包括：
在载体上布置第一芯片；
在连续绝缘层上布置第二芯片；以及
随后在被布置在所述载体上的所述第一芯片上布置所述连续绝缘层，所述连续绝缘层具有被布置在其上的多个第二芯片，
其中所述连续绝缘层是可扩展的或者有弹性的。
13.根据权利要求12所述的方法，
其中在将所述第二芯片布置在所述连续绝缘层上时，所述连续绝缘层包括粘性的材料。
14.根据权利要求12所述的方法，进一步包括：
在被布置在所述载体上的所述第一芯片上布置所述连续绝缘层之前，在所述第二芯片的顶部上布置包封层。
15.根据权利要求12所述的方法，进一步包括：
在被布置在所述载体上的所述第一芯片上布置所述连续绝缘层期间，在所述第二芯片的顶部上布置包封层。
16.根据权利要求14所述的方法，进一步包括：在所述载体之上布置所述包封层之后，对所述包封层进行开口。
17.根据权利要求16所述的方法，其中对所述包封层进行开口是通过激光器执行的。
18.根据权利要求12所述的方法，进一步包括单片化步骤。
CN201410806933.XA 2014-01-05 2014-12-22 芯片装置及其制造方法 Active CN104766855B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/147,547 2014-01-05
US14/147,547 US9349680B2 (en) 2014-01-05 2014-01-05 Chip arrangement and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN104766855A CN104766855A (zh) 2015-07-08
CN104766855B true CN104766855B (zh) 2018-10-16

Family

ID=53443386

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410806933.XA Active CN104766855B (zh) 2014-01-05 2014-12-22 芯片装置及其制造方法

Country Status (3)

Country Link
US (1) US9349680B2 (zh)
CN (1) CN104766855B (zh)
DE (1) DE102015100001B4 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269887B1 (en) * 2015-01-06 2016-02-23 Triquint Semiconductor, Inc. Ultrathin flip-chip packaging techniques and configurations
CN105118820B (zh) * 2015-07-21 2017-12-19 三星半导体(中国)研究开发有限公司 封装件及其制造方法、封装堆叠结构及其制造方法
DE102017201584A1 (de) 2017-02-01 2018-08-02 Robert Bosch Gmbh Kontaktanordnung und Verfahren zur Herstellung einer Kontaktanordnung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465412A (zh) * 2013-09-17 2015-03-25 英飞凌科技股份有限公司 芯片封装及其制造方法和芯片组件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
US7868465B2 (en) 2007-06-04 2011-01-11 Infineon Technologies Ag Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier
US7612457B2 (en) 2007-06-21 2009-11-03 Infineon Technologies Ag Semiconductor device including a stress buffer
US7847375B2 (en) 2008-08-05 2010-12-07 Infineon Technologies Ag Electronic device and method of manufacturing same
US7994646B2 (en) 2008-12-17 2011-08-09 Infineon Technologies Ag Semiconductor device
US8580612B2 (en) 2009-02-12 2013-11-12 Infineon Technologies Ag Chip assembly
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8975711B2 (en) * 2011-12-08 2015-03-10 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
KR101818507B1 (ko) * 2012-01-11 2018-01-15 삼성전자 주식회사 반도체 패키지
US8648473B2 (en) 2012-03-27 2014-02-11 Infineon Technologies Ag Chip arrangement and a method for forming a chip arrangement

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465412A (zh) * 2013-09-17 2015-03-25 英飞凌科技股份有限公司 芯片封装及其制造方法和芯片组件及其制造方法

Also Published As

Publication number Publication date
CN104766855A (zh) 2015-07-08
US20150194377A1 (en) 2015-07-09
DE102015100001B4 (de) 2020-03-26
US9349680B2 (en) 2016-05-24
DE102015100001A1 (de) 2015-07-09

Similar Documents

Publication Publication Date Title
KR102071522B1 (ko) 극박의 매설식 다이 모듈 및 그 제조 방법
CN107123632B (zh) 电性接合薄膜及其制造方法
US20190088636A1 (en) Laminated interposers and packages with embedded trace interconnects
US20170256474A1 (en) Module
JP2013243345A5 (zh)
JP2010205772A (ja) Ｉｃ搭載基板、プリント配線板、及び製造方法
US20130075928A1 (en) Integrated circuit and method of making
KR102194718B1 (ko) 임베디드 기판 및 임베디드 기판의 제조 방법
CN104766855B (zh) 芯片装置及其制造方法
US9892984B2 (en) Embedded electronic packaging and associated methods
JP6235575B2 (ja) 部品内蔵基板の製造方法及び部品内蔵基板
JP4798237B2 (ja) Ｉｃ搭載基板、及び多層プリント配線板
CN103400810A (zh) 半导体芯片的层叠封装结构及其制造方法
US20140014398A1 (en) Coreless subtrate and method of manufacturing the same
US20170020001A1 (en) Method for producing a printed circuit board with an embedded sensor chip, and printed circuit board
US11380650B2 (en) Batch manufacture of component carriers
US20150111344A1 (en) Method of fabricating a circuit
US20140124254A1 (en) Non-solder mask defined copper pad and embedded copper pad to reduce packaging system height
CN104952839B (zh) 封装装置及其制作方法
US20210358883A1 (en) Fan-out packaging method employing combined process
CN104701185B (zh) 封装基板、封装结构以及封装基板的制作方法
TW201711145A (zh) 具有內建金屬塊以及防潮蓋之散熱增益型線路板及其製備方法
US20110297427A1 (en) Printed circuit board and a method of manufacturing the same
US9466553B2 (en) Package structure and method for manufacturing package structure
KR20160149733A (ko) 칩 내장형 인쇄회로기판 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant