CN104733439A - Testing of Semiconductor Devices and Devices, and Designs Thereof - Google Patents

Testing of Semiconductor Devices and Devices, and Designs Thereof Download PDF

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Publication number
CN104733439A
CN104733439A CN201410795551.1A CN201410795551A CN104733439A CN 104733439 A CN104733439 A CN 104733439A CN 201410795551 A CN201410795551 A CN 201410795551A CN 104733439 A CN104733439 A CN 104733439A
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China
Prior art keywords
metal wire
voltage
metal
shielding conductor
semiconductor device
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Granted
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CN201410795551.1A
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Chinese (zh)
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CN104733439B (en
Inventor
S.阿雷素
M.勒纳
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Infineon Technologies AG
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Infineon Technologies AG
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
    • G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
    • G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01—ELECTRIC ELEMENTS
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
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    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a testing of semiconductor devices and devices, and the designs thereof. In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.

Description

The test of semiconductor device and device and design thereof
Technical field
The present invention relates generally to semiconductor device, and relate more specifically to the test of semiconductor device and device and design thereof.
Background technology
Semiconductor device is used in various electronic application such as personal computer, cell phone, digital camera and other electronic equipment exemplarily.Generally by the sequentially insulation of deposition materials or dielectric layer, conductive layer and semiconductor layer use photolithographic patterning various layer to form circuit block thereon and element manufactures semiconductor device on Semiconductor substrate.
One of challenge be associated with semiconductor manufacturing relates to product yield and/or reliability.The consumer of semiconductor device expects the reliability of certain level from its device.When using semiconductor device in safety-critical application, this is more important.But due to the defect introduced during manufacture, product may be out of order during its useful life.
Integrity problem also can cause the underproof fault of process, the poor output at semiconductor device manufacturing facility place and/or fault at the scene, and wherein any one fault all can cause the loss in products reclaiming and/or income.These problems even become when high voltage applications and more worsen.
Summary of the invention
According to embodiments of the invention, semiconductor device comprises the first metal wire being arranged in the substrate comprising circuit and the second metal wire arranged adjacent to the first metal wire.First metal wire and the second metal wire are the metal wires being configured to supply to circuit different voltage.3rd metal wire is arranged between the first metal wire and the second metal wire.3rd metal wire is not the part of any functional circuit in the substrate, and is not coupled to any potential nodes.
According to embodiments of the invention, the method for testing multiple semiconductor device be included in be arranged in substrate shielding conductor on apply to have the withstand voltage of crest voltage, substrate comprises the functional circuit of semiconductor device.Fixed voltage is applied to the first metal wire of the substrate be arranged in adjacent to shielding conductor.First metal wire is coupled to functional circuit and is configured to be coupled to high voltage node during operation.Crest voltage is larger than maximum fixed voltage.Shielding conductor makes the first metal wire be separated with adjacent second metal wire being configured to be coupled to during operation lower voltage node.The method also comprises the electric current measured in response to withstand voltage through shielding conductor, determines the electric current of the shielding conductor through semiconductor device, and determines to be identified as by semiconductor device by test based on this.
According to embodiments of the invention, the method for designing semiconductor device comprises the district be identified in the layout of semiconductor device, and this district comprises the first metal wire being configured to be coupled to high voltage node and the second metal wire being configured to be coupled to lower voltage node.The method also comprises the layout of amendment semiconductor to be included in the 3rd metal wire between the first metal wire and the second metal wire.3rd metal wire has external contact pads, but is not the part of any functional circuit of semiconductor device and is not coupled to any functional circuit of semiconductor device.
Foregoing teachings outlines the feature of embodiments of the invention quite widely, so that ensuing detailed description of the present invention can be better understood.Will be described below the additional feature and advantage of embodiments of the invention, it forms the theme of claim of the present invention.Those of skill in the art it should be understood that disclosed concept and specific embodiment can easily be utilized as and perform other structure of identical object of the present invention or the basis of process for revising or being designed for.Those of skill in the art also it should be understood that such equivalent structure does not depart from the spirit and scope of the present invention as set forth in the following claims.
Accompanying drawing explanation
In order to understand the present invention and advantage thereof more completely, with reference now to the description below understanding by reference to the accompanying drawings, wherein:
The defect concentration that the Fig. 1 comprising Figure 1A and 1B illustrates different metal wire structure is associated fault;
The Fig. 2 comprising Fig. 2 A with 2B illustrates the metal wire be separated by shielding conductor according to embodiments of the invention, and wherein Fig. 2 A illustrates arranged perpendicular, and Fig. 2 B illustrates horizontal arrangement;
Fig. 3 illustrates the flow chart of the diagnostic method that realization describes in various embodiments of the present invention;
Fig. 4 illustrates the blind zone formed around power line according to embodiments of the invention;
The Fig. 5 comprising Fig. 5 A and 5B illustrates the blind zone formed around power line according to embodiments of the invention, wherein Fig. 5 A diagrammatic cross-section view, and Fig. 5 B diagrammatic top view;
Comprise Fig. 6 diagram of Fig. 6 A and 6B according to embodiments of the invention semiconductor test;
Fig. 7 illustrates the embodiment of the isolated area of test around high-voltage power line;
Comprise Fig. 8 diagram of Fig. 8 A-8C according to an embodiment of the invention adjacent to the top view of the high voltage transmission line of low voltage lines extension;
Fig. 9 illustrates the alternate configurations of shielding conductor according to an embodiment of the invention;
Comprise Figure 10 diagram of Figure 10 A-10F according to the semiconductor device of embodiments of the invention during the various stages of process;
Comprise Figure 11 diagram of Figure 11 A-11F according to the semiconductor device of embodiments of the invention during the various stages of process, wherein Figure 11 A, 11C-11F diagrammatic cross-section view, and Figure 11 B diagrammatic top view;
Comprise Figure 12 diagram of Figure 12 A-12F according to the semiconductor device of embodiments of the invention during the various stages of wafer-class encapsulation; And
Figure 13 diagram comprising Figure 13 A-13C comprises wafer-level process to be formed in another embodiment of the process of the shielding conductor between adjacent redistribution lines.
Respective material in different figures and symbol are often referred to corresponding part, unless otherwise directed.Figure is drawn into the related fields of clearly illustrated embodiment and might not draws in proportion.
Embodiment
Discuss manufacture and the use of various embodiment below in detail.But it should be understood that a lot of applicable creative concept that the invention provides and be embodied in various specific context.The specific embodiment discussed only illustrates and manufactures and use ad hoc fashion of the present invention, and does not limit the scope of the invention.
The present invention will be described about various embodiment in a specific context, is namely implemented in power device applications.Embodiments of the invention also can other semiconductor application such as such as storage component part, logical device, analogue device, radio frequency (RF) device, data device and utilize metal wire other application in realize.
Intermetallic distance is key factor, particularly when metal wire carries high voltage.Such as, when carrying high-tension metal wire and abutting against another metal wire at low voltage place, large potential difference is being separated the dielectric layer two ends development of high-voltage metal line and low-voltage metal wire.Potential difference can cause fault subsequently, and it can exist before product operation, or can develop during product useful life.But current method of testing can not identify these defects.Such as, conventional method such as by apply between high-voltage metal line and low-voltage metal wire voltage detect leakage current may not out of order part subsequently and by fail-safe part between find any difference.In various embodiments, the present invention's instruction overcomes the method for these problems, design and device.
Use Fig. 2 is described constructive embodiment of the present invention.By use Fig. 4,5,8,9,11F, 12F and 13C describe other constructive embodiment.By the method using Fig. 6 to describe test component.Fig. 3,10,11,12 and 13 will be used to describe design and/or manufacture method for semiconductor.
The defect concentration that the Fig. 1 comprising Figure 1A and 1B illustrates different metal wire structure is associated fault.
Various semiconductor process techniques such as becomes stricter day by day for the production of the failure rate target of those technology of automobile component.Such as, to the failure rate of a lot of application expection lower than 1ppm.On the other hand, in a lot of technology, use higher voltage, it increases the tendency of fault especially.Can comprise capacitor back-end process (BEOL) metal wire and also have FEOL (FEOL) capacitor be difficult to only meet these strict reliability requirements by technological improvement because reliability by may can't help manufacturers of semiconductor devices control external defect concentration level determine.Such as, grit can become on the metal wire that deposits to and make their short circuits.Alternatively, such as change in process can cause being formed the difference isolation with metal wire, the dielectric bag (pocket) narrowing/broaden, thus deposits the particle compared with low quality dielectric path be introduced between adjacent wires.For FEOL device and FEOL capacitor, electrode or dielectric poor quality may be the reasons of external defect.
With reference to Figure 1A, the general breakdown characteristics of dielectric isolation is shown.First curve 11 represents the first dielectric thickness/interval of metal wire, and the second curve 12 represents the second dielectric thickness/interval of metal wire.In the example shown, the first dielectric thickness/interval of the first curve 11 is less than the second dielectric thickness/interval of the second curve 12.In other words, use thicker dielectric isolation that curve 11 is moved to curve 12.This however with the lower ratio capacitance of FEOL and BEOL capacitor for cost.The more shallow branch (lower slope) of curve punctures relevant with external, and the comparatively steep part of curve is due to indigenous fault.External puncturing can be the result of change, dielectric quality etc. in the introducing of defective workmanship such as particle, metal line-width.It is be restricted to the dielectric physical restriction making a part for insulator become the minimum voltage of conduction that inherence punctures.Therefore, the puncturing in isolation occurred at much lower voltage place punctures due to external instead of interiorly puncturing.Therefore, much lower voltage place occur puncturing in isolation be due to external puncture instead of dielectric in puncturing.Therefore, for given defect concentration, the first curve 11 is being out of order at lower voltage place than the second curve 12, which illustrates less clearance distance and has higher probability of malfunction.Up to the present not used for the available solution there is strict (PPM) ppm target being such as less than the technology of a few ppm.In order to content with funtion safety requirements (short circuit such as wherein between different voltage domain is crucial), usable floor area consumption is measured.
Change sentence to have a talk about, as shown in Figure 1B, vertically or laterally increase dielectric thickness (as mentioned above, curve 13 has maximal clearance, and curve 11 has minimum clearance) and improve reliability (in the x-axis of Figure 1B improvement) from left to right.But existence improves with this area be associated and punishes, which increases manufacturing cost.For FEOL device, this is normally the most impossible, because electrical quantity also changes along with the dielectric thickness increased.Therefore, the raising in reliability and exist compromise between the area consumed.Particularly, given process can be restricted to and move along the line shown in Figure 1B.Breaking this compromise (shown in small arrow) will be favourable.Embodiments of the invention by identifying that susceptible chip is broken this and traded off in a cost efficient manner, and do not consume and above-mentioned compromise as many area.
To improve the another way of reliability be the distance that is increased between the metal wire with large voltage difference and use pre-burning to filter out the device with external defect.But pre-burning is at a higher temperature by the process of use one section of long time slightly higher than the voltage of operating voltage.Although applied voltage is higher than operating voltage, be limited to avoid puncturing completely of other simultaneously tested device.But these measure the area or testing time that cost a lot of money.In addition, not all line is all come-at-able by burn-in process.
The Fig. 2 comprising Fig. 2 A with 2B illustrates the metal wire be separated by shielding conductor according to embodiments of the invention, and wherein Fig. 2 A illustrates arranged perpendicular, and Fig. 2 B illustrates horizontal arrangement.
In various embodiments of the present invention, the quick and effective method in the weak district detecting metal wire is presented.Additional shielding conductor is more easily being subject to being formed around the metal wire in the district of short circuit.Shielding conductor is not coupled to other circuit any in substrate.Therefore, shielding conductor does not draw the leakage current of any type.Such as, if shielding conductor is even connected to functional circuit in disconnection (OFF) pattern, leakage current is due to diode, transistor and can cause the intrinsic noise level of micromicroampere.On the contrary, shielding conductor may can detect and be low to moderate several leakage current receiving ampere.Therefore, the electric current very in a small amount through shielding conductor can be detected.Such leakage current instruction is easily subject to the district of fault.Detect more than 1000X – 10 6it is direct result shielding conductor not being coupled to other circuit any that this of X is increased sharply.
With reference to figure 2A, shielding conductor 20 is arranged between the first metal wire 10 and the second metal wire 30.First metal wire 10 and the second metal wire 30 have them and are parallel to the part extending each other and also have large voltage difference during operation between which.Such as, the first metal wire 10 can be configured to carry high voltage, and the second metal wire 30 can be configured to carry low-voltage.
As shown in Figure 2 A, shielding conductor 20 is arranged between the first metal wire 10 and the second metal wire 30.Fig. 2 A is also shown in intermetallic distance V13 when not having shielding conductor between two metal wires.Relative to the design having now shielding conductor, the intermetallic distance V13 ' between the first metal wire 10 and the second metal wire 30 can increase due to the introducing of shielding conductor 20.But with the design comparison not having shielding conductor, the increase of intermetallic distance V13 ' may be little.
Shielding conductor 20 is free of attachment to other circuit any in substrate.Therefore, the parasitic circuit be not associated with shielding conductor 20 or leakage circuit.Such as, the metal wire being connected to substrate can have the leakage current that is associated, even if all devices are not active.Advantageously, the leakage current that shielding conductor 20 non-conducting is such, because it is not coupled to any circuit on chip.More properly, shielding conductor 20 is only coupled to external pads and is applied to shielding conductor 20 for by voltage.
The embodiment of Fig. 2 B illustrated alternative, wherein the first metal wire 10 is separated with the second metal wire 30 by shielding conductor 20.In this case, the lateral separation L13 between the first metal wire 10 and the second metal wire 30 is controlled, and shielding conductor 20 can be inserted between these row.But the introducing of shielding conductor 20 again can not obvious increase intermetallic distance.
Fig. 3 illustrates the flow chart of the diagnostic method that realization describes in various embodiments of the present invention.
With reference to figure 3, in first step 105, provide chip layout.Chip layout can comprise the layout of metal layer and the information that also can comprise about carrying high-tension line.Then, layout is analyzed to identify critical zone, wherein carries high-tension metal wire adjacent to the metal wire (second step 110) carrying low-voltage during operation.Such as, the intermetallic distance limited in advance can be used for the such metal wire be identified in the district of layout, and wherein voltage difference exceedes the restriction embodiment limited in advance.In another embodiment, carry out by potential difference the intermetallic distance that standardization limits in advance.Such as, in the circuit with the pressure-wire carrying different voltage, distance can be standardized (such as by making voltage difference divided by intermetallic distance), and, to determine the district of layout, the electric field wherein crossing over dielectric substance exceedes certain critical number.In addition, in various embodiments, can generate more complicated scheme or rule such as to determine the district of chip, wherein metal wire is not and then under same metal level or laterally in same metal level.
Then, as shown in Figure 3, in third step 115, blind zone is introduced into.Shielding conductor not n-back test during the operation of chip.More properly, shielding conductor is test structure with the defect introduced during being identified in process.
With reference to the 4th step 120, generate the technological process manufacturing and there is the semiconductor chip of blind zone, and semiconductor chip therefore manufactured (the 5th step 135).
Fig. 4 illustrates the blind zone formed around power line according to embodiments of the invention.
With reference to figure 4, shielding conductor 20 can be formed in more than one metal layer in various embodiments.Such as, shielding conductor 20 can be formed between power line (such as the first metal wire 10) and other metal wires 50 all.As shown in Figure 4, shielding conductor 20 is laterally with vertically around the first metal wire 10.The metal wire be arranged under shielding conductor 20 can be coupled to and laterally be arranged in other metal wire around the first metal wire 10 by through hole 40.Therefore in this embodiment, the protection more completely of the first metal wire 10 is possible.
The Fig. 5 comprising Fig. 5 A and 5B illustrates the blind zone formed around power line according to embodiments of the invention, Fig. 5 A diagrammatic cross-section view, and Fig. 5 B diagrammatic top view.
In another embodiment, shielding conductor 20 can be formed at first metal wire 10(Fig. 5 B) under pad to make the first metal wire 10 be separated with other metal wires 50 all.
The Fig. 6 comprising Fig. 6 A and 6B illustrates semiconductor device according to an embodiment of the invention.
With reference to figure 6A, in various embodiments can during manufacture or afterwards test component.Test can be performed in one embodiment after manufacture and cutting.In another embodiment, test can be performed before being cut.In another embodiment, such as test can be performed after there is the completing of such as special metal layer of metal wire to be tested during manufacture.
As shown in Figure 6A, shielding conductor 20 can be coupled to the voltage node being configured to apply potential pulse Vs.Galvanometer can be used measure the electric current flowing through shielding conductor 20.In various embodiments, high voltage can be applied through shielding conductor 20.In one embodiment, high voltage can be used as short pulse and is applied in.Such as in various embodiments, high voltage can be applied in and be less than hundreds of ns, and is less than 10 ns in one embodiment.In various embodiments, high voltage can be applied in one period between about 1 ns to about 100 ns.In various embodiments, high voltage can between about 10 V to about 100 V.In various embodiments, the crest voltage be applied to during stress on shielding conductor 20 is that about 1.2:1 is to about 10:1 with the ratio of the maximum peak voltage being applied to functional circuit during operation.In various embodiments, the ratio of the maximum voltage applied on other metal wire 50 during the maximum voltage and the operation at chip that apply on the first metal wire 10 during the operation of chip is about 5:1 to 100:1.
Because shielding conductor 20 is not coupled to other circuit any in device, the electric current instruction flowing through shielding conductor 20 punctures with the external of the isolation 25 between the first metal wire 10 and shielding conductor 20 leakage current be associated.Such as, when without any leakage or defect, the electric current through shielding conductor 20 measured by galvanometer can be less than 1 nA.Therefore, the little increase even in leakage current is also measurable.Such as, the weak device of identifiable design, itself otherwise will be tested by all functions.On the contrary, if shielding conductor 20 is coupled to any circuit, then the leakage current of certain amount is inevitable, which suppress galvanometer and senses the ability puncturing the leakage current be associated with the isolation 25 between the first metal wire 10 and shielding conductor 20.
In addition, because the first metal wire 10 and substrate can be grounded.Therefore, the first metal wire 10 and other circuit any in the substrate are not subject to the high voltage that applied by shielding conductor 20.Therefore, the danger of any parts of circuit is not damaged due to high voltage.
Fig. 6 B illustrates the optional embodiment measured around the globality of the isolated area of high-voltage power line.
In this embodiment, high voltage transmission line and low voltage lines are all coupled to comparatively electronegative potential, such as earth potential.Such as, as shown in Figure 6B, the first metal wire 10 and all metal wires 50 are coupling to ground.Therefore, if high voltage pulse is applied on shielding conductor 20, then the isolation 25 between the first metal wire 10 and shielding conductor 20 and the isolation 26 between shielding conductor 20 and all metal wires 50 tested.Problem in any leakage current instruction isolation that test period is measured.
In various embodiments, test process can be included in the operation described in Fig. 6 A and 6B.Therefore, location of fault also can be identified, and makes process reform may be utilized the process yields improved subsequently.
Advantageously, use embodiments of the invention, the shielding conductor of all critical zones can be shorted together, makes the large regions of semiconductor chip (or even all chips) can be simultaneously tested concurrently.
In an alternate embodiment of the invention, above-mentioned test can be used as diagnostic test and is such as performed upon power-up or after the time interval when device starts.Outside or inside diagnostic program such as built-in self-test can initiate this test.Leakage at shielding conductor place can be then used in the globality of the isolated area of monitoring chip.Increase in the leakage current at shielding conductor place can start (initial) chip to take protection action, and such as before fault occurs, chip is converted to the transition in safe condition.
Fig. 7 illustrates the embodiment of the isolated area of test around high-voltage power line.
In this embodiment, high voltage pulse is applied on the first metal wire 10, and shielding conductor 20 ground connection.The electric current flowing through shielding conductor 20 is measured.
Comprise Fig. 8 diagram of Fig. 8 A-8C according to an embodiment of the invention adjacent to the top view of the high voltage transmission line of low voltage lines extension.
Fig. 8 A illustrates normal arrangement, and wherein high voltage transmission line such as carries high-tension first metal wire 10 is adjacent to another metal wire, such as, carry the second metal wire 30 of low voltage.According to embodiments of the invention, identify the external critical zone 155 punctured of the isolation be easily subject between the first metal wire and the second metal wire.As shown, the lateral separation L13 between the first metal wire 10 and the second metal wire 30 is less than the critical distance (such as, as described previously) limited in advance.
Not shift metal wire to be increased in the distance L13 between the first metal wire 10 and the second metal wire 30, as shown in Figure 8 B, between the first metal wire 10 and the second metal wire 30, introduce shielding conductor 20.Shielding conductor 20 is for use in testing for the globality of the isolation between the first metal wire 10 and the second metal wire 30.But the distance L13 ' between the first metal wire 10 in the fig. 8b and the second metal wire 30 is not obvious is greater than distance L13 between the first metal wire 10 in fig. 8 a and the second metal wire 30.Such as, in one or more embodiments, the ratio of the distance L13 between the first metal wire 10 in fig. 8 a and the second metal wire 30 and the distance L13 ' between the first metal wire 10 in the fig. 8b and the second metal wire 30 can be about 1:1.1 to about 1:1.8, and is less than 1:2 in various embodiments.
Fig. 8 C illustrates the difference configuration of shielding conductor according to an alternative embodiment of the invention.
As shown in Figure 8 C, the shape of shielding conductor 20 can be modified the globality of the isolated area of testing in more than one directions.In Fig. 8 C, shielding conductor 20 around high-voltage metal line, that is, is formed in the concave around the first metal wire 10.
Fig. 9 illustrates the alternate configurations of shielding conductor according to an embodiment of the invention.
In this embodiment, shielding conductor 20 around the first metal wire 10, make they vertically on both direction and under and laterally formed in the two directions.Fig. 9 illustrates semiconductor device 200(and illustrates not in scale) viewgraph of cross-section, it can comprise the active circuit being arranged in its inside.Active circuit can comprise active device region and comprise necessary transistor, resistor, capacitor or other parts for the formation of integrated circuit.Such as, the active region comprising transistor (such as CMOS transistor) by isolated area such as shallow trench isolation from separated from one another.Then, metallize and formed to make active device electrical contact and interconnection on active device region.Metallization forms complete functional integrated circuit together with active device region.In other words, the Electricity Functional of semiconductor device 200 can be performed by the active circuit interconnected.In logical device, metallization can comprise the plurality of layers of copper or other metal alternatively, such as nine or more.In storage component part such as DRAM, the quantity of metal level can be less, and can be aluminium.Such as in fig .9, M is comprised 1, M 2, M 3, M 4, M 5and M 6six metal layer vertical ground stacking, and by contact and via layer V 1, V 2, V 3, V 4, V 5with, V 6connect.In other embodiments, metal and the via layer of more or less quantity can be used.
Comprise the first via layer V of multiple through holes of different designs 1be arranged on the substrate 100 in the first insulating barrier 121, the first insulating barrier 121 is arranged on substrate 100.In various embodiments, substrate 100 can comprise Semiconductor substrate and/or the dielectric layer on Semiconductor substrate.Similarly, the second insulating barrier 122 is included in the first metal layer M 1multiple metal wires of the different designs at place.Similarly, the subsequent layer of insulating barrier comprises corresponding metal wire or through hole.Such as, 3rd insulating barrier 123 comprises the second via layer V2,4th insulating barrier 124 comprises the second metal level M2, pentasyllabic quatrain edge layer 125 comprises third through-hole layer V3,6th insulating barrier 126 comprises the 3rd metal level M3, four-line poem with seven characters to a line edge layer 127 comprises fourth hole layer V4,8th insulating barrier 128 comprises the 4th metal level M4,9th insulating barrier 129 comprises fifth hole layer V5, tenth insulating barrier 130 comprises the 5th metal level M5,11 insulating barrier 131 comprises the 6th via layer V6, and the 12 insulating barrier 132 comprises the 6th metal level M6.
Pitch (distance between adjacent through-holes or between adjacent wires) at each metal level place is by the Separation control of the minimum permission to specific technology limiting.
In this embodiment, shielding conductor 20 is formed between the Formation period of the metal wire of back-end process process.Formed around first metal wire 10 carrying high voltage transmission line of shielding conductor 20 in district (wherein other metal wire 50 is adjacent).Such as, the district 155 of semiconductor device is district, and wherein high-voltage metal line parallel extends in other low voltage line.
Therefore, what this district can be identified as easily being isolated externally punctures.As shown in Figure 8 A, the first metal wire 10 can by shielding conductor 20 around.In addition, as described in existing embodiment, shielding conductor 20 can not be coupled (electrically, inductively, capacitively and ohmically) to other circuit any of semiconductor device.In other words, other circuit electric isolution any in shielding conductor 20 and the first metal wire 10 and semiconductor device.Particularly, the device that wherein shielding conductor 20 not exclusively isolates (due to puncturing of isolation) makes test or screening process failure, and is not the part of final work product.In work product, shielding conductor 20 is isolated with the first metal wire 10 and other metal wires 50 all.
Comprise Figure 10 diagram of Figure 10 A-10F according to the semiconductor device of embodiments of the invention during the various stages of process.
Perform the first FEOL process.FEOL process is included in Semiconductor substrate 100 and is formed with source region, diffusion region and other district.Subsequently, back-end process process is performed.Back-end process process comprises metallization processes to make various parts in Semiconductor substrate 100 or device interconnection.
In various embodiments, the process of deducting or adding procedure such as mosaic process can be used to form metal wire.Such as, use deducts process and carrys out deposition of aluminum, and uses adding procedure to carry out deposited copper.Deducting in process, plated metal cover layer, then it use photoetching process and etch process to be constructed.On the contrary, in adding procedure, insulating barrier is patterned to form opening, and then it be filled with metal.
Illustratively, in various embodiments of the present invention, single mosaic process or dual-damascene process can be used to form metal level and via layer.In single mosaic process, single-layer insulation material is patterned the pattern of conductive features such as conductor wire, conductive through hole.On the contrary, in a dual damascene process, through hole and metal wire are patterned for conductive features and are filled with electric conducting material in single filling steps.
In Figure 10 A-10C, diagram uses the example of this process of single mosaic process, at the first via layer V 1in the formation of through hole.With reference to figure 10A, the first insulating barrier 121 is deposited on etch stop liner plate (not shown) such as silicon nitride.Photoetching process is used to carry out patterning first insulating barrier 121.First insulating barrier 121 of Figure 10 A pictorial image patterning, and Figure 10 B is shown in this layer after through hole formation (filling through hole and complanation).By depositing outside first conduction liner plate and being then formed in the first via layer V with all the other openings of filled with conductive material 1in through hole.Conduction liner plate can comprise such as CVD titanium nitride and mix silicon tungsten, although in other embodiments, conduction liner plate can comprise other material, such as tantalum, tantalum nitride, titanium, tungsten nitride, ruthenium or its any combination.Electric conducting material comprises tungsten, although in other embodiments, electric conducting material can comprise other suitable material, such as copper, aluminium, tungsten, tantalum, titanium nitride and ruthenium.
The first metal layer M 1at the first via layer V 1on formed.Second insulating barrier 122 is deposited on the first insulating barrier 121.Etch stop liner plate can be formed between the first and second insulating barriers 121 and 122.Figure 10 C illustrates the formation of metal one pattern, and Figure 10 D is shown in the structure after the filling of metal and complanation such as CMP subsequently, thus is formed in the metal wire in the first metal layer M1.Additional barrier layer (spreading to prevent metal) and the inculating crystal layer for electroplating can deposit before the filling of metal.The example on barrier layer can be similar to the conduction liner plate of through hole.After formation barrier layer, physical vapour deposition (PVD) can be used to deposit inculating crystal layer.Then, electroplating technology can be used for filling opening to form metal wire.Metal level subsequently and via layer are formed in a similar fashion.Metal level M 2, M 3with via layer V 2, V 3illustrate in Figure 10 E, Figure 10 E also illustrates at the 3rd metal level M 3in shielding conductor 20.General manufacturing process can use list or dual-damascene process or its to combine when building multiple metal level and via layer.In certain embodiments, metal layer is as the 3rd metal level M 3major part can be used for shielding conductor.
Figure 10 F is shown in and forms additional shielding conductor 20 and be configured to carry high-tension metal wire, that is, the semiconductor device after the first metal wire 10.In addition, in certain embodiments, can such as in this case at the 5th metal level M before final manufacture 5formation after perform test process.Therefore, in certain embodiments, metal level subsequently can be used for lock shield line 20.Such as, the 11 insulating barrier the 131 and the 12 insulating barrier 132 covers shielding conductor 20, prevents shielding conductor 20 to be touched after manufacture process completes.
Comprise Figure 11 diagram of Figure 11 A-11F according to the semiconductor device of embodiments of the invention during the various stages of process, wherein Figure 11 A, 11C-11F diagrammatic cross-section view, and Figure 11 B diagrammatic top view.
In the embodiment described by Figure 10, shielding conductor is formed the part of conventional back-end-of-line process.Therefore, the district for shielding conductor can not be used for the component connection making semiconductor device.In this optional embodiment, after the completing of all metal wires, use conventional back-end-of-line process to form shielding conductor.Therefore, in this embodiment, short lap metal can be deposited between high voltage in the critical zone of chip and low voltage lines.
As illustrated in the top of Figure 11 B, district 155 is identified as needing additional test process.With reference to figure 11A and 11B, hard mask layer 220 to be deposited on semiconductor device and to use photoetching process and etch process to be patterned to form opening 225.The hard mask 220 of patterning exposes the passivation layer 210 be arranged on semiconductor device.Use the hard mask 220 of patterning, anisotropic etching process is performed the insulating barrier (Figure 11 C) etched below.
With reference to figure 11D, fill metal 230 and be deposited in opening 225.Fill metal 230 and can partially or completely fill opening 225.Such as, as shown in Figure 11 D, filling metal 230 may be crossed and be filled.Then, as depicted in fig. 1 ie, filling metal 230 is etched with and is removed any filling metal 230 from the top surface of passivation layer 210.Figure 11 F illustrates another embodiment, and it illustrates such as by using the interior etching of increase or being partially filled opening 225 by controlling sedimentation time.
Comprise Figure 12 diagram of Figure 12 A-12F according to the semiconductor device of embodiments of the invention during the various stages of wafer-class encapsulation.The enlarged cross-sectional view of Figure 12 diagram semiconductor packages during manufacture according to an embodiment of the invention, it illustrates front side metallization.
Embodiments of the invention also can be applicable to front side and rear side redistribution lines.Illustratively, Figure 12 discloses the application to wafer-level process of embodiments of the invention.
Figure 12 A diagram comprises the reconstruction wafer 300 of multiple semiconductor chips 320 with multiple contact pad 330.In multiple semiconductor chip 320 embedding sealing agent 310, sealant 310 surrounds multiple semiconductor chip 320 at least in part.Sealant 310 provides machinery and thermal stability during process subsequently.
With reference to figure 12B, passivation layer 350 can be formed and be patterned around front side metallization layer.In various embodiments, passivation layer 350 is insulating barriers.In one or more embodiments, passivation layer 350 can comprise oxide skin(coating) or oxide/nitride layer lamination.In other embodiments, passivation layer 350 can comprise silicon nitride, silicon oxynitride, FTEOS, SiCOH, polyimides, photoimide, BCB or other organic polymer or its combination.Optional insulating barrier can be formed on passivation layer 350.In one embodiment, optional insulating lining can comprise nitride layer.In various embodiments, optional insulating lining can comprise FTEOS, SiO 2, SiCOH or other low-k materials.
Use photoetching process, passivation layer 350 is patterned the multiple contact pads 330 opened on last metal level of multiple semiconductor chip 320.But opening 340 is also being identified as being formed in critical district's (adjacent to high voltage and low voltage lines).
Figure 12 C illustrates the zoomed-in view according to embodiments of the invention semiconductor packages during manufacture after the formation of front side redistributing layer.
With reference to figure 12C, conduction liner plate 360 is deposited.Conduction liner plate 360 can comprise adhesive layer, barrier layer and/or inculating crystal layer.In various embodiments, use depositing operation come depositing electrically conductive liner plate 360 with formed comprise Ti, Ta, Ru, W, its combination or its nitride, silicide, carbide conformal layer.The example of such combination comprises TiN, TaN and WN and TiW.In various embodiments, chemical vapour deposition (CVD), plasma gas phase deposition or ald is used to carry out depositing electrically conductive liner plate 360.In various embodiments, the liner plate 360 that conducts electricity comprises the thickness of about 20 nm to about 200 nm.Conduction liner plate 360 is diffusion barrier metals, and prevents copper from last metal wire of front side metal layer to outdiffusion and prevent from mixing with other metal level.
Conduction liner plate 360 can comprise the conductive seed layer be deposited on barrier layer.Conductive seed layer covers electrically conductive barrier.In various embodiments, depositing operation is used to carry out depositing electrically conductive inculating crystal layer to form conformal layer.In various embodiments, chemical vapour deposition (CVD), plasma gas phase deposition or ald is used to carry out depositing electrically conductive inculating crystal layer.In various embodiments, conductive seed layer comprises the thickness of about 20 nm to about 200 nm.Conductive seed layer is provided for the inculating crystal layer grown during electroplating technology subsequently.In various embodiments, conductive seed layer can comprise copper or other metal as Al, W, Ag, Au, Ni or Pd.
As also illustrated in fig. 12 c, thick photoresist oxidant layer 370 is deposited on conduction liner plate 360.In various embodiments, photoresist oxidant layer 370 is several micron thickness, and changes to about 10 μm from about 1 μm in one embodiment.After deposition, photoresist oxidant layer 370 fills the opening formed in passivation layer 350 in the past.Photoresist oxidant layer 370 is exposed and develops.The photoresist oxidant layer 370 of patterning comprises the pattern of redistribution metal wire and contact pad.
Then with reference to figure 12D, the filling metal on the conduction liner plate 360 exposed between the photoresist oxidant layer 370 of patterning by plating forms the first redistribution metal wire 410, second redistribution metal wire 430, shielding redistribution lines 420 and contact pad 405.In various embodiments, fill metal and comprise copper, although in certain embodiments, other suitable conductor is used.In one embodiment, the liner plate 360 that conducts electricity can comprise the material identical with the material of metal wire subsequently to make it possible to electroplate.In various embodiments, the first redistribution metal wire 410, second redistribution lines 430, shielding redistribution lines 420 and contact pad 405 can comprise multilayer, such as Cu/Ni, Cu/Ni/Pd/Au, Cu/NiMoP/Pd/Au or Cu/Sn in one embodiment.
Then with reference to figure 12E, the photoresist oxidant layer 370 of patterning is peelled off to expose conduction liner plate 360.Use such as wet etching chemical process to etch away the conduction liner plate 360 of exposure.Structure is at this stage illustrated in Figure 12 F.Therefore, can use in the mode identical with the shielding conductor described in various embodiments and shield redistribution lines 420.
Figure 13 diagram comprising Figure 13 A-13C comprises another embodiment of the process of wafer-level process, to be formed in the shielding conductor between adjacent redistribution lines.
In this embodiment, compare with embodiment above, shielding conductor is not parallel to contact through hole and extends.More properly, shielding conductor is only formed the redistribution lines on passivation layer 350.Therefore, Figure 13 A is shown in the device after the formation of opening 340.Figure 13 B is shown in the device after the photoresist oxidant layer 370 of patterning and the formation of shielding redistribution lines 420, first redistribution metal wire 410, second redistribution metal wire 430.Figure 13 C is shown in and removes, that is, the device after the photoresist oxidant layer 370 of etch patterning.
As described in various embodiments, the material comprising metal can be such as simple metal, metal alloy, metallic compound, intermetallic compound etc., that is, comprise any material of metallic atom.Such as, copper can be fine copper or any material comprising copper, such as but not limited to copper alloy, copper compound, copper intermetallic compound, comprises the insulator of copper and comprises the semiconductor of copper.
Although describe the present invention with reference to exemplary embodiment, this description is not intended to as being explained in limiting sense.When describing with reference to this, the various amendment of exemplary embodiment and combination and other embodiments of the invention will be obvious for those of skill in the art.Illustratively, the embodiment described in Fig. 1-12 can combination with one another in an alternate embodiment of the invention.Therefore be intended that claims and comprise any such amendment or embodiment.
Although described the present invention and advantage thereof in detail, should be understood that and can make a variety of changes herein, substitute and change, and do not departed from the spirit and scope of the present invention be defined by the following claims.Such as, those of skill in the art will readily appreciate that, a lot of feature described herein, function, process and material can change, and keep within the scope of the invention simultaneously.
And, the scope of the application be not intended to for be restricted to describe in the description process, machine, manufacture, material composition, device, method and step specific embodiment.Because those skilled in the art open easily will to recognize from of the present invention, can utilize according to the present invention the current existence that performs the function identical in fact with corresponding embodiment described herein or realize result identical in fact or later the process developed, machine, manufacture, material to be formed, device, method or step.Therefore, claims are intended to such process, machine, manufacture, material composition, device, method or step to be included within the scope of it.

Claims (22)

1. a semiconductor device, comprising:
First metal wire, it is arranged in the substrate comprising circuit;
Second metal wire, it is arranged adjacent to described first metal wire, and wherein said first metal wire and described second metal wire are the metal wires being configured to supply to described circuit different voltage; And
3rd metal wire, it is arranged between described first metal wire and described second metal wire, and described 3rd metal wire is not the part of any functional circuit in described substrate, and is not coupled to any potential nodes.
2. device as claimed in claim 1, wherein said 3rd metal wire comprises the material different from described first metal wire.
3. device as claimed in claim 1, wherein said first metal wire comprises copper.
4. device as claimed in claim 1, wherein said 3rd metal wire comprises metal nitride.
5. device as claimed in claim 1, wherein said first metal wire is configured to during operation to the described circuit supply high voltage in described substrate, and wherein said second metal wire is configured to during operation to the described circuit supply low-voltage in described substrate.
6. device as claimed in claim 5, wherein said high voltage is at least 10V.
7. device as claimed in claim 6, wherein said low-voltage is different from ground voltage.
8. device as claimed in claim 7, wherein said low-voltage is between 1V and 5V.
9. device as claimed in claim 5, wherein said 3rd metal wire is configured to isolate with all built-in potentials, and any pad dielectric layer being wherein coupled to described 3rd metal wire covers to isolate described 3rd metal wire and bulk potential.
10. device as claimed in claim 5, wherein said 3rd metal wire is configured to isolate with all built-in potentials, and wherein said 3rd metal wire is coupled to the pad of exposure.
11. devices as claimed in claim 2, wherein said first metal wire, described second metal wire and described 3rd metal wire are arranged in same metal level.
12. devices as claimed in claim 2, wherein said first metal wire, described second metal wire and described 3rd metal wire are arranged in different metal levels.
The method of 13. 1 kinds of multiple semiconductor device of test, described method comprises:
The shielding conductor being arranged in substrate applies the withstand voltage with crest voltage, and described substrate comprises the functional circuit of semiconductor device;
Fixed voltage is applied to the first metal wire of the described substrate be arranged in adjacent to described shielding conductor, described first metal wire is coupled to described functional circuit and is configured to be coupled to high voltage node during operation, described crest voltage is larger than maximum fixed voltage, and described shielding conductor makes described first metal wire be separated with the second adjacent metal wire being configured to be coupled to during operation lower voltage node;
The electric current measured through described shielding conductor in response to described withstand voltage;
Determine the described electric current of the described shielding conductor through described semiconductor device; And
Determine described semiconductor device to be identified as by test based on described.
14. methods as claimed in claim 13, wherein said crest voltage is at least 10V, and wherein said fixed voltage is earth potential.
15. method as claimed in claim 13, the absolute value of the value of wherein said crest voltage is 1.1:1 to 10:1 with the ratio of the maximum voltage at described high voltage node place being configured to apply during operation.
16. methods as claimed in claim 15, the maximum voltage at described high voltage node place being wherein configured to apply during operation is about 5:1 to 100:1 with the ratio of the voltage at described lower voltage node place being configured to apply during operation.
17. methods as claimed in claim 13, also comprise and described fixed voltage are applied to described second metal wire.
The method of 18. 1 kinds of designing semiconductor devices, described method comprises:
Be identified in the district in the layout of described semiconductor device, described district comprises the first metal wire being configured to be coupled to high voltage node and the second metal wire being configured to be coupled to lower voltage node; And
Revise the layout of described semiconductor to be included in the 3rd metal wire between described first metal wire and described second metal wire, described 3rd metal wire has external contact pads, but is not the part of any functional circuit of described semiconductor device and is not coupled to any functional circuit of described semiconductor device.
19. methods as claimed in claim 18, the current potential being in which during operation applied to described high voltage node is 5:1 to 100:1 with the ratio of the current potential being applied to described lower voltage node during operation.
20. methods as claimed in claim 18, distance wherein between described first metal wire and described second metal wire is the minimum metal spacing of technology, and the distance wherein between described first metal wire and described 3rd metal wire is less than described minimum metal spacing.
21. methods as claimed in claim 18, wherein said first metal wire, described second metal wire and described 3rd metal wire are in different mask layers.
22. methods as claimed in claim 18, wherein said first metal wire, described second metal wire and described 3rd metal wire are in same mask layer.
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