CN104716103B - 具有间隙的底部填充图案 - Google Patents
具有间隙的底部填充图案 Download PDFInfo
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- CN104716103B CN104716103B CN201410058251.5A CN201410058251A CN104716103B CN 104716103 B CN104716103 B CN 104716103B CN 201410058251 A CN201410058251 A CN 201410058251A CN 104716103 B CN104716103 B CN 104716103B
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- packaging part
- underfill
- substrate
- semiconductor structure
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- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 13
- 239000000565 sealant Substances 0.000 claims description 13
- 238000007789 sealing Methods 0.000 claims description 8
- 238000012856 packing Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000001427 coherent effect Effects 0.000 description 3
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
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Classifications
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Abstract
本发明的实施例是一种结构,该结构包括封装件、衬底和将封装件机械连接并电连接至衬底的外部电连接件。封装件包含管芯。外部电连接件位于封装件和衬底之间。底部填充材料围绕封装件的***区域并且位于***区域和衬底之间。间隙位于封装件的中心区域和衬底之间,并且间隙不包含底部填充材料。底部填充材料可以密封间隙。间隙可以是气隙。在一些实施例中,底部填充材料可以填充封装件与衬底之间的大于或等于10%且不超过70%的体积。本发明还提供了涉及具有间隙的底部填充图案。
Description
技术领域
本发明总体涉及半导体工艺,具体的,涉及具有间隙的底部填充图案。
背景技术
半导体器件用于各种电子应用中,诸如个人电脑、手机、数码相机和其他电子设备。通常,通过在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导电层的材料,然后使用光刻图案化各个材料层以在其上形成电路部件和元件,从而制造半导体器件。通常,在单个半导体晶圆上制造数十或数百个集成电路。通过沿划线锯切集成电路来分割单个管芯。然后,例如以多芯片模块或以其他类型的封装来单独封装单个管芯。
半导体工业已经开发了许多可以封装管芯的方式。近年来,经常使用焊球或凸块将管芯和/或包含管芯的封装件附接至一些其他衬底、封装件、管芯或中介层。在许多这些应用中,底部填充材料用于填充管芯/封装件与其他部件之间的间隔。通过填充间隔,从而认为底部填充物通过为焊球或凸块提供额外的接合和支撑而为接合提供了更好的机械完整性。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种结构,包括:第一封装件,包含第一管芯;衬底;第一外部电连接件,将所述第一封装件机械连接和电连接至所述衬底,所述第一外部电连接件位于所述第一封装件和所述衬底之间;以及底部填充材料,环绕所述第一封装件的第一***区域并且位于所述第一***区域和所述衬底之间,所述第一封装件的第一中心区域和所述衬底之间存在第一间隙,并且所述第一间隙不包含所述底部填充材料。
在上述结构中,其中,所述第一间隙是气隙。
在上述结构中,其中,所述底部填充材料密封所述第一间隙。
在上述结构中,其中,所述底部填充材料至少环绕所述第一封装件的第一***区域上的外部的所述第一外部电连接件。
在上述结构中,其中,所述底部填充材料填充所述第一封装件和所述衬底之间的大于或等于10%且不超过70%的体积。
在上述结构中,其中,所述底部填充材料填充所述第一封装件和所述衬底之间的大于或等于20%且不超过50%的体积。
在上述结构中,其中,所述底部填充材料填充所述第一封装件和所述衬底之间的大于或等于20%且不超过40%的体积。
在上述结构中,其中,所述第一封装件包括:密封剂,至少横向地密封所述第一管芯;以及重分布结构,位于所述第一管芯的有源侧和所述密封剂上,所述重分布结构包括介电层和位于所述介电层上的导电图案,所述导电图案将所述第一管芯电连接至所述外部电连接件。
根据本发明的另一个方面,提供了一种结构,包括:封装件,包括:管芯,具有有源侧,密封剂,至少横向地密封所述管芯,和重分布结构,位于所述管芯的有源侧和所述密封剂上,衬底;外部电连接件,设置在所述封装件和所述衬底之间,所述外部电连接件将所述衬底机械连接并电连接至所述封装件,所述电连接件通过所述重分布结构电连接至所述管芯的有源侧;以及底部填充材料,环绕所述封装件的外边缘并且设置在所述封装件的外边缘和所述衬底之间,所述封装件和所述衬底之间存在气隙,所述底部填充材料围绕所述气隙。
根据上述结构中,其中,所述底部填充材料至少环绕外部的所述外部电连接件。
根据上述结构中,其中,所述底部填充材料连续地围绕所述气隙。
根据上述结构中,其中,所述底部填充材料填充所述封装件和所述衬底之间的间隔的10%至70%。
根据上述结构中,其中,所述底部填充材料填充所述封装件和所述衬底之间的间隔的20%至50%。
根据上述结构中,其中,所述底部填充材料填充所述封装件和所述衬底之间的间隔的20%至40%。
根据本发明的又一个方面,提供了一种方法,包括:使用外部电连接件将封装件附接至衬底,所述外部电连接件设置在所述封装件和所述衬底之间,所述封装件包括密封的管芯和将所述管芯电连接至所述外部电连接件的重分布结构;以及围绕所述封装件的***区域并在所述***区域和所述衬底之间的第一间隔中形成底部填充材料,位于所述封装件的中心区域和所述衬底之间的第二间隔不包含所述底部填充材料。
在上述方法中,其中,围绕所述***区域连续地形成所述底部填充材料。
在上述方法中,其中,所述第二间隔包含空气。
在上述方法中,其中,所述第二间隔是所述封装件和所述衬底之间体积的30%至90%。
在上述方法中,其中,形成所述底部填充材料包括:沿着所述封装件的横向边缘的部分分配所述底部填充材料,其中,不沿着所述横向边缘的全部分配所述底部填充材料;以及随后,沿着所述横向边缘的全部分配所述底部填充材料。
在上述方法中,其中,形成所述底部填充材料包括:围绕所述封装件的***分配所述底部填充材料,所述封装件在分配所述底部填充材料期间保持静止。
附图说明
为了更全面地理解本发明的实施例及其优势,现将结合附图所进行的以下描述作为参考,其中:
图1是根据实施例的位于衬底上的晶圆级封装件(WLP);
图2A、图2B和图3是根据实施例的二次分配工艺(two-pass dispense processes)的实例;以及
图4是根据实施例的位于封装件上的外部电连接件的图案的示例布局图。
具体实施方式
下面,详细论述了本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅示出了制造和使用本发明主题的具体方式,而不用于限制不同实施例的范围。
将结合具体环境(即,晶圆级封装结构)描述实施例。一些实施例可以应用于引线接合封装结构、叠层封装结构等。其他实施例也可以应用于其他可以使用底部填充材料的结构,诸如倒装芯片结构、衬底上中介层、堆叠式管芯等。在以下附图中,相似的参考标号表示相似的部件。虽然可以将方法实施例论述为按照特定顺序实施,但也可以以任何合逻辑的顺序来实施其他方法实施例。
图1根据实施例示出了晶圆级封装件(WLP)的实例。该结构包括例如扇出型WLP(FOWLP)封装件10,其包括通过密封剂14(诸如模塑料)密封的管芯12和重分布结构16。该结构进一步包括诸如印刷电路板(PCB)、有机衬底等的衬底20。诸如球栅阵列(BGA)球、凸块或其他电连接件的外部电连接件18将封装件10机械连接至衬底20,并且外部电连接件18结合重分布结构16进一步将管芯12电连接至衬底20。重分布结构16包括诸如凸块下金属(UBM)结构、后钝化互连(PPI)结构、迹线结构等的接合结构,该接合结构机械连接并电连接至相应的外部电连接件18。此外,衬底20具有机械连接并电连接相应的外部电连接件18的接合结构。
本领域的普通技术人员将容易理解封装件10是如何形成的,并且本文将提供关于封装件10形成的简单论述。最初,管芯12可以是部分晶圆,其经历半导体工艺以形成合适的器件。例如,管芯12可以包含逻辑电路、模拟电路、存储电路等或它们的组合。可以形成穿过管芯的有源侧上的顶部钝化层而暴露的诸如铝焊盘的电焊盘。可以使用电镀工艺在焊盘上形成诸如金属柱的柱形件。然后可以在晶圆上方(诸如在柱形件和顶部钝化层上方)对牺牲层进行涂布、层压等。随后可通过划切或锯切来从晶圆上分割管芯12,并且拾取和放置工具可以将管芯12放置在具有管芯附着膜的载体衬底上,该载体衬底可以是玻璃衬底、硅衬底、氧化铝衬底等,诸如任何合适的粘合剂、环氧树脂、紫外线(UV)胶(当其暴露于UV光线时,其将失去粘附性能)等的管芯附着膜将管芯12粘附至载体衬底。柱形件(例如管芯12的有源侧)可以与载体衬底相对设置。然后,密封工艺可以使用密封剂14密封管芯12。例如,使用模塑料进行模压成型、层压等可以密封管芯12。诸如使用化学机械抛光(CMP)的研磨工艺可以用于穿过密封剂14暴露牺牲层。然后,可以使用例如合适的蚀刻工艺去除牺牲层。
重分布结构16可以包括一个或多个介电层和一个或多个导电图案。去除牺牲层以后,通过诸如旋涂等可在管芯12上方形成诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等或它们的组合的第一介电层,并且平坦化该第一介电层以暴露柱形件。通过诸如旋涂等可在下面的介电层和/或密封剂上方形成诸如PBO、聚酰亚胺、BCB等或它们的组合的第二介电层和任意随后的介电层。使用例如光刻工艺、蚀刻、激光钻孔等可以形成穿过任意介电层到达下面的导电部件的开口。使用例如电镀工艺可以在介电层上和开口中形成诸如包括介电层中的重分布图案和顶部介电层上的接合焊盘的导电图案。
然后可以使用球落工艺(ball drop process)以在封装件10的接合焊盘上形成外部电连接件18。球落工艺可以使用焊料(诸如无铅焊料)以在封装件10上形成外部电连接件18。然后,诸如通过将管芯附着膜暴露于UV光或合适的溶剂以释放封装件10,从而可以从载体衬底去除封装件10。封装件10可放置在衬底20上,并且回流工艺可用于将外部电连接件18机械连接并电连接至衬底20。
底部填充材料22环绕封装件10的***并且位于封装件10和衬底20之间。在封装件10和衬底20之间的中心区域中形成诸如气隙的间隙24。底部填充材料22可以连续地环绕封装件10,这可导致间隙24密封在中心区域中。底部填充材料22沿着封装件10的***环绕并且密封各个外部电连接件18。
当结构保持不动或静止时,通过控制环绕封装件10分布的底部填充材料的量来形成底部填充材料22。可以使用二次分配工艺。例如,在第一次中,可沿着封装件10的每个横向边缘的小部分分配少量的底部填充材料22,并且在第二次中,可沿着封装件10的每个横向边缘的全部分配底部填充材料22。图2A、图2B和图3示出了二次分配工艺的实例。图2A、图2B和图3示出了位于封装件10上的外部电连接件18的布局图。在图2A中,第一次分配30沿着封装件10的每个边缘的相应的中心部分分配底部填充材料22。在图2B中,第一次分配32沿着封装件10的每个拐角部分分配底部封装材料22。在图3中,第二次分配34沿着每个横向边缘相应的全部分配底部填充材料22。图2A、图2B和图3是实例,并且可以使用不同的二次或多次工艺。另外,实施例预期通过单次工艺形成底部填充材料22。一些实施例预期在将封装件10附接至衬底20之前和/或之后(例如,预表面贴装技术(SMT)和/或后SMT)应用底部填充材料22。
再次参考图1,底部填充材料22从封装件10的横向边缘向内朝着位于封装件10和衬底20之间的中心区域延伸距离26。示出的距离28可以是例如封装件10的横向宽度或长度。距离26可以是封装件10的最小横向距离,距离26可以等于或大于0,并且可以小于距离28的一半。例如,距离26可以是:,其中距离26是“D26”,且距离28是“D28”。在一些实施例中,底部填充材料22填充封装件10和衬底20之间的区域的约10%至约70%,诸如介于约20%和约50%之间,且进一步地介于约20%和约40%之间。
图4示出了位于封装件60上的外部电连接件62的图案的布局图的另一个实例。外部电连接件62沿着封装件60的每个边缘成两行。底部填充材料64密封且环绕每个外部电连接件62,并且在另一个实例中,可以不对每个外部电连接件62进行密封。在中心区域66中形成诸如气隙的间隙。可以如上文所述的形成底部填充材料64。
实施例可以实现多种优势。例如,FOWLP结构与图1中所示的结构相似并且具有15×15mm2的面积,其经历了可靠性测试并具有改进的性能。在热循环测试中,热循环包括在-40℃至125℃范围内每小时循环两个周期,FOWLP结构在故障前(诸如球破裂)经历了1205个周期。在下落测试中,例如,使用5000G的加速度,FOWLP结构经历20次下落而不发生故障。这些结果确定了在不具有底部填充材料和具有全部底部填充材料的相似结构上的改进。实施例可以有利地应用于具有较大的封装尺寸、较小的球间距、较小的球尺寸、较薄的封装高度或它们的组合的封装件,以提高这类封装件的可靠性。
一实施例是一种结构,该结构包括第一封装件、衬底和将第一封装件机械连接并电连接至衬底的第一外部电连接件。第一封装件包含第一管芯。第一外部电连接件位于第一封装件和衬底之间。底部填充材料环绕第一封装件的第一***区域并且位于第一***区域和衬底之间。第一间隙位于第一封装件的第一中心区域和衬底之间,并且不包含底部填充材料。
另一个实施例是一种结构,该结构包含封装件、衬底和设置在封装件与衬底之间的外部电连接件。封装件包含具有有源侧的管芯、至少横向密封管芯的密封剂和位于管芯的有源侧和密封剂上的重分布结构。外部电连接件将衬底机械连接并电连接至封装件,并且电连接件通过重分布结构电连接至管芯的有源侧。底部填充材料环绕封装件的外边缘并且设置在封装件的外边缘和衬底之间。气隙位于封装件和衬底之间,并且底部填充材料围绕气隙。
又一个实施例是一种方法,该方法包含使用外部电连接件将封装件附接至衬底,并且围绕封装件的***区域和在***区域与衬底之间的第一间隔中形成底部填充材料。外部电连接件设置在封装件和衬底之间。封装件包含密封的管芯和将管芯电连接至外部电连接件的重分布结构。第二间隔位于封装件的中心区域和衬底之间并且不包括底部填充材料。
尽管已经详细地描述了本发明的实施例及其优势,但应该理解,在不背离所附权利要求限定的本发明的精神和范围的情况下,可以对本发明作出各种改变、替换和更改。而且,本申请的范围预期不限于本说明书中描述的工艺、机器、制造、材料组分、工具、方法和步骤的特定实施例。作为本领域普通技术人员将很容易地理解,根据本发明,可以利用现有的或今后将开发的、用于与本发明描述的相应实施例执行基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、工具、方法或步骤。相应地,所附权利要求旨在将这些工艺、机器、制造、材料组分、工具、方法或步骤包括在它们的范围内。
Claims (20)
1.一种半导体结构,包括:
第一封装件,包含第一管芯;
衬底;
第一外部电连接件,将所述第一封装件机械连接和电连接至所述衬底,所述第一外部电连接件位于所述第一封装件和所述衬底之间;以及
底部填充材料,环绕所述第一封装件的第一***区域并且位于所述第一***区域和所述衬底之间,所述第一封装件的第一中心区域和所述衬底之间存在第一间隙,并且自顶向下看,所述第一间隙不包含所述底部填充材料,所述第一间隙内也不包含位于所述封装件的底面上以及位于所述衬底的顶面上的任何导电部件,所述第一间隙与所述底部填充材料邻接,
其中,所述第一中心区域是所述第一封装件中除去所述第一***区域且不包含所述底部填充材料的区域。
2.根据权利要求1所述的半导体结构,其中,所述第一间隙是气隙。
3.根据权利要求1所述的半导体结构,其中,所述底部填充材料密封所述第一间隙。
4.根据权利要求1所述的半导体结构,其中,所述底部填充材料至少环绕所述第一封装件的第一***区域上的外部的所述第一外部电连接件。
5.根据权利要求1所述的半导体结构,其中,所述底部填充材料填充所述第一封装件和所述衬底之间的大于或等于10%且不超过70%的体积。
6.根据权利要求1所述的半导体结构,其中,所述底部填充材料填充所述第一封装件和所述衬底之间的大于或等于20%且不超过50%的体积。
7.根据权利要求1所述的半导体结构,其中,所述底部填充材料填充所述第一封装件和所述衬底之间的大于或等于20%且不超过40%的体积。
8.根据权利要求1所述的半导体结构,其中,所述第一封装件包括:
密封剂,至少横向地密封所述第一管芯;以及
重分布结构,位于所述第一管芯的有源侧和所述密封剂上,所述重分布结构包括介电层和位于所述介电层上的导电图案,所述导电图案将所述第一管芯电连接至所述外部电连接件。
9.一种半导体结构,包括:
封装件,包括:
管芯,具有有源侧,
密封剂,至少横向地密封所述管芯,和
重分布结构,位于所述管芯的有源侧和所述密封剂上,
衬底;
外部电连接件,设置在所述封装件和所述衬底之间,所述外部电连接件将所述衬底机械连接并电连接至所述封装件,所述电连接件通过所述重分布结构电连接至所述管芯的有源侧;以及
底部填充材料,环绕所述封装件的外边缘并且设置在所述封装件的外边缘和所述衬底之间,所述封装件的中心区域和所述衬底之间存在气隙,所述底部填充材料围绕且邻接所述气隙,其中,自顶向下看,所述气隙内不含有位于所述封装件的底面上以及位于所述衬底的顶面上的任何导电部件,
其中,所述中心区域是所述封装件中除去所述外边缘且不包含所述底部填充材料的区域。
10.根据权利要求9所述的半导体结构,其中,所述底部填充材料至少环绕外部的所述外部电连接件。
11.根据权利要求9所述的半导体结构,其中,所述底部填充材料连续地围绕所述气隙。
12.根据权利要求9所述的半导体结构,其中,所述底部填充材料填充所述封装件和所述衬底之间的间隔的10%至70%。
13.根据权利要求9所述的半导体结构,其中,所述底部填充材料填充所述封装件和所述衬底之间的间隔的20%至50%。
14.根据权利要求9所述的半导体结构,其中,所述底部填充材料填充所述封装件和所述衬底之间的间隔的20%至40%。
15.一种形成半导体结构的方法,包括:
使用外部电连接件将封装件附接至衬底,所述外部电连接件设置在所述封装件和所述衬底之间,所述封装件包括密封的管芯和将所述管芯电连接至所述外部电连接件的重分布结构;以及
围绕所述封装件的***区域并在所述***区域和所述衬底之间的第一间隔中形成底部填充材料,自顶向下看,位于所述封装件的中心区域和所述衬底之间的第二间隔不包含所述底部填充材料,并且,所述第二间隔不包含位于所述封装件的底面上以及位于所述衬底的顶面上的任何导电部件,所述第二间隔与所述底部填充材料邻接,
其中,所述中心区域是所述封装件中除去所述***区域且不包含所述底部填充材料的区域。
16.根据权利要求15所述的形成半导体结构的方法,其中,围绕所述***区域连续地形成所述底部填充材料。
17.根据权利要求15所述的形成半导体结构的方法,其中,所述第二间隔包含空气。
18.根据权利要求15所述的形成半导体结构的方法,其中,所述第二间隔是所述封装件和所述衬底之间体积的30%至90%。
19.根据权利要求15所述的形成半导体结构的方法,其中,形成所述底部填充材料包括:
沿着所述封装件的横向边缘的部分分配所述底部填充材料,其中,不沿着所述横向边缘的全部分配所述底部填充材料;以及
随后,沿着所述横向边缘的全部分配所述底部填充材料。
20.根据权利要求15所述的形成半导体结构的方法,其中,形成所述底部填充材料包括:围绕所述封装件的***分配所述底部填充材料,所述封装件在分配所述底部填充材料期间保持静止。
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