CN104714590B - NMOS drive output band-gap reference circuit - Google Patents
NMOS drive output band-gap reference circuit Download PDFInfo
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- CN104714590B CN104714590B CN201510012144.3A CN201510012144A CN104714590B CN 104714590 B CN104714590 B CN 104714590B CN 201510012144 A CN201510012144 A CN 201510012144A CN 104714590 B CN104714590 B CN 104714590B
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Abstract
The invention provides an NMOS drive output band-gap reference circuit. The NMOS drive output band-gap reference circuit comprises a starting circuit module for providing a bias voltage, an operational amplifier used for fixing node voltages at the two feedback input ends of a band-gap reference module and the band-gap reference module used for generating a reference voltage with the zero-temperature coefficient; the starting circuit module provides the bias voltage for the operational amplifier and the band-gap reference module. According to the NMOS drive output band-gap reference circuit, an NMOS serves as output of the band-gap reference voltage, and the band-gap reference drive capacity is improved; a PMOS is used for starting the current of the circuit in a mirroring mode, hundreds of nA of current flows through a band-gap reference zero-temperature coefficient generation circuit, the band-gap reference starting capacity is strengthened, and the circuit reliability is improved. Unit resistors are connected in parallel or in series to be equivalent to a resistor R0, so that the resistance matching performance is improved, and the band-gap reference accuracy is optimized; the resistors are connected between an NMOS drive pipe and a power source in series, so that the electrostatic protection capacity of the circuit is improved.
Description
Technical field
The present invention relates to extensive analogue layout field, more particularly to a kind of being applied to has stronger drive
Kinetic force, the band-gap reference circuit of current start mechanism.
Background technology
Reference voltage source is the foundation stone of cmos IC design, provides reference voltage for analog circuits most in chip,
As digital-to-analogue conversion (d/a convertor) circuit, analog digital conversion ((a/d convertor) circuit, phaselocked loop, power management mould
Block and comparator etc..
Preferably the output voltage of reference voltage source does not change with the change of temperature, technique, supply voltage and load.
The mode realizing reference voltage has stabilivolt, thermal voltage a reference source, vbe a reference source and band gap reference etc..Wherein band gap base
Reference voltage source obtains because itself having the advantage such as, low-temperature coefficient compatible with cmos standard technology and high power supply rejection ability
To being widely applied.
With the continuous improvement of chip integration, the continuous development of mobile communication, the performance requirement to band-gap reference for the chip
Increasingly harsher.In high-precision chip, such as high-precision a/d, d/a transducer will to the precision of band-gap reference output voltage
Ask strict, conventional trim then increases the area of chip.And in large-scale chip, band-gap reference provides for multiple modules
Reference voltage, output loading is larger, needs extra driving stage to realize, and increases the power consumption of circuit.Large-scale with chip
Produce and the inevitable deviation of technique, the reliability of bandgap voltage reference determines the reliability of whole chip, improve
The reliability of bandgap voltage reference is particularly important.
Therefore, the output loading how solving band-gap reference circuit in prior art is big, power consumption is big, the reliability of voltage source
The problems such as difference, has become one of those skilled in the art's problem demanding prompt solution.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of nmos drives output band gap base
Quasi- circuit, the output loading for solving band-gap reference circuit in prior art is big, power consumption is big, the poor reliability of voltage source etc. is asked
Topic.
For achieving the above object and other related purposes, the present invention provides a kind of nmos to drive output band-gap reference circuit,
Described nmos drives output band-gap reference circuit at least to include:
Start-up circuit module, operational amplifier module and band-gap reference module；
Described start-up circuit module provides bias voltage to described operational amplifier module and described band-gap reference module, treats
After described nmos drives output band-gap reference circuit to open, described start-up circuit module is automatically switched off；
The positive differential input of described operational amplifier module and negative differential input end respectively with described band-gap reference module
Negative feedback input and positive feedback input connect, for fixing the section of two feedback input ends of described band-gap reference module
Point voltage；
Described band-gap reference module is used for producing the reference voltage of zero-temperature coefficient, wherein, described band-gap reference module
Output stage is managed for output driving nmos, and the input of described output driving nmos pipe is connected to the defeated of described operational amplifier module
Go out end.
Preferably, described start-up circuit module includes the 5th pmos pipe, the 6th pmos pipe, the 7th pmos pipe, the 8th pmos
Pipe, the 9th pmos pipe, the tenth pmos pipe, the 11st pmos pipe, the 12nd pmos pipe, the 5th nmos pipe, the 6th nmos pipe, the 7th
Nmos pipe, the 8th nmos pipe, biasing bjt pipe and biasing resistor；
Wherein, the source of described 5th pmos pipe and described 6th pmos pipe connects power supply, described 5th pmos pipe and institute
The grid end stating the 6th pmos pipe is connected and connects to the drain terminal of described 6th pmos pipe；The source of described 7th pmos pipe is connected to
The drain terminal of described 5th pmos pipe, the source of described 8th pmos is connected to the drain terminal of described 6th pmos pipe as described startup
The outfan of circuit module, the grid end of described 7th pmos pipe and described 8th pmos is connected and connects to described 8th pmos pipe
Drain terminal；The drain terminal of described 5th nmos pipe is connected to the drain terminal of described 7th pmos pipe, and the drain terminal of described 6th nmos pipe is even
It is connected to the drain terminal of described 8th pmos pipe, the grid end of described 5th nmos pipe and described 6th nmos pipe is connected and connects to described
The drain terminal of the 5th nmos pipe；The drain terminal of described 7th nmos pipe is connected to the grid of described 7th pmos pipe and described 8th pmos pipe
End, source are connected to the grid end of described 5th nmos pipe and described 6th nmos pipe；The emitter stage of described biasing bjt pipe is connected to
The source of described 5th nmos pipe, base stage and grounded collector；One end of described biasing resistor is connected to described 6th nmos pipe
Source, the other end ground connection；The source of described 9th pmos pipe connects the source that electric source and drain is connected to described tenth pmos pipe
End；The drain terminal of described tenth pmos pipe is connected to the source of described 11st pmos pipe；The drain terminal of described 11st pmos pipe is even
It is connected to the source of described 12nd pmos pipe；The drain terminal of described 12nd pmos pipe is connected to the drain terminal of described 8th nmos pipe simultaneously
It is connected to the grid end of described 7th nmos pipe；The source ground connection of described 8th nmos pipe；Described 9th pmos pipe, the described tenth
Pmos pipe, the grid end of described 11st pmos pipe, described 12nd pmos pipe and described 8th nmos pipe are connected and are connected to institute
State the grid end of the 5th nmos pipe and described 6th nmos pipe.
Preferably, described operational amplifier module include first order tail current pmos pipe, the first Differential Input pmos pipe, the
Two Differential Input pmos pipes, the first load nmos pipe, the second load nmos pipe, second level tail current pmos pipe and the 3rd nmos
Pipe；
Wherein, the source of described first order tail current pmos pipe connects power supply, grid end is connected to described start-up circuit module
Outfan, drain terminal be connected to described first Differential Input pmos pipe and described second Differential Input pmos pipe source；Described
The grid end of the first Differential Input pmos pipe, as the positive differential input of described operational amplifier module, is connected to described band gap base
The negative feedback input of quasi-mode block；The grid end of described second Differential Input pmos pipe is as the minus tolerance of described operational amplifier module
Divide input, be connected to the positive feedback input of described band-gap reference module；The drain terminal of described first load nmos pipe is connected to
The drain terminal of described first Differential Input pmos pipe, source ground connection；The drain terminal of described second load nmos pipe is connected to described second
The drain terminal of Differential Input pmos pipe, source ground connection；The grid end of described first load nmos pipe and the second load nmos pipe is connected simultaneously
Connect to the drain terminal of the described first load nmos pipe；The source of described second level tail current pmos pipe connects power supply, grid end connects
Outfan in described start-up circuit module；The drain terminal of described 3rd nmos pipe is connected to described second level tail current pmos pipe
Drain terminal is as the outfan of described operational amplifier module, source is grounded, grid end is connected to described second Differential Input pmos pipe
And described second load nmos pipe drain terminal.
It is highly preferred that described operational amplifier module also includes miller compensation electric capacity and zero-regulator resistor；Wherein, described close
The one end strangling compensating electric capacity is connected to the drain terminal of described 3rd nmos pipe, the other end connects to described the via described zero-regulator resistor
The grid end of three nmos pipes.
Preferably, described band-gap reference module includes current start pmos pipe, output driving nmos pipe, the first negative temperature system
Number voltage produces resistance, the second negative temperature coefficient voltage produces resistance, positive temperature coefficient voltage produces resistance, the first temperature coefficient
Pnp transistor and second temperature coefficient pnp transistor；
Wherein, the drain terminal of the source of described current start pmos pipe and described output driving nmos pipe connects power supply；Described
The grid end of current start pmos pipe is connected to the outfan of described start-up circuit module；The grid end of described output driving nmos pipe is even
It is connected to the outfan of described operational amplifier module；The drain terminal of described current start pmos pipe, described output driving nmos pipe
Source, described first negative temperature coefficient voltage produce one end of resistance and described second negative temperature coefficient voltage produces the one of resistance
End is connected, and the outfan as described band-gap reference module exports described reference voltage；Described first negative temperature coefficient voltage produces
The other end of raw resistance is connected to the emitter stage of described first temperature coefficient pnp transistor, as described band-gap reference module
Positive feedback input；The base stage of described first temperature coefficient pnp transistor and grounded collector；Described second negative temperature coefficient electricity
The other end that pressure produces resistance is connected to one end that described positive temperature coefficient voltage produces resistance, as described band-gap reference module
Negative feedback input；The other end that described positive temperature coefficient voltage produces resistance is connected to described second temperature coefficient pnp crystalline substance
The emitter stage of body pipe；The base stage of described second temperature coefficient pnp transistor and grounded collector.
It is highly preferred that described band-gap reference module also includes being connected between power supply and the drain electrode of described output driving nmos pipe
Electrostatic protection resistance.
It is highly preferred that described positive temperature coefficient voltage produces resistance includes the first positive temperature coefficient voltage generation square electricity
Resistance, the second positive temperature coefficient voltage produce square resistance, the 3rd positive temperature coefficient voltage produces square resistance, the 4th upright temperature
Coefficient voltages produce the resistance；Wherein, described first positive temperature coefficient voltage produces square resistance and described second positive temperature
After coefficient voltages produce square resistance parallel connection, produce square resistance and described the with described 3rd positive temperature coefficient voltage in parallel
Four positive temperature coefficient voltages produce square resistance series connection.
It is highly preferred that the area of described first temperature coefficient pnp transistor and described second temperature coefficient pnp transistor it
Than for 1:8.
As described above, the nmos of the present invention drives output band-gap reference circuit, have the advantages that
1) present invention is used nmos as the output of bandgap voltage reference, improves the driving force of band-gap reference；
2) present invention uses the electric current of pmos image starting circuit, and band-gap reference zero-temperature coefficient generation circuit flows through hundreds of
Na electric current, strengthens the startup ability of band-gap reference, improves the reliability of circuit；
3) present invention carrys out equivalent resistance r0 using unit resistance series connection in parallel, improves resistors match performance, optimizes band gap base
Quasi- precision；
4) present invention, using series resistance between nmos driving tube and power supply, improves the electrostatic protection ability of circuit.
Brief description
The nmos that Fig. 1 is shown as the present invention drives output band-gap reference circuit schematic diagram.
Component label instructions
1 nmos drives output band-gap reference circuit
11 start-up circuit modules
12 operational amplifier modules
13 band-gap reference modules
Pm0 first order tail current pmos manages
Pm1 the first Differential Input pmos manages
Pm2 the second Differential Input pmos manages
Pm3 second level tail current pmos manages
Pm4 current start pmos manages
Pm5 the 5th pmos manages
Pm6 the 6th pmos manages
Pm7 the 7th pmos manages
Pm8 the 8th pmos manages
Pm9 the 9th pmos manages
Pm10 the tenth pmos manages
Pm11 the 11st pmos manages
Pm12 the 12nd pmos manages
Nm1 first load nmos pipe
Nm2 second load nmos pipe
Nm3 the 3rd nmos manages
Nm4 output driving nmos is managed
Nm5 the 5th nmos manages
Nm6 the 6th nmos manages
Nm7 the 7th nmos manages
Nm8 the 8th nmos manages
Q0 biasing bjt pipe
Q1 the first temperature coefficient pnp transistor
Q2 second temperature coefficient pnp transistor
R0 positive temperature coefficient voltage produces resistance
R1 the first negative temperature coefficient voltage produces resistance
R2 the second negative temperature coefficient voltage produces resistance
R3 zero-regulator resistor
R4 biasing resistor
R5 electrostatic protection resistance
Ra the first positive temperature coefficient voltage produces square resistance
Rb the second positive temperature coefficient voltage produces square resistance
Rc the 3rd positive temperature coefficient voltage produces square resistance
Rd the 4th positive temperature coefficient voltage produces square resistance
ccMiller compensation electric capacity
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.
Refer to Fig. 1.It should be noted that the diagram provided in the present embodiment only illustrates the present invention's in a schematic way
Basic conception, only shows the assembly relevant with the present invention rather than then according to component count during actual enforcement, shape in schema
And size drafting, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout
Kenel is likely to increasingly complex.
As shown in figure 1, a kind of nmos that the present invention provides drives output band-gap reference circuit 1, described nmos drives output
Band-gap reference circuit 1 at least includes:
Start-up circuit module 11, operational amplifier module 12 and band-gap reference module 13.
Described start-up circuit module 11 is used for providing to described operational amplifier module 12 and described band-gap reference module 13
Bias voltage, after described nmos drives output band-gap reference circuit 1 to open, described start-up circuit module 11 is automatically switched off.
Described operational amplifier module 12 is used for fixing the node electricity of described 13 two feedback input ends of band-gap reference module
Pressure.
Described band-gap reference module 13 is used for producing the reference voltage vref of zero-temperature coefficient.
Wherein, described start-up circuit module 11 starts the biasing input of voltage output point and described operational amplifier module 12
End starts input point o point with band-gap reference module and is connected；The positive differential input y point of described operational amplifier module 12 and minus tolerance
Input x point is divided to be connected with the negative feedback input of described band-gap reference module 13 and positive feedback input respectively；Described computing
Amplifier module 12 outfan is connected with the nmos driving stage input of described band-gap reference module 13.
Specifically, as shown in figure 1, in the present embodiment, described start-up circuit module 11 include the 5th pmos pipe pm5,
Six pmos pipe pm6, the 7th pmos pipe pm7, the 8th pmos pipe pm8, the 5th nmos pipe nm5, the 6th nmos pipe nm6, the 7th nmos
Pipe nm7, the 9th pmos pipe pm9, the tenth pmos pipe pm10, the 11st pmos pipe pm11, the 12nd pmos pipe pm12, the 8th nmos
Pipe nm8, biasing bjt pipe q0 and biasing resistor r4.
Wherein, the source of described 5th pmos pipe pm5, the source of described 6th pmos pipe pm6 and described 9th pmos
The source of pipe pm9 is connected with power supply avdd；The drain terminal of described 5th pmos pipe pm5 and the source phase of described 7th pmos pipe pm7
Even；The grid end of described 5th pmos pipe pm5, the grid end of described 6th pmos pipe pm6, the drain terminal of described 6th pmos pipe pm6 with
And the source of described 8th nmos pipe nm8 is connected and connects to the first order tail current pmos pipe of described operational amplifier module 12
The current start pmos pipe of the grid end of pm0, the grid end of second level tail current pmos pipe pm3 and described band-gap reference module 13
The grid end of pm4；The grid end of described 7th pmos pipe pm7, the grid end of described 8th pmos pipe pm8, described 8th pmos pipe pm8
Drain terminal, the drain terminal of described 7th nmos pipe nm7 and described 6th nmos pipe nm6 are connected；The leakage of described 7th pmos pipe pm7
End, the source of described 7th nmos pipe nm7, the drain terminal of described 5th nmos pipe nm5, the grid end of described 5th nmos pipe nm5, institute
State the grid end of the 6th nmos pipe nm6, the grid end of described 9th pmos pipe pm9, the grid end of described tenth pmos pipe pm10, described
The grid end phase of the grid end of 11 pmos pipe pm11, the grid end of described 12nd pmos pipe pm12 and described 8th nmos pipe nm8
Even；The source of described 5th nmos pipe nm5 is connected with the emitter stage of described biasing bjt pipe q0；The source of described 6th nmos pipe nm6
End is connected with one end of described biasing resistor r4；The base stage of described biasing bjt pipe q0, colelctor electrode, described 8th nmos pipe nm8's
The other end of source and described biasing resistor r4 is connected with ground avss；The drain terminal and the described tenth of described 9th pmos pipe pm9
The source of pmos pipe pm10 is connected；The drain terminal of described tenth pmos pipe pm10 and the source phase of described 11st pmos pipe pm11
Even；The drain terminal of described 11st pmos pipe pm11 is connected with the source of described 12nd pmos pipe pm12；Described 12nd pmos
The drain terminal of pipe pm12, the drain terminal of described 8th nmos pipe nm8 are connected with the grid end of described 7th nmos pipe nm7.
The present invention uses the electric current of pmos image starting circuit, and band-gap reference zero-temperature coefficient produces circuit and flows through hundreds of na
Electric current, strengthens the startup ability of band-gap reference, improves the reliability of circuit.
Specifically, as shown in figure 1, in the present embodiment, described operational amplifier module includes first order tail current pmos
Pipe pm0, the first Differential Input pmos pipe pm1, the second Differential Input pmos pipe pm2, the first load nmos pipe nm1, the second load
Nmos pipe nm2, second level tail current pmos pipe pm3, the 3rd nmos pipe nm3, miller compensation electric capacity cc and zero-regulator resistor r3.
Wherein, the source of described first order tail current pmos pipe pm0, the source of described second level tail current pmos pipe pm3
It is connected with power supply avdd；The drain terminal of described first order tail current pmos pipe pm0, the source of described first Differential Input pmos pipe pm1
End is connected with the source of described second Differential Input pmos pipe pm2；Described first load nmos pipe nm1 grid end, described first
The drain terminal of load nmos pipe nm1, the drain terminal of described first Differential Input pmos pipe pm1 are with described second load nmos pipe nm2's
Grid end is connected；The described second load drain terminal of nmos pipe nm2, the drain terminal of described second Differential Input pmos pipe pm2, the described 3rd
The grid end of nmos pipe nm3 is connected with one end of described zero-regulator resistor r3；The other end of described zero-regulator resistor r3 is mended with described Miller
The one end repaying electric capacity cc is connected；The other end of described miller compensation electric capacity cc, the drain terminal of described 3rd nmos pipe nm3 and described
The drain terminal of second level tail current pmos pipe pm3 is connected and connects to the grid end of described output driving nmos pipe nm4；Described first is negative
Carry source, the source of described second load nmos pipe nm2, the source of described 3rd nmos pipe nm3 and the ground avss of nmos pipe nm1
It is connected.
Specifically, as shown in figure 1, in the present embodiment, described band-gap reference module 13 includes current start pmos pipe
Pm4, output driving nmos pipe nm4, electrostatic protection resistance r5, the first negative temperature coefficient voltage produce resistance r1, the second negative temperature
Coefficient voltages produce resistance r2, the first positive temperature coefficient voltage produces square resistance ra, the second positive temperature coefficient voltage generation side
Block resistance rb, the 3rd positive temperature coefficient voltage produce square resistance rc, the 4th positive temperature coefficient voltage produces square resistance rd, the
One temperature coefficient pnp transistor q1, second temperature coefficient pnp transistor q2.
Wherein, the source of described current start pmos pipe pm4, one end of described electrostatic protection resistance r5 and power supply avdd phase
Even；The other end of described electrostatic protection resistance r5 is connected with the drain terminal of described output driving nmos pipe nm4；Described current start
The drain terminal of pmos pipe pm4, the source of described output driving nmos pipe nm4, described first negative temperature coefficient voltage produce resistance r1
One end and described second negative temperature coefficient voltage produce resistance r2 one end be connected；Described second negative temperature coefficient voltage produces
The other end of raw resistance r2, the grid end of described first Differential Input pmos pipe pm1, described first positive temperature coefficient voltage generation side
One end of block resistance ra produces square resistance rb with described second positive temperature coefficient voltage and is connected；Described 3rd positive temperature coefficient electricity
Pressure produces one end of square resistance rc, described 4th positive temperature coefficient voltage produces one end of square resistance rd, described second temperature
The emitter stage of degree coefficient pnp transistor q2 is connected；Described first positive temperature coefficient voltage produces the other end of square resistance ra, institute
State the second positive temperature coefficient voltage and produce the other end of square resistance rb, described 3rd positive temperature coefficient voltage generation square resistance
The other end that the other end of rc produces square resistance rd with positive temperature coefficient voltage described in the 4th is connected；Described first negative temperature system
Number voltages produce the other end of resistance r1, the grid end of the second Differential Input pmos pipe pm2 of described operational amplifier module 12 with
The emitter stage of described first temperature coefficient pnp transistor q1 is connected；The base stage of described first temperature coefficient pnp transistor q1, institute
State the colelctor electrode of the first temperature coefficient pnp transistor q1, the base stage of described second temperature coefficient pnp transistor q2, described second
The colelctor electrode of temperature coefficient pnp transistor q2 is connected with ground avss.
In the present embodiment, described first temperature coefficient pnp transistor q1 and described second temperature coefficient pnp transistor q2
Area ratio be 1:8.
The present invention is used nmos as the output of bandgap voltage reference, improves the driving force of band-gap reference.Output is driven
Connect between dynamic nmos pipe nm4 and power supply avdd electrostatic protection resistance r5, effectively improves the electrostatic protection ability of circuit.
Described first positive temperature coefficient voltage produces square resistance ra, the second positive temperature coefficient voltage produces square resistance
Rb, the 3rd positive temperature coefficient voltage produce square resistance rc, cubic positive temperature coefficient voltage produces the resistance rd and is equivalent to
Positive temperature coefficient voltage produces resistance r0.The present invention carrys out equivalent PTC voltage using unit resistance series connection in parallel and produces electricity
Resistance r0, can effectively improve resistors match performance, optimize band-gap reference precision.
As shown in figure 1, the nmos of the present invention drives the operation principle of output band-gap reference circuit 1 as follows:
Upon power-up, in described start-up circuit module 11, the grid end of described 6th nmos pipe nm6 is low level, described the
Five nmos pipe nm5, described 6th nmos pipe nm6, described 8th nmos pipe nm8 turn off, the leakage of described 12nd pmos pipe pm12
Hold as high level, described 9th pmos pipe pm9, described tenth pmos pipe pm10, described 11st pmos pipe pm11 and described
12nd pmos pipe pm12 opens so that described 7th nmos pipe nm7 also opens.After described 7th nmos pipe nm7 opens, by institute
State the 7th pmos pipe pm7, the grid end of described 8th pmos pipe pm8 drags down, described 5th nmos pipe nm5, described 6th nmos pipe
The grid end of nm6 is drawn high, then described 5th pmos pipe pm5, and described 6th pmos pipe pm6 place branch road has electric current to produce.When described
5th nmos pipe nm5, after the grid end of described 6th nmos pipe nm6 is driven high, described 8th nmos pipe nm8 opens, and the described 9th
Pmos pipe pm9, described tenth pmos pipe pm10, described 11st pmos pipe pm11, described 12nd pmos pipe pm12 presents greatly
Resistance, the drain terminal of described 8th nmos pipe nm8 is pulled low, and described 7th nmos pipe nm7 turns off.Described 6th pmos pipe pm6's
Current mirror gives described first order tail current pmos pipe pm0, the second level tail current pmos pipe of described operational amplifier module 12
The pm3 and described current start pmos pipe pm4 of described band-gap reference module 13, thus whole circuit is opened.
In described band-gap reference module 13, described first temperature coefficient pnp transistor q1, described second temperature coefficient pnp
The voltage difference of transistor q2 emitter stage and base stage is positive temperature coefficient, flows through described second negative temperature coefficient voltage and produces resistance
The electric current of r2 is positive temperature coefficient, and reference voltage vref is described second temperature coefficient pnp transistor q2 two ends negative temperature coefficient
Voltage add that described second negative temperature coefficient voltage produces the voltage gained of resistance r2 two ends positive temperature coefficients, in certain condition
Under, negative temperature coefficient voltage and positive temperature coefficient are cancelled out each other, and vref is the output voltage of zero-temperature coefficient.
In sum, the present invention provides a kind of nmos to drive output band-gap reference circuit, including start-up circuit module, computing
Amplifier module and band-gap reference module；Described start-up circuit module is to described operational amplifier module and described band-gap reference
Module provides bias voltage, and after described nmos drives output band-gap reference circuit to open, described start-up circuit module is closed automatically
Close；The positive differential input of described operational amplifier module and negative differential input end are negative anti-with described band-gap reference module respectively
Feedback input and positive feedback input connect, for fixing the node electricity of two feedback input ends of described band-gap reference module
Pressure；Described band-gap reference module is used for producing the reference voltage of zero-temperature coefficient, wherein, the output stage of described band-gap reference module
Manage for output driving nmos, the input of described output driving nmos pipe is connected to the outfan of described operational amplifier module.
The present invention is used nmos as the output of bandgap voltage reference, improves the driving force of band-gap reference；Opened using pmos mirror image
The electric current on galvanic electricity road, band-gap reference zero-temperature coefficient produces circuit and flows through hundreds of na electric current, strengthens the startup ability of band-gap reference,
Improve the reliability of circuit；Carry out equivalent resistance r0 using unit resistance series connection in parallel, improve resistors match performance, optimize band gap base
Quasi- precision；Using series resistance between nmos driving tube and power supply, improve the electrostatic protection ability of circuit.So, the present invention
Effectively overcome various shortcoming of the prior art and have high industrial utilization.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (7)
1. a kind of nmos drives output band-gap reference circuit it is characterised in that described nmos drives output band-gap reference circuit extremely
Few inclusion:
Start-up circuit module, operational amplifier module and band-gap reference module；
Described start-up circuit module provides bias voltage to described operational amplifier module and described band-gap reference module, treats described
After nmos drives output band-gap reference circuit to open, described start-up circuit module is automatically switched off；
The positive differential input of described operational amplifier module and negative differential input end are negative with described band-gap reference module respectively
Feedback input end and positive feedback input connect, for fixing the node electricity of two feedback input ends of described band-gap reference module
Pressure；
Described band-gap reference module is used for producing the reference voltage of zero-temperature coefficient, wherein, the output of described band-gap reference module
Level is connected to the output of described operational amplifier module for output driving nmos pipe, the input of described output driving nmos pipe
End；
Wherein, described band-gap reference module includes current start pmos pipe, output driving nmos pipe, the first negative temperature coefficient voltage
Produce resistance, the second negative temperature coefficient voltage produces resistance, positive temperature coefficient voltage produces resistance, the first temperature coefficient pnp is brilliant
Body pipe and second temperature coefficient pnp transistor；
Wherein, the drain terminal of the source of described current start pmos pipe and described output driving nmos pipe connects power supply；Described electric current
The grid end starting pmos pipe is connected to the outfan of described start-up circuit module；The grid end of described output driving nmos pipe is connected to
The outfan of described operational amplifier module；The drain terminal of described current start pmos pipe, the source of described output driving nmos pipe,
Described first negative temperature coefficient voltage produces one end of resistance and described second negative temperature coefficient voltage produces one end phase of resistance
Even, the outfan as described band-gap reference module exports described reference voltage；Described first negative temperature coefficient voltage produces electricity
The other end of resistance is connected to the emitter stage of described first temperature coefficient pnp transistor, positive and negative as described band-gap reference module
Feedback input；The base stage of described first temperature coefficient pnp transistor and grounded collector；Described second negative temperature coefficient voltage produces
The other end of raw resistance is connected to one end that described positive temperature coefficient voltage produces resistance, negative as described band-gap reference module
Feedback input end；The other end that described positive temperature coefficient voltage produces resistance is connected to described second temperature coefficient pnp transistor
Emitter stage；The base stage of described second temperature coefficient pnp transistor and grounded collector.
2. nmos according to claim 1 drive output band-gap reference circuit it is characterised in that:
Described start-up circuit module includes the 5th pmos pipe, the 6th pmos pipe, the 7th pmos pipe, the 8th pmos pipe, the 9th pmos
Pipe, the tenth pmos pipe, the 11st pmos pipe, the 12nd pmos pipe, the 5th nmos pipe, the 6th nmos pipe, the 7th nmos pipe, the 8th
Nmos pipe, biasing bjt pipe and biasing resistor；
Wherein, the source of described 5th pmos pipe and described 6th pmos pipe connects power supply, described 5th pmos pipe and described the
The grid end of six pmos pipes is connected and connects to the drain terminal of described 6th pmos pipe；The source of described 7th pmos pipe is connected to described
The drain terminal of the 5th pmos pipe, the source of described 8th pmos is connected to the drain terminal of described 6th pmos pipe as described start-up circuit
The outfan of module, the grid end of described 7th pmos pipe and described 8th pmos is connected and connects to the leakage of described 8th pmos pipe
End；The drain terminal of described 5th nmos pipe is connected to the drain terminal of described 7th pmos pipe, and the drain terminal of described 6th nmos pipe is connected to
The drain terminal of described 8th pmos pipe, the grid end of described 5th nmos pipe and described 6th nmos pipe is connected and connects to the described 5th
The drain terminal of nmos pipe；The drain terminal of described 7th nmos pipe be connected to described 7th pmos pipe and described 8th pmos pipe grid end,
Source is connected to the grid end of described 5th nmos pipe and described 6th nmos pipe；The emitter stage of described biasing bjt pipe is connected to institute
State source, base stage and the grounded collector of the 5th nmos pipe；One end of described biasing resistor is connected to described 6th nmos pipe
Source, other end ground connection；The source of described 9th pmos pipe connects the source that electric source and drain is connected to described tenth pmos pipe；
The drain terminal of described tenth pmos pipe is connected to the source of described 11st pmos pipe；The drain terminal of described 11st pmos pipe is connected to
The source of described 12nd pmos pipe；The drain terminal of described 12nd pmos pipe is connected to the drain terminal of described 8th nmos pipe and connects
Grid end in described 7th nmos pipe；The source ground connection of described 8th nmos pipe；Described 9th pmos pipe, described tenth pmos
Pipe, the grid end of described 11st pmos pipe, described 12nd pmos pipe and described 8th nmos pipe are connected and are connected to described the
Five nmos pipes and the grid end of described 6th nmos pipe.
3. nmos according to claim 1 drive output band-gap reference circuit it is characterised in that:
Described operational amplifier module includes first order tail current pmos pipe, the first Differential Input pmos pipe, the second Differential Input
Pmos pipe, the first load nmos pipe, the second load nmos pipe, second level tail current pmos pipe and the 3rd nmos pipe；
Wherein, the source of described first order tail current pmos pipe connects power supply, grid end is connected to the defeated of described start-up circuit module
Go out end, drain terminal be connected to described first Differential Input pmos pipe and described second Differential Input pmos pipe source；Described first
The grid end of Differential Input pmos pipe, as the positive differential input of described operational amplifier module, is connected to described band-gap reference mould
The negative feedback input of block；The grid end of described second Differential Input pmos pipe as described operational amplifier module minus tolerance divide defeated
Enter end, be connected to the positive feedback input of described band-gap reference module；The drain terminal of described first load nmos pipe is connected to described
The drain terminal of the first Differential Input pmos pipe, source ground connection；The drain terminal of described second load nmos pipe is connected to described second difference
The drain terminal of input pmos pipe, source ground connection；The grid end of described first load nmos pipe and the second load nmos pipe is connected and connects
Drain terminal to described first load nmos pipe；The source of described second level tail current pmos pipe connects power supply, grid end is connected to institute
State the outfan of start-up circuit module；The drain terminal of described 3rd nmos pipe is connected to the drain terminal of described second level tail current pmos pipe
It is connected to described second Differential Input pmos pipe and institute as the outfan of described operational amplifier module, source ground connection, grid end
State the drain terminal of the second load nmos pipe.
4. nmos according to claim 3 drive output band-gap reference circuit it is characterised in that: described operational amplifier mould
Block also includes miller compensation electric capacity and zero-regulator resistor；Wherein, one end of described miller compensation electric capacity is connected to the described 3rd
The drain terminal of nmos pipe, the other end connect via described zero-regulator resistor to the grid end of described 3rd nmos pipe.
5. nmos according to claim 1 drive output band-gap reference circuit it is characterised in that: described band-gap reference module
Also include the electrostatic protection resistance being connected between power supply and the drain electrode of described output driving nmos pipe.
6. nmos according to claim 1 drive output band-gap reference circuit it is characterised in that: described positive temperature coefficient electricity
Pressure generation resistance includes the first positive temperature coefficient voltage generation square resistance, the second positive temperature coefficient voltage produces square resistance,
3rd positive temperature coefficient voltage produces square resistance, the 4th positive temperature coefficient voltage produces square resistance；Wherein, described first just
After temperaturecoefficient voltage generation square resistance is in parallel with described second positive temperature coefficient voltage generation square resistance, with institute in parallel
State the 3rd positive temperature coefficient voltage and produce square resistance and described 4th positive temperature coefficient voltage generation square resistance series connection.
7. nmos according to claim 1 drive output band-gap reference circuit it is characterised in that: described first temperature coefficient
The area ratio of pnp transistor and described second temperature coefficient pnp transistor is 1:8.
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| CN106354186A (en) * | 2015-07-21 | 2017-01-25 | 炬芯（珠海）科技有限公司 | Low-voltage-difference linear voltage stabilizer |
| CN113465764B (en) * | 2020-03-31 | 2023-01-10 | 圣邦微电子（北京）股份有限公司 | Analog output integrated temperature sensor |
| CN112667016A (en) * | 2020-12-29 | 2021-04-16 | 上海华力微电子有限公司 | Band-gap reference circuit system for high-precision correction of voltage temperature coefficient |
| CN113589874B (en) * | 2021-08-17 | 2022-12-06 | 深圳清华大学研究院 | Linear power supply integrated circuit without off-chip capacitor and wireless charging equipment |
| CN114167931B (en) * | 2021-12-04 | 2023-02-17 | 恒烁半导体(合肥)股份有限公司 | Band-gap reference voltage source capable of being started quickly and application thereof |
| CN114115433B (en) * | 2021-12-29 | 2023-04-18 | 苏州锴威特半导体股份有限公司 | Band gap reference circuit |
| CN115309227B (en) * | 2022-08-04 | 2024-07-02 | 西安电子科技大学 | Full-saturation MOSFET band-gap reference source |
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| CN103383579A (en) * | 2012-05-02 | 2013-11-06 | 上海华虹Nec电子有限公司 | Reference voltage source |
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| US7113025B2 (en) * | 2004-04-16 | 2006-09-26 | Raum Technology Corp. | Low-voltage bandgap voltage reference circuit |
| GB0519987D0 (en) * | 2005-09-30 | 2005-11-09 | Texas Instruments Ltd | Band-gap voltage reference circuit |
| KR101015523B1 (en) * | 2008-06-17 | 2011-02-16 | 주식회사 동부하이텍 | Band Gap Reference Voltage Generator |
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Address after: Zhangjiang Building 20A, 289 Chunxiao Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Co-patentee after: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee after: Xinyuan Microelectronics (Shanghai) Co., Ltd. Co-patentee after: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee after: Core holdings limited company Address before: 201203 Zhangjiang Building 20A, 560 Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Co-patentee before: VeriSilicon Microelectronics (Beijing) Co., Ltd. Patentee before: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Co-patentee before: VERISILICON MICROELECTRONICS (CHENGDU) CO., LTD. Co-patentee before: VeriSilicon Holdings Co., Ltd. |