CN104702282A - Digital calibration method and circuit for multi-stage multi-bit sub circuit in analog-digital converters - Google Patents

Abstract

The invention relates to a digital calibration method for a multi-stage multi-bit sub circuit in analog-digital converters. The digital calibration method for the multi-stage multi-bit sub circuit in the analog-digital converters comprises the steps of first designing a peripheral control circuit, controlling the working condition of ADCs to enable the ADCs to control a sub flow-stage circuit needing to be calibrated, reading output with errors of each sub stage existing in a register inside the corresponding ADC, error calculating, storing error values obtained by calculating to the ADC internal registers, compensating the errors calculated from each sub stage to final output through a data synthesis module and finishing calibration. The digital calibration method and a circuit for the multi-stage multi-bit sub circuit in the analog-digital converters have the main advantages that a digital calibration method for a multi-stage multi-bit sub circuit capacitor mismatch calibration method is provided, and the digital circuit is adopted to achieve the calibration. The calibration control process is achieved outside the analog-digital converters, the whole analog-digital converter design complexity is reduced, the calibration method is simple and convenient and reliable, and the calibration effect is good.

Description

The digital calibrating method of multistage many bits electronic circuit and circuit in analog to digital converter

Technical field

The invention belongs to integrated circuit (IC) design and manufacture field, particularly the digital calibrating method of multistage many bits electronic circuit and circuit in a kind of production line analog-digital converter.

Background technology

Along with developing rapidly of microprocessor and signal processing technology, more and more higher to the performance requirement of analog to digital converter (Analog-to-DigitalConverter, ADC).High-speed high-precision flow line ADC is fast with its conversion speed, and resolution is high, feature low in energy consumption, is widely used in signal transacting field.On the other hand, along with the high speed development of integrated circuit technology, the size of device is more and more less, and the operating rate of device promotes further, and power consumption reduces further.But, it is more and more serious that size reduces caused device mismatch, when the precision of pipeline ADC brings up to more than 12bit, the capacitance mismatch that the deviation of technique causes, the imperfection of amplifier, the generation of comparator imbalance equal error, adopt the method for designing of conventional analog circuits cannot design high performance ADC.The method of digital calibration is adopted to carry out error correction to the data that analog sampling circuit exports, can the error brought of the deviation of compensate for process effectively, the performance of raising pipeline ADC.In the research of high-speed high-precision flow line ADC, the sub-level ADC of every grade of traditional single bits structures realizes the overall power that will significantly improve chip, increases the area of chip.In order to reduce sampling capacitance, reducing power consumption, reducing noise, many bit architecture must be adopted at chopped-off head and what sub-ADC front.In the sub-level ADC of many bit architecture, the capacitance mismatch of comparator will produce nonlinearity erron, have impact on the dynamic property of transducer, needs the error to the capacitance mismatch of the sub-level ADC of many bits causes to calibrate.

As shown in Figure 1, pipeline ADC is by clock generating circuit, pipeline conversion structure, register array is aimed in time delay and digital calibration circuit is formed, wherein pipeline conversion structure is that input sample holding circuit (SHA, Sample-Hold Amplifier) and the cascade of n level change-over circuit are formed.Each streamline level change-over circuit comprises 1 sub-ADC (SADC) and 1 surplus gain digital analog converter (MDAC, Multiplying Digital to Analog Converter).When carrying out digital-to-analogue conversion, sampling hold circuit is sampled at sampling relative input signal, then stage1 is in opposite directions being kept to export, as the input voltage Vi of the 1st grade, SHA circuit in stage1 is sampled to Vi and is kept, SADC carries out A/D conversion to Vi simultaneously, obtaining k1bit transformation result outputs in delay aligning register array as transformation result at the corresponding levels, and the numeral as SADC inputs with the quantitative estimation realized Vi, analog subtraction circuit realiration Vi and k1bit estimated value poor, the difference obtained amplification by amplifier amplify 2 ^k1-1modulating output Vo as the corresponding levels doubly exports to stage2.All the other grade of circuit and the 1st level work similar process.

Fig. 2 is the transfer curve of 1.5bit level circuit, and the circuit of 1.5bit structure exports 3 kinds of digital codes, is 00 when corresponding levels input is less than Vr/4 output code at the corresponding levels.When corresponding levels input is between [-Vr/4, Vr/4], output code at the corresponding levels is 01.When corresponding levels input is greater than Vr/4, output code at the corresponding levels is 10.Do not mate by electric capacity the error brought by calculating at two breakover points, and then by this error compensation, obtain the output of linear relationship, the curve of output after calibration as shown in Figure 3.

The electric capacity number adopted due to the sub-level ADC of many bits is more, and the comparison point of comparator is numerous, and adopt analog circuit implementation method that circuit will be made very complicated, power consumption and area greatly increase.And although the digital calibration techniques of the sub-ADC of existing 1.5bit level has possessed good calibration effect, the requirement of the ADC design of the sub-level structure streamline of the many bits of high accuracy cannot be met.Invent a kind of implementation method simple, realizing circuit is easy, and the much higher level of calibration efficiency, many bit-level electronic circuit calibration steps seem and be necessary very much.

Summary of the invention

A kind of digital calibrating method and the circuit of being convenient to the sub-level ADC of multistage many bits of digital circuit is the invention provides for above problem.

The invention provides the calibration steps of a kind of 3.5bit level comparator capacitance mismatch, carry out multistage calibration, in order to realize correcting the error that capacitance mismatch causes, error calculation realizes outward at sheet, circuit simple and convenient, calibrates effective, less with the change of the external environment such as temperature, voltage.

The digital calibrating method of multistage many bits electronic circuit in a kind of analog to digital converter, described pipeline ADC comprises multiple pipelining-stage, each pipelining-stage comprises sub-ADC, sub-DAC, amplifier and subtracter, analog input signal Vi is input in sub-ADC and carries out the output of quantification generation numeral, this numeral is exported to send in sub-DAC simultaneously and carry out digital-to-analogue conversion, export analog quantity, analog input signal Vi and described output analog quantity are carried out subtraction in subtracter, after amplifier amplifies, obtain output voltage Vo again, be the output of MDAC.Sub-DAC, adder and amplifier constitute MADC jointly.

Due in circuit MDAC adopt is differential configuration export, employing be differential comparator.As shown in Figure 4, if qp, qn are the difference output of comparator level, law of conservation of charge is adopted for same virtual earth point:

A () works as qp=0, during qn=1, and V _reftswitch OFF, V _refbswitch closes, and it is 0 that comparator exports.If x1, x2 are respectively amplifier differential, output is right, VL ₁and VL ₂for common mode electrical level during direct current.

If virtual earth point voltage is 0, by charge conservation, following equation is obtained for ina point:

(0-VL ₁)·C _1.1+(0-VL ₂)·2C _x1＝(0-V _refb)·C _1.1+(0-x1)·2C _x1(1)

Can derive:

$x1=\frac{{\mathrm{VL}}_1-V_{\mathrm{refb}}}{2C_{x1}}\·C_{1.1}+{\mathrm{VL}}_2---\left(2\right)$

It is same for inb point,

(0-VL ₁)·C _2.1+(0-VL ₂)·2C _x2＝(0-V _reft)·C _2.1+(0-x2)·2C _x2(3)

Can derive:

$x2=\frac{{\mathrm{VL}}_1-V_{\mathrm{reft}}}{{2C}_{x2}}\·C_{2.1}+{\mathrm{VL}}_2---\left(4\right)$

By (2) and (4) obtain first comparison point export be 0 time amplifier analog differential export,

$V_{\mathrm{diff}1.0}=x1-x2=\frac{{\mathrm{VL}}_1-V_{\mathrm{refb}}}{2C_{x1}}\·C_{1.1}-\frac{{\mathrm{VL}}_1-V_{\mathrm{reft}}}{{2C}_{x2}}\·C_{2.1}---\left(5\right)$

Similar for other comparison point derivation formulas.

B () works as qp=1, during qn=0, and V _reftswitch closes, V _refbswitch OFF, it is 1 that comparator exports.

The difference output of each comparison point can be obtained according to above-mentioned analysis:

$V_{\mathrm{diff}1.1}=x1-x2=\frac{{\mathrm{VL}}_1-V_{\mathrm{reft}}}{{2C}_{x1}}\·C_{1.1}-\frac{{\mathrm{VL}}_1-V_{\mathrm{refb}}}{{2C}_{x2}}\·C_{2.1}---\left(6\right)$

Similar for other comparison point derivation formulas.

Fig. 5 is the transference curve of 3.5bit level circuit, has 16 comparison point as can be seen from Fig..The digital coding of each comparator output interval that 3.5bit level electronic circuit exports is 0000 ~ 1111, interval for the 1st:

Coding output is 0000, qp [15:0]=16 ' h0000, qn [15:0]=16 ' hffff, and electronic circuit exports and is:

$V_{\mathrm{outA}}=\frac{C_{1.1}+C_{1.2}+...+C_{1.16}}{{2C}_{x1}}-\frac{C_{2.1}+C_{2.2}+...+C_{2.16}}{{2C}_{x2}}+(V_{\mathrm{diff}1.0}+V_{\mathrm{diff}2.0}+...+V_{\mathrm{diff}16.0})---\left(7\right)$

Interval for the 2nd:

Coding output is 0001, qp [15:0]=16 ' h0001, qn [15:0]=16 ' hfffe, and electronic circuit exports and is:

$V_{\mathrm{outB}}=\frac{C_{1.1}+C_{1.2}+...+C_{1.16}}{{2C}_{x1}}-\frac{C_{2.1}+C_{2.2}+...+C_{2.16}}{{2C}_{x2}}+(V_{\mathrm{diff}1.0}+V_{\mathrm{diff}2.0}+...+V_{\mathrm{diff}15.0}+V_{\mathrm{diff}16.1})---\left(8\right)$

For the 3 to the 16 interval output class seemingly

Deduct formula (7) by formula (8) can obtain:

V _outB-V _outA＝V _diff16.1-V _diff16.0≈1 (9)

Can draw further in conjunction with above-mentioned analysis:

$V_{\mathrm{diff}16.1}-V_{\mathrm{diff}16.0}=(V_{\mathrm{refb}}-V_{\mathrm{reft}})\·(\frac{C_{1.16}}{{2C}_{x1}}+\frac{C_{2.16}}{{2C}_{x2}})---\left(10\right)$

In the ideal case, electric capacity C _1.16equal C _x1, C _2.16equal C _x2, the right and left of formula (9) is completely equal.During real work, due to the imperfect type C of device _1.16and C _x1, C _2.16and C _x2inconsistent, cause the output of sub-ADC to there is error.

Obtain the error amount at this comparison point place:

error＝(V _diff16.1-V _diff16.0)-1 (11)

After being compensated by this error amount, use the same method the error amount calculating and comparatively put than all the other in district.For the capacitor mismatch calibration of 1.5 bit-level circuit, also this technical scheme can be adopted.

According to the analysis of above-mentioned technical method, draw the digital calibration circuit of multistage many bits electronic circuit in described analog to digital converter, comprise: the 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, pulse-generating circuit, calibration value measuring circuit, data synthesis circuit, clock generation circuit, SPI register circuit and chip periphery control circuit.Wherein peripheral control circuits comprises, SPI control circuit, calibration control circuit and calibration value counting circuit.

Its concrete technical scheme is: in order to overcome the above problems the digital calibrating method and circuit that the invention provides multistage many bits electronic circuit in a kind of analog to digital converter.

A digital calibrating method for multistage many bits electronic circuit in analog to digital converter, is characterized in that:

The first step: first initialization of calibration control word in peripheral control circuits, in the effective situation of calibration enable signal, enter circulation, cycle-index is the number of the comparison point of electronic circuit; Peripheral control circuits sends forces interval code, makes the comparator in sub-MDAC be in corresponding operation interval; After analog circuit receives this code, obtain the output digital code of the current corresponding levels, digital calibration circuit receives the digital code of this grade, the Data Synthesis of the digital code of multistage electronic circuit is completed by data synthesis circuit, the numeral obtaining current ADC exports, completed the accumulating operation of current comparison point quantized value by calibration value measuring circuit according to the parameter value in SPI register circuit, and be stored in SPI register circuit; Peripheral control circuits reads this accumulated value, carries out error op and takes the mean, and obtains this and compares the calibration value pointed out, and is written in SPI register circuit by this calibration value, and the error amount then entering next comparison point calculates; After electronic circuit at the corresponding levels has been calibrated, error amount is compensated in the output of data synthesis circuit, carried out the calibration of next stage electronic circuit;

Second step: peripheral control circuits completes the Row control that calibrates for error of front 3 grades of electronic circuits according to the flow process described in the first step; First using 4th ~ m level electronic circuit as ideal circuit, its m >=4, calibration 3rd level, obtains the calibration value of 3rd level and compensates, then using 3 ~ m level electronic circuit as ideal circuit, calibrate the 2nd grade, obtain the calibration value of the 2nd grade and compensate, then using 2 ~ m level electronic circuit as ideal circuit, calibrating the 1st grade, obtain the calibration value post-compensation of the 1st grade, finally complete the calibration of whole circuit.

In analog to digital converter, a digital calibration circuit for multistage many bits electronic circuit, is characterized in that: comprise digital calibration circuit, SPI register circuit, peripheral control circuits; Digital calibration circuit, SPI register circuit, peripheral control circuits is arranged on chip periphery;

The input of described digital calibration circuit is the quantized value of analog circuit and the controlling value of SPI register circuit, and output is the output exporting accumulated value and the analog to digital converter after calibration without calibration;

Described peripheral control circuits calibrates flow process, the SPI register circuit read-write capability of calibration parameter for controlling;

Described SPI register circuit, for depositing the parameter needed for analog circuit and digital calibration circuit, stores the status signal of analog to digital converter internal circuit, for the operating state of the reading chip of peripheral control circuits and the calculating of calibration value at different levels.

Described digital calibration circuit comprises clock generation circuit, pulse-generating circuit, calibration value measuring circuit, the 1st grade of driving

Circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit;

Described clock generation circuit, for receiving the control signal of SPI register circuit, produces gated clock, paired pulses produces circuit, calibration value measuring circuit, the 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit provides controllable clock, for not in running order circuit, can close clock, make it be in resting state, reduce power consumption.

Described digital calibration the 1st stage drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for analog circuit the 1st grade of comparator circuit output according to the sequential needed for analog circuit;

Described digital calibration the 2nd stage drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for analog circuit the 2nd grade of comparator circuit output according to the sequential needed for analog circuit;

Described digital calibration 3rd level drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for the output of analog circuit 3rd level comparator circuit according to the sequential needed for analog circuit;

Described pulse-generating circuit: for receiving the control signal of SPI register circuit, the digital signal of the pulse width variability of generation, for the sequencing control of data synthesis circuit and the accumulation calculating of calibration value measuring circuit;

Described calibration value measuring circuit: for receiving the control signal of SPI register circuit, summation operation being carried out to the digital signal after Data Synthesis, result being kept at SPI register circuit.

Described data synthesis circuit: for sub-level circuit digital each in pipeline ADC is exported, after coding, carry out Data Synthesis according to time delay aligned array sequential and receive the calibration value in SPI register circuit, carry out compensation for calibrating errors, produce the output of final analog to digital converter.

Described peripheral control circuits comprises SPI configuration circuit, calibration flow process control circuit, calibration value counting circuit;

Described SPI configuration circuit, for configuring the running parameter of digital calibration circuit, the accumulated value reading digital calibration circuit generation is used for error calculation, configures and read the operating state of analog circuit the control signal needed for ADC internal analogue circuit;

Described calibration control circuit is used for the control of the align mode of carrying out adc circuit inside, the control code of respective bins is sent according to the sequential relationship needed for analog circuit, and the control that the circuit in each subinterval exports, in addition, also carry out the control of 3 calibration sub-level calibration flow processs.

Described calibration value counting circuit is that the accumulated value read according to SPI configuration circuit carries out doing difference operation, obtain the mean value of the error amount at each comparison point place, and each comparison point place error amount is deposited in SPI configuration circuit, for the compensation to adc circuit internal calibrators.

The calibration control flow of described calibration control circuit is: first initialization of calibration control word in peripheral control circuits, and in the effective situation of calibration enable signal, enter circulation, cycle-index is the number of the comparison point of electronic circuit; Peripheral control circuits sends forces interval code, makes the comparator in sub-MDAC be in corresponding operation interval; After analog circuit receives this code, obtain the output digital code of the current corresponding levels, digital calibration circuit receives the digital code of this grade, the Data Synthesis of the digital code of multistage electronic circuit is completed by data synthesis circuit, the numeral obtaining current ADC exports, completed the accumulating operation of current comparison point quantized value by calibration value measuring circuit according to the parameter value in SPI register circuit, and be stored in SPI register circuit; Peripheral control circuits reads this accumulated value, carries out error op and takes the mean, and obtains this and compares the calibration value pointed out, and is written in SPI register circuit by this calibration value, and the error amount then entering next comparison point calculates; After electronic circuit at the corresponding levels has been calibrated, error amount is compensated in the output of data synthesis circuit, carried out the calibration of next stage electronic circuit;

Peripheral control circuits completes the Row control that calibrates for error of front 3 grades of electronic circuits according to the flow process described in the first step; First using 4th ~ m level electronic circuit as ideal circuit, its m >=4, calibration 3rd level, obtains the calibration value of 3rd level and compensates, then using 3 ~ m level electronic circuit as ideal circuit, calibrate the 2nd grade, obtain the calibration value of the 2nd grade and compensate, then using 2 ~ m level electronic circuit as ideal circuit, calibrating the 1st grade, obtain the calibration value post-compensation of the 1st grade, finally complete the calibration of whole circuit.

Major advantage of the present invention is the Capacitor Mismatch Calibration proposing a kind of multistage many bits electronic circuit, and adopts digital circuit.Calibration control flow realizes outward at the sheet of analog to digital converter, and reduce the complexity of whole Design of A/D Converter, calibration steps is reliably easy, calibrates effective.

1, the Capacitor Mismatch Calibration of the sub-level ADC of a kind of multistage many bits is provided.

2, provide the calibration steps of a kind of outer error calculation, scale and the complexity of digital circuit in design can be decreased.

3, calibration circuit application can be designed in HIGH-SPEED HIGH-ACCURACY A/D CONVERTER, improve the dynamic property of chip.

4, new generation High Speed High Precision ADC chip or SOC on the basis of achievement of the present invention and experience, reduce the complexity of chip, and can improve the Performance And Reliability of product.

Accompanying drawing explanation

Fig. 1 is the system configuration schematic diagram of typical pipeline ADC

Fig. 2 is the transmission characteristic schematic diagram of 1.5 bit-level circuit.

Fig. 3 is the curve of output schematic diagram of inter-stage when there is error.

Fig. 4 is 3.5bit level electronic circuit structural representation.

Fig. 5 is the transmission characteristic signal of 3.5 bit-level circuit.

Fig. 6 is that digital calibration circuit realizes schematic diagram.

Register array schematic diagram is aimed in Fig. 7 time delay.

Fig. 8 is single-stage 3.5 bit electronic circuit calibration schematic flow sheet.

Fig. 9 is 3 grades of sub-pipelining-stage calibration schematic flow sheets.

Embodiment

Son is touched for vane type below for metal, and Structure Figure, the present invention is described in further detail.

The invention provides a kind of digital calibrating method of pipeline ADC of multistage many bit architecture, calibration flow process is: first, design peripheral control circuits, the operating state of control ADC, it is made to control needing the sub-pipelining-stage circuit calibrated, and exporting with error of each sub-level existed in the register of ADC inside is read, carry out error calculation, by the error amount calculated, be deposited in ADC internal register, the error compensation each sub-level calculated by Data Synthesis module, in last output, completes calibration.

The structure chart of this pipeline ADC shown in Fig. 1, in the present invention, N is 11.Wherein, k1 and k2 is 3.5 bit architecture, and k3 to k11 is 1.5 bit architecture.The 1st grade that the error effect that the present invention causes capacitance mismatch is larger, the 2nd grade, 3rd level is calibrated.

Figure 5 shows that the transmission curve of the 3.5bit of the 1st grade of electronic circuit and the 2nd grade of electronic circuit in the present invention.3.5 bit electronic circuit comparators export 17 kinds of output codes, 16 are respectively 0000 ~ 1111 and 1 negative value output c0 on the occasion of output c1 ~ c16 is 1111 (for preventing overflowing 1 Interval Coding increased), and corresponding is 17 output intervals and 16 comparison point with it.Owing to all there is the capacitance mismatch of comparator at each comparison point place, for the 1st comparison point, calibration circuit tries to achieve the accumulated value of y0 point and y1 point respectively, through asking difference operation to draw the 1st comparison point error amount error1, after this error amount is compensated, try to achieve the 2nd comparison point place error amount error2 again, in like manner obtain the error amount error3 ~ error16 at the 3 to 16 comparison point place.

As shown in Figure 6, the invention provides the digital calibration circuit of multistage many bits electronic circuit in a kind of analog to digital converter, its chip internal comprises digital calibration circuit, SPI register circuit; Chip periphery comprises peripheral control circuits.

The input of described digital calibration circuit is the quantized value of analog circuit and the controlling value of SPI register circuit, and output is the output without the accumulated value of calibration output and the analog to digital converter after calibration;

Described peripheral control circuits calibrates flow process, the SPI register circuit read-write capability of calibration parameter for controlling;

Described SPI register circuit, for depositing analog circuit and counting the parameter of depositing needed for calibration circuit, stores the status signal of analog to digital converter internal circuit, for the operating state of the reading chip of peripheral control circuits and the calculating of calibration value at different levels;

Described digital calibration circuit comprises clock generation circuit, pulse-generating circuit, calibration value measuring circuit, the 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit;

Described clock generation circuit, for receiving the control signal of SPI register circuit, produce gated clock, paired pulses produces circuit, calibration value measuring circuit, 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit provides controllable clock, for not in running order circuit, can clock be closed, make it be in resting state;

Described digital calibration the 1st stage drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for analog circuit the 1st grade of comparator circuit output according to the sequential needed for analog circuit;

Described digital calibration the 2nd stage drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for analog circuit the 2nd grade of comparator circuit output according to sequential needed for analog circuit;

Described digital calibration 3rd level drive circuit: for receiving the control signal of SPI register control circuit, produces the pressure control signal needed for the output of analog circuit 3rd level comparator circuit according to sequential needed for analog circuit;

Described pulse-generating circuit: for receiving the control signal of SPI register circuit, the digital signal of the pulse width variability of generation, for the sequencing control of data synthesis circuit and the accumulation calculating of calibration value measuring circuit;

Described calibration value measuring circuit: for receiving the control signal of SPI register circuit, summation operation being carried out to the digital signal after Data Synthesis, result being kept at SPI register circuit.

Described data synthesis circuit: for sub-level circuit digital each in pipeline ADC is exported by after coding circuit, Data Synthesis is carried out according to the time delay aligned array sequential in the present invention, and the calibration value received in SPI register circuit, carry out compensation for calibrating errors, produce the output of final analog to digital converter.Fig. 7 is the time delay alignment circuit of pipeline ADC of the present invention, wherein the 1st grade identical with the time delay of the 2nd grade of circuit, 3rd level and 1,2 grades one clock cycle of the 4th grade of delay control, 5th grade and 3,4 grades one clock cycle of the 6th grade of delay control, 7th grade and 5,6 grades one clock cycle of the 8th grade of delay control, 9th grade and 7,8 grades one clock cycle of the 10th grade of delay control, 9,10 grades one clock cycle of the 11st grade of delay control.The error amount of calculate 3 grades of circuit also compensates in this circuit by this data synthesis circuit, also carries out output gain adjustment according to the control signal of register control circuit.

Described peripheral control circuits comprises SPI configuration circuit, calibration flow process control circuit, calibration value counting circuit;

Described SPI configuration circuit, for configuring the running parameter of digital calibration circuit, the accumulated value reading digital calibration circuit generation is used for error calculation, configures and read the operating state of analog circuit the control signal needed for ADC internal analogue circuit;

Described calibration flow process control circuit, be used for the control of the align mode of carrying out adc circuit inside, for the flow process according to Fig. 8 and Fig. 9 in the present invention, the control code of respective bins is sent according to the sequential relationship needed for analog circuit, and the control that the circuit in each subinterval exports, in addition, the control of 3 calibration sub-level calibration flow processs is also carried out.

Described calibration value counting circuit is that the accumulated value read according to SPI configuration circuit carries out doing difference operation, obtain the mean value of the error amount at each comparison point place, and each comparison point place error amount is deposited in SPI configuration circuit, for the compensation to adc circuit internal calibrators.

Fig. 8 is single-stage 3.5 bit electronic circuit calibration flow process, first initialization of calibration control word in peripheral control circuits, and in the effective situation of calibration enable signal, enter circulation, cycle-index is the number of the comparison point of electronic circuit; Peripheral control circuits sends forces interval code, makes the comparator in sub-MDAC be in corresponding operation interval; After analog circuit receives this code, obtain the output digital code of the current corresponding levels, digital calibration circuit receives the digital code of this grade, the Data Synthesis of the digital code of multistage electronic circuit is completed by data synthesis circuit, the numeral obtaining current ADC exports, completed the accumulating operation of current comparison point quantized value by calibration value measuring circuit according to the parameter value in SPI register circuit, and be stored in SPI register circuit; Peripheral control circuits reads this accumulated value, carries out error op and takes the mean, and obtains this and compares the calibration value pointed out, and is written in SPI register circuit by this calibration value, and the error amount then entering next comparison point calculates; After electronic circuit at the corresponding levels has been calibrated, error amount is compensated in the output of data synthesis circuit, carried out the calibration of next stage electronic circuit;

Fig. 9 is the calibration flow process control of front 3 grades of electronic circuits, and peripheral control circuits completes the Row control that calibrates for error of front 3 grades of electronic circuits according to the flow process described in the first step; First using 4th ~ m level electronic circuit as ideal circuit, its m >=4, calibration 3rd level, obtains the calibration value of 3rd level and compensates, then using 3 ~ m level electronic circuit as ideal circuit, calibrate the 2nd grade, obtain the calibration value of the 2nd grade and compensate, then using 2 ~ m level electronic circuit as ideal circuit, calibrating the 1st grade, obtain the calibration value post-compensation of the 1st grade, finally complete the calibration of whole circuit.

The foregoing is only the preferred embodiments of the present invention, be not restricted to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within right of the present invention.

Claims (5)

1. the digital calibrating method of multistage many bits electronic circuit in analog to digital converter, is characterized in that:

The first step: first initialization of calibration control word in peripheral control circuits, in the effective situation of calibration enable signal, enter circulation, cycle-index is the number of the comparison point of electronic circuit; Peripheral control circuits sends forces interval code, makes the comparator in sub-MDAC be in corresponding operation interval; After analog circuit receives this code, obtain the output digital code of the current corresponding levels, digital calibration circuit receives the digital code of this grade, the Data Synthesis of the digital code of multistage electronic circuit is completed by data synthesis circuit, the numeral obtaining current ADC exports, completed the accumulating operation of current comparison point quantized value by calibration value measuring circuit according to the parameter value in SPI register circuit, and be stored in SPI register circuit; Peripheral control circuits reads this accumulated value, carries out error op and takes the mean, and obtains this and compares the calibration value pointed out, and is written in SPI register circuit by this calibration value, and the error amount then entering next comparison point calculates; After electronic circuit at the corresponding levels has been calibrated, error amount is compensated in the output of data synthesis circuit, carried out the calibration of next stage electronic circuit;

Second step: peripheral control circuits completes the Row control that calibrates for error of front 3 grades of electronic circuits according to the flow process described in the first step; First using 4th ~ m level electronic circuit as ideal circuit, its m >=4, calibration 3rd level, obtains the calibration value of 3rd level and compensates, then using 3 ~ m level electronic circuit as ideal circuit, calibrate the 2nd grade, obtain the calibration value of the 2nd grade and compensate, then using 2 ~ m level electronic circuit as ideal circuit, calibrating the 1st grade, obtain the calibration value post-compensation of the 1st grade, finally complete the calibration of whole circuit.

2. the digital calibration circuit of multistage many bits electronic circuit in analog to digital converter, is characterized in that: comprise digital calibration circuit, SPI register circuit, peripheral control circuits; Digital calibration circuit, SPI register circuit is arranged in chip, and peripheral control circuits is arranged on chip periphery;

The input of described digital calibration circuit is the quantized value of analog circuit and the controlling value of SPI register circuit, and output is without calibration, the output of the accumulated value of output and the analog to digital converter after calibration;

Described peripheral control circuits calibrates flow process, the SPI register circuit read-write capability of calibration parameter for controlling;

Described SPI register circuit, for depositing the parameter needed for analog circuit and digital calibration circuit, stores the status signal of analog to digital converter internal circuit, for the operating state of the reading chip of peripheral control circuits and the calculating of calibration value at different levels.

3. the digital calibration circuit of multistage many bits electronic circuit in the analog to digital converter according to right 1, it is characterized in that: described digital calibration circuit comprises clock generation circuit, pulse-generating circuit, calibration value measuring circuit, 1st stage drive circuit, 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit;

Described clock generation circuit, for receiving the control signal of SPI register circuit, produce gated clock, paired pulses produces circuit, calibration value measuring circuit, 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit provides controllable clock, for not in running order circuit, can clock be closed, make it be in resting state;

Described digital calibration the 1st stage drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for analog circuit the 1st grade of comparator circuit output according to the sequential needed for analog circuit;

Described digital calibration the 2nd stage drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for analog circuit the 2nd grade of comparator circuit output according to the sequential needed for analog circuit;

Described digital calibration 3rd level drive circuit: for receiving the control signal of SPI register circuit, produces the pressure control signal needed for the output of analog circuit 3rd level comparator circuit according to the sequential needed for analog circuit;

Described pulse-generating circuit: for receiving the control signal of SPI register control circuit, the digital signal of the pulse width variability of generation, for the sequencing control of data synthesis circuit and the accumulation calculating of calibration value measuring circuit;

Described calibration value measuring circuit: for the control signal of receiving register control circuit, carries out summation operation to the digital signal after Data Synthesis, result is kept at SPI register circuit;

Described data synthesis circuit: for sub-level circuit digital each in pipeline ADC is exported, after coding, carry out Data Synthesis according to time delay aligned array sequential, and receive the calibration value in SPI register circuit, carry out compensation for calibrating errors, produce the output of final analog to digital converter.

4. the digital calibration circuit of multistage many bits electronic circuit in analog to digital converter according to claim 1, is characterized in that: described peripheral control circuits comprises SPI configuration circuit, calibration flow process control circuit, calibration value counting circuit;

Described SPI configuration circuit, for configuring the running parameter of digital calibration circuit, the accumulated value reading digital calibration circuit generation is used for error calculation, configures and read the operating state of analog circuit the control signal needed for ADC internal analogue circuit;

Described calibration control circuit is used for the control of the align mode of carrying out adc circuit inside, the control code of respective bins is sent according to the sequential relationship needed for analog circuit, and the control that the circuit in each subinterval exports, in addition, also carry out the control of 3 calibration sub-level calibration flow processs.

Described calibration value counting circuit is that the accumulated value read according to SPI configuration circuit carries out doing difference operation, obtain the mean value of the error amount at each comparison point place, and each comparison point place error amount is deposited in SPI configuration circuit, for the compensation to adc circuit internal calibrators.

5. the digital calibration circuit of multistage many bits electronic circuit in analog to digital converter according to claim 3, it is characterized in that: the calibration control flow of described calibration control circuit is: first initialization of calibration control word in peripheral control circuits, in the effective situation of calibration enable signal, enter circulation, cycle-index is the number of the comparison point of electronic circuit; Peripheral control circuits sends forces interval code, makes the comparator in sub-MDAC be in corresponding operation interval; After analog circuit receives this code, obtain the output digital code of the current corresponding levels, digital calibration circuit receives the digital code of this grade, the Data Synthesis of the digital code of multistage electronic circuit is completed by data synthesis circuit, the numeral obtaining current ADC exports, completed the accumulating operation of current comparison point quantized value by calibration value measuring circuit according to the parameter value in SPI register circuit, and be stored in SPI register circuit; Peripheral control circuits reads this accumulated value, carries out error op and takes the mean, and obtains this and compares the calibration value pointed out, and is written in SPI register circuit by this calibration value, and the error amount then entering next comparison point calculates; After electronic circuit at the corresponding levels has been calibrated, error amount is compensated in the output of data synthesis circuit, carried out the calibration of next stage electronic circuit;

Peripheral control circuits completes the Row control that calibrates for error of front 3 grades of electronic circuits according to the flow process described in the first step; First using 4th ~ m level electronic circuit as ideal circuit, its m >=4, calibration 3rd level, obtains the calibration value of 3rd level and compensates, then using 3 ~ m level electronic circuit as ideal circuit, calibrate the 2nd grade, obtain the calibration value of the 2nd grade and compensate, then using 2 ~ m level electronic circuit as ideal circuit, calibrating the 1st grade, obtain the calibration value post-compensation of the 1st grade, finally complete the calibration of whole circuit.