CN104699656A - FPGA (field programmable gate array)-based microprocessor PUF (physically unclonable function) implementing system and FPGA-based microprocessor PUF implementing method - Google Patents

Abstract

The invention discloses an FPGA (field programmable gate array)-based microprocessor PUF (physically unclonable function) implementing system and an FPGA-based microprocessor PUF implementing method. The FPGA-based microprocessor PUF implementing system comprises a PUF character acquiring module and a data stream generating module. The FPGA-based microprocessor PUF implementing method includes that an ALU (arithmetic logic unit) functional module is established on an FPGA platform, arithmetic data of the ALU functional module are collected under a high-frequency clock condition and random time delay on an FPGA array is extracted to serve as a label of a physical entity. The FPGA-based microprocessor PUF implementing system and the FPGA-based microprocessor PUF implementing method have the advantages that the defects that instruction sets and clock module circuits suitable for different types of microprocessor chips need to be configured in an existing scheme are overcome and resource consumption is reduced since the specialized ALU module is only established on the FPGA platform, and thereby being capable of supplementing an existing microprocessor PUF implementing scheme beneficially.

Description

A kind of microprocessor PUF based on FPGA realizes system and method thereof

Technical field

The present invention relates to the anti-clone's security technology area of physics, particularly relate to a kind of microprocessor PUF based on FPGA and realize system and method thereof.

Background technology

The ultimate principle of microprocessor PUF utilizes the propagation delay time on microprocessor data transmission line and order control line to change difference to realize the anti-clone's function of physics.Due to the random difference in manufacture process, the propagation delay time T of particular path on every block microprocessor chip _pathall different.When microprocessor is in operational process, along with the lifting of clock frequency, the clock period reduces, if the clock period is less than propagation delay time T _path, instruction performs will be failed.Research shows that this error status has between a zone of transition, on the Frequency point namely in this interval, along with the rising of frequency, repeats an instruction repeatedly, and its instruction performs correct number of times and presents a curve declined.For a certain specific data routing on different microprocessor chip or controllability path, due to propagation delay time T _pathdifferent, the decline curve that when therefore microprocessor performs a certain same instructions, its instruction performs corresponding to correct number of times is not identical, and namely microprocessor presents different serviceabilitys under overclocking duty.Therefore by certain quantizing rule, we can convert microprocessor to bit string output, in this, as the identity information of this chip by the working performance curve performed corresponding to certain instruction.

The instruction set supported due to the microprocessor chip of different manufacturers or different model is different different with hardware parameter, need the clock module circuit configuring this system suitable, apply the instruction set be consistent with hardware configuration, this makes test code not possess good portability.Meanwhile, microprocessor chip function is fairly perfect, if only just obviously can cause the waste of resource as the function that a label realizes PUF with it.For this reason, on the basis of using for reference microprocessor PUF know-why, we have proposed the microprocessor PUF implementation method based on FPGA, form a special circuit module, realize PUF function to meet the application of multiple occasion with less cost.

Summary of the invention

Goal of the invention: for problems of the prior art, the invention provides that a kind of resource cost cost is very little and the microprocessor PUF based on FPGA with general applicability realizes system and method thereof.

Technical scheme: the present invention proposes a kind of microprocessor PUF based on FPGA and realizes system, comprise PUF characteristic acquisition module and data stream generation module, wherein PUF characteristic acquisition module comprises central control unit, clock adjustment unit, ALU unit, serial communication unit, and data stream generation module comprises decision unit and post-processing unit; The output terminal of central control unit is connected with the input end of clock adjustment unit, ALU unit and serial communication unit respectively, is responsible for the operation of program on control FPGA development board, ensures in concert with work between unit; The output terminal of clock adjustment unit is connected with the input end of central control unit and ALU unit respectively, is responsible for producing the system clock of PUF feature extraction module and the overclocking clock of ALU unit, and can adjust in real time it; The output terminal of ALU unit is connected with the input end of serial communication unit, and this unit runs under high frequency clock drives, and its operation result reflects the time-delay characteristics of transmission line on FPGA development board; The output terminal of serial communication unit is connected with decision unit input end, is responsible for PUF characteristic acquisition module and communicating between data stream generation module; The output terminal of decision unit is connected with post-processing unit input end, is responsible for the data receiving the transmission of PUF characteristic acquisition module, and converts binary data to by decision mechanism; Post-processing unit is responsible for generating m sequence by receiving the binary data transmitted with decision unit by linear shift register, and exports fixed length binary responses.

Described clock adjustment unit produces 30 clock frequency points, to cover the frequency transition territory of different PUF physical entity error status in PUF entity set, is specially from 400MHz to 545MHz, interval 5MHz.

Described ALU unit comprises additive operation unit, multiplying unit and division arithmetic unit, also reduces resource cost while simplifying circuit structure.

The present invention also proposes a kind of microprocessor PUF implementation method based on FPGA, and comprise PUF performance data acquisition method and PUF physical entity label generating method, wherein PUF performance data acquisition method comprises the steps:

(1) internal register of initialization PUF performance data acquisition module: Frequency point counter, wheel counter, wheel indegree counter and the instruction of each ALU arithmetic element are performed correct number counter and is initialized as 0;

(2) adjust frequency: according to ongoing frequency Counter Value, corresponding frequency division Clock Multiplier Factor is set, the real-time adjustment of line frequency of going forward side by side;

(3) ALU module is run: after frequency has adjusted, each ALU arithmetic element is run 6 and is taken turns under current clock frequency drives, often take turns 40 times, add up each to take turns instruction and perform correct number of times, if 6 take turns statistics in the error range preset, using this 6 statisticss summation as the PUF performance data of this PUF physical entity at this Frequency point, proceed to step (4), otherwise these 6 statisticss are abandoned, counter will be taken turns, wheel indegree counter, the instruction of each ALU arithmetic element performs correct number counter and all recovers initial value, rerun step (3),

(4) data are transmitted: the PUF performance data of this PUF physical entity on a certain Frequency point collected in step (3) sent to data stream generation module for follow-up data process, and judge whether data acquisition terminates according to current operation frequency point, if Frequency point counter has been counted to 29, terminate, otherwise frequency counter adds 1, and jump to step (2) continuation operation.

PUF physical entity label generates and comprises the steps:

(1) generate binary data string by decision mechanism: receive each Frequency point statistics that PUF characteristic acquisition module sends, and generate the fixed length binary data string of 3 string 60 according to following decision rule:

$r=\left\{\begin{array}{ccc}00& \mathrm{if}& \mathrm{pc}/k\&le;0.1\\ 01& \mathrm{if}& 0.1<\mathrm{pc}/k\&le;0.5\\ 10& \mathrm{if}& 0.5<\mathrm{pc}/k\&le;0.9\\ 11& \mathrm{if}& \mathrm{pc}/k>0.1\end{array}\right.---\left(1\right)$

Wherein, to be the number of times that altogether runs and k=240, pc be k performs the statistics of each Frequency point that correct number of times and PUF characteristic acquisition module transmit.

(2) Data Post is carried out: the initial value using the binary data string of the fixed length 60 of 3 arithmetic element generations in step (1) as 3 progression being the linear shift register of 60, connects polynomial expression each self-generating m sequence according to following:

f(x)＝x ⁶⁰+x+1 (2)

Wherein, x ⁶⁰, x, 1 current state representing the 60th grade, the 1st grade and the 0th grade register in shift-register sequence respectively, f (x) then represents the output valve of m sequence under current state, i.e. the XOR value of the 60th grade, the 1st grade and the 0th grade register current state.

(3) export PUF physical entity label: according to the sequence length n of required output, the 1st of the m sequence generated from step (2), select progressively length is the sequence string c of n ₁, c _2,c ₃, calculate output sequence s=c ₁+ c ₂+ c ₃(each sequence pair answers position mould two to be added), the fixed length obtained for identifying PUF physical entity is the bit string of n.

Beneficial effect: the present invention adopts technique scheme, has following beneficial effect:

1, the present invention effectively overcomes existing scheme needs to determine the starting point in its frequency transition territory and the defect of cut off for each microprocessor chip, overcome the defect that it needs to write for different microprocessor chips response test code, and resource is fewer on the FPGA plate expended, having general applicability, is a beneficial complement to existing microprocessor PUF implementation.

2, raw 30 the clock frequency points of clock adjustment unit common property in the present invention, can cover the frequency transition territory of different PUF physical entity error status in PUF entity set.

3, in the present invention, ALU unit builds the arithmetic element module realizing the functions such as addition, multiplication, division respectively, also reduces resource cost while simplifying circuit structure.

4, the binary data string that in the present invention, decision unit generates by post-processing unit does further process, makes to generate the fixed length binary sequence of random length and has Hamming distance between good sheet between different sequence.

Accompanying drawing explanation

Fig. 1 is the system construction drawing of the embodiment of the present invention;

Fig. 2 is the PUF characteristic acquisition method process flow diagram of the embodiment of the present invention;

Fig. 3 is the PUF physical entity label generating method process flow diagram of the embodiment of the present invention.

Embodiment

Below in conjunction with specific embodiment, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, those skilled in the art have all fallen within the application's claim limited range to various equivalents of the present invention.

The present embodiment selects the hardware implementing platform using the XC6SLX16-2CSG324 FPGA Siga-S16 development board that is core processor as scheme designed by us in the Spartan6 series of Xilinx, and the hardware resource of development board is as follows:

FPGA:XC6SLX16-2CSG324 Spartan-6 series@Xilinx

FPGA configures: 8MB SPI Flash@Numonyx

Memory: plate carries 128MB DDR2 SDRAM@Micron

8MB SPI Flash@Numonyx

Interface resource: USB2.0 high-speed communication, CY68013@Cypress;

USB turns UART communication, CP2102@Silicon Labs;

DB9 formula RS232 interface (female mouth);

10/100M Ethernet RJ-45 interface, adopts chip RTL8201@Realtek etc.

Clock: plate carries 50MHz oscillator

Control and display: 4 buttons

2 road toggle switchs

4 LED

Power supply: 5V/2A power supply adaptor

DDR2 power solution@TI

FPGA power solution@MPS

Microprocessor PUF based on FPGA realizes system as shown in Figure 1, comprise two modules: (1) PUF characteristic acquisition module is based on the principle of microprocessor PUF, utilize the random delay difference due to manufacturing process generation on fpga logic array, collect the PUF performance data presented when every block FPGA development board ALU module under high frequency state performs response computing, this functional module adopts design and the input of hardware description language (Verilog HDL) realizing circuit on FPGA; (2) the PUF performance data received is carried out after statistical treatment by certain generate rule bit string by data stream generation module, and using this string data as the label identifying this physical entity, this functional module has been held at PC, reduce the calculated amount of PUF feature extraction module on the one hand, to meet the lightweight attribute of PUF label, hold at PC the computing and process that more easily complete batch data on the other hand.

PUF characteristic acquisition module comprises central control unit, clock frequency adjustment unit, ALU unit and serial communication unit, and wherein the operation of program on control FPGA development board is responsible for by central control unit, ensures in concert with work between unit; Clock adjustment unit is responsible for producing the system clock of PUF feature extraction module and the overclocking clock of ALU unit, and can adjust in real time it; ALU unit comprise add, multiplication and division three arithmetic elements, this unit high frequency clock drive under run, its operation result reflects the time-delay characteristics on FPGA development board on some transmission line; Serial communication unit is responsible for PUF characteristic acquisition module and communicating between data stream generation module, the statistics of ALU module is transferred to PC end, PC sort command is sent to FPGA development board simultaneously.

Data stream generation module comprises decision unit and post-processing unit, wherein

The data that decision unit is responsible for PUF characteristic acquisition module exports convert binary data to by certain decision mechanism;

The binary data that post-processing unit is responsible for decision unit to export generates m sequence by linear shift register, and exports fixed length binary responses.

The groundwork of PUF feature extraction module is by collecting the running status of ALU functional module at different frequency point to extract the PUF characteristic of propagation delay time in FPGA, namely extracting the FFP point set corresponding to every block fpga chip.For this reason, we have selected 30 clock frequency points, to cover the frequency transition territory of different physical entity error status, be specially from 400MHz to 545MHz, interval 5MHz, and the ALU calculation function module selecting addition, multiplication and division three kinds different guarantees to distinguish different physical entities, on each Frequency point, test is for 40 times take turns statistic processes in addition, statistics wherein runs correct number of times, as the pc value of this Frequency point.In order to improve the stability of fetched data, reduce randomness, we carry out 6 altogether at each Frequency point and take turns statistic processes, and 6 of statistics take turns data be only just considered to effective in certain error ranges, otherwise these data are rejected, restart statistic processes, until after acquisition valid data, sued for peace as this Frequency point statistical value and by serial ports sending module be sent to PC end, facilitate follow-up data processing and the generation of binary data stream, therefore the flow process of PUF performance data module acquires PUF performance data is as shown in Figure 2:

(1) internal register of initialization PUF performance data acquisition module, in order to record the running status of ALU functional module at different frequency point, the starting stage is run in program, by Frequency point counter, wheel counter, wheel indegree counter and the instruction of each ALU unit perform correct number counter and are initialized as 0.

(2) adjust frequency: corresponding frequency division Clock Multiplier Factor is set according to ongoing frequency Counter Value and goes forward side by side the real-time adjustment of line frequency, 30 Frequency points are had in the present embodiment, Frequency point counter counts from 0, when count to 29 time show that the data acquisition of PUF characteristic acquisition module completes.

(3) ALU module is run: after frequency has adjusted, each ALU functional module brings into operation under current clock frequency drives, operation result and theoretical value compare each time, if equal, instruction performs correct number counter and adds 1, by wheel counter and the number of run of taking turns indegree counter controls ALU functional module, run 6 at each Frequency point to take turns, often take turns operation 40 times, add up each to take turns instruction and perform correct number of times, if 6 take turns statistics in certain error range, then sued for peace as the PUF performance data of PUF entity at this Frequency point, proceed to step (4).If 6 to take turns statistics application condition large, then statistics abandoned, by respectively taking turns counter, wheel indegree counter, the instruction of each ALU unit perform correct number counter and all recover initial value, reruns step (3).

(4) transmit data: the PUF performance data of this PUF physical entity on a certain Frequency point collected in step (3) is sent to data stream generation module, carry out data processing for follow-up.And judge whether data acquisition terminates according to current operation frequency point, if Frequency point counter has been counted to 29, terminate PUF performance data gatherer process, otherwise frequency counter adds 1, and jumped to step (2) continuation operation.

Data stream generation module generates the flow process of this PUF physical entity label of identification as shown in Figure 3:

(1) PUF performance data is received, and generating binary string by decision mechanism: each Frequency point statistics sent by PUF characteristic acquisition module generates bit string according to certain decision rule, because PUF characteristic acquisition module has added up the performance data of 3 ALU arithmetic elements at 30 Frequency points, each data can convert 2 bit binary data to, therefore can obtain the fixed length binary data string of 3 string 60 by following decision mechanism:

$r=\left\{\begin{array}{ccc}00& \mathrm{if}& \mathrm{pc}/k\&le;0.1\\ 01& \mathrm{if}& 0.1<\mathrm{pc}/k\&le;0.5\\ 10& \mathrm{if}& 0.5<\mathrm{pc}/k\&le;0.9\\ 11& \mathrm{if}& \mathrm{pc}/k>0.1\end{array}\right.---\left(1\right)$

Wherein, to be the number of times that altogether runs and k=240, pc be k performs the statistics of each Frequency point that correct number of times and PUF characteristic acquisition module transmit.

(2) Data Post: the initial value using the binary data string of the fixed length 60 of 3 arithmetic element generations in step (1) as 3 progression being the linear shift register of 60, according to connection polynomial f (x)=x ⁶⁰+ x+1 each self-generating m sequence, wherein an x ⁶⁰, x, 1 current state representing the 60th grade, the 1st grade and the 0th grade register in shift-register sequence respectively, f (x) then represents the sequence output valve under current state, i.e. the XOR value of the 60th grade, the 1st grade and the 0th grade register current state.

(3) export fixed length binary data string: according to the sequence length n of required output, the 1st of the m sequence generated from step (2), select progressively length is the sequence string c of n ₁, c _2,c ₃, calculate output sequence s=c ₁+ c ₂+ c ₃(each sequence pair answers position mould two to be added), namely obtaining the last fixed length exported is the bit string of n.

Microprocessor PUF design proposal based on FPGA adopts Veriog HDL programming language to describe completely, and synthesis tool automatic Synthesis can be used, by placement-and-routing's instrument process, without the need to manual intervention, convenient and swift, make circuit design cycle greatly shorten, this programme PUF characteristic acquisition module on FPGA development board through compiling and comprehensive after to take the situation of development board resource as shown in table 1, can find out that to take resource fewer.

Table 1

The uniqueness of the anti-clone's function of physics is embodied by the mean value calculating Hamming distance between sheet usually, and specific formula for calculation is:

$u_p^{\mathrm{inter}}=\frac{2}{m(m-1)}\underset{i=1}{\overset{m-1}{\mathrm{\&Sigma;}}}\underset{j=i+1}{\overset{m}{\mathrm{\&Sigma;}}}\frac{\mathrm{HD}(R_i,R_j)}{n}\&times;100\%---\left(3\right)$

Wherein, R _i, R _jrefer to two different PUF entity i, the response that j exports, m refers to the sum of different PUF entities, and n is the length exporting response.

We select m=5, n=128, and 256, test the uniqueness of the binary sequence that the PUF entity set of 5 pieces of FPGA development board compositions generates when 512, test result is as shown in table 2, can find out that its uniqueness characteristic is close to ideal value 50%, meets re-set target.

Table 2

Length	n＝128	n＝256	n＝512	Average
					Uniqueness	45.63％	47.81％	48.54％	47.33％

Claims (4)

1. one kind realizes system based on the microprocessor PUF of FPGA, it is characterized in that, comprise PUF characteristic acquisition module and data stream generation module, wherein PUF characteristic acquisition module comprises central control unit, clock adjustment unit, ALU unit, serial communication unit, and data stream generation module comprises decision unit and post-processing unit; The output terminal of central control unit is connected with the input end of clock adjustment unit, ALU unit and serial communication unit respectively, is responsible for the operation of program on control FPGA development board, ensures in concert with work between unit; The output terminal of clock adjustment unit is connected with the input end of central control unit and ALU unit respectively, is responsible for producing the system clock of PUF feature extraction module and the overclocking clock of ALU unit, and can adjust in real time it; The output terminal of ALU unit is connected with the input end of serial communication unit, and this unit runs under high frequency clock drives, and its operation result reflects the time-delay characteristics of transmission line on FPGA development board; The output terminal of serial communication unit is connected with decision unit input end, is responsible for PUF characteristic acquisition module and communicating between data stream generation module; The output terminal of decision unit is connected with post-processing unit input end, is responsible for the data receiving the transmission of PUF characteristic acquisition module, and converts binary data to by decision mechanism; Post-processing unit is responsible for generating m sequence by receiving the binary data transmitted with decision unit by linear shift register, and exports fixed length binary responses.

2. realize system based on the microprocessor PUF of FPGA as claimed in claim 1, it is characterized in that, described clock adjustment unit produces 30 clock frequency points, from 400MHz to 545MHz, and interval 5MHz.

3. realize system based on the microprocessor PUF of FPGA as claimed in claim 1, it is characterized in that, described ALU unit comprises additive operation unit, multiplying unit and division arithmetic unit.

4. based on a microprocessor PUF implementation method of FPGA, it is characterized in that, comprise PUF performance data acquisition method and PUF physical entity label generating method, wherein PUF performance data acquisition method comprises the steps:

(1) internal register of initialization PUF performance data acquisition module: Frequency point counter, wheel counter, wheel indegree counter and the instruction of each ALU arithmetic element are performed correct number counter and is initialized as 0;

(2) adjust frequency: according to ongoing frequency Counter Value, corresponding frequency division Clock Multiplier Factor is set, the real-time adjustment of line frequency of going forward side by side;

(3) ALU module is run: after frequency has adjusted, each ALU arithmetic element is run 6 and is taken turns under current clock frequency drives, often take turns 40 times, add up each to take turns instruction and perform correct number of times, if 6 take turns statistics in the error range preset, using this 6 statisticss summation as the PUF performance data of this PUF physical entity at this Frequency point, proceed to step (4), otherwise these 6 statisticss are abandoned, counter will be taken turns, wheel indegree counter, the instruction of each ALU arithmetic element performs correct number counter and all recovers initial value, rerun step (3),

(4) data are transmitted: the PUF performance data of this PUF physical entity on a certain Frequency point collected in step (3) sent to data stream generation module for follow-up data process, and judge whether data acquisition terminates according to current operation frequency point, if Frequency point counter has been counted to 29, terminate, otherwise frequency counter adds 1, and jump to step (2) continuation operation;

PUF physical entity label generates and comprises the steps:

(1) generate binary data string by decision mechanism: receive each Frequency point statistics that PUF characteristic acquisition module sends, and generate the fixed length binary data string of 3 string 60 according to following decision rule:

$r=\left\{\begin{array}{ccc}00& \mathrm{if}& \mathrm{pc}/k\&le;0.1\\ 01& \mathrm{if}& 0.1<\mathrm{pc}/k\&le;0.5\\ 10& \mathrm{if}& 0.5<\mathrm{pc}/k\&le;0.9\\ 11& \mathrm{if}& \mathrm{pc}/k>0.1\end{array}\right.---\left(1\right)$

Wherein, to be the number of times that altogether runs and k=240, pc be k performs the statistics of each Frequency point that correct number of times and PUF characteristic acquisition module transmit;

(2) Data Post is carried out: the initial value using the binary data string of the fixed length 60 of 3 arithmetic element generations in step (1) as 3 progression being the linear shift register of 60, connects polynomial expression each self-generating m sequence according to following:

f(x)＝x ⁶⁰+x+1 (2)

Wherein, x ⁶⁰, x, 1 current state representing the 60th grade, the 1st grade and the 0th grade register in shift-register sequence respectively, f (x) then represents the output valve of m sequence under current state, i.e. the XOR value of the 60th grade, the 1st grade and the 0th grade register current state;

(3) export PUF physical entity label: according to the sequence length n of required output, the 1st of the m sequence generated from step (2), select progressively length is the sequence string c of n ₁, c _2,c ₃, calculate output sequence s=c ₁+ c ₂+ c ₃(each sequence pair answers position mould two to be added), the fixed length obtained for identifying PUF physical entity is the bit string of n.