CN102313604B - Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) - Google Patents
Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) Download PDFInfo
- Publication number
- CN102313604B CN102313604B CN201110194051.9A CN201110194051A CN102313604B CN 102313604 B CN102313604 B CN 102313604B CN 201110194051 A CN201110194051 A CN 201110194051A CN 102313604 B CN102313604 B CN 102313604B
- Authority
- CN
- China
- Prior art keywords
- fpga
- module
- circuit
- cpld
- photon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000003044 adaptive effect Effects 0.000 title abstract description 10
- 230000001360 synchronised effect Effects 0.000 claims abstract description 21
- 238000012544 monitoring process Methods 0.000 claims description 19
- 238000012795 verification Methods 0.000 claims description 8
- 238000004422 calculation algorithm Methods 0.000 claims description 5
- 238000012937 correction Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 2
- 238000005314 correlation function Methods 0.000 abstract description 7
- 238000005070 sampling Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 9
- 239000002105 nanoparticle Substances 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 5
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000001186 cumulative effect Effects 0.000 description 3
- 238000002296 dynamic light scattering Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 101100459912 Caenorhabditis elegans ncs-1 gene Proteins 0.000 description 2
- 101100293720 Caenorhabditis elegans ncs-2 gene Proteins 0.000 description 2
- 101000885387 Homo sapiens Serine/threonine-protein kinase DCLK2 Proteins 0.000 description 2
- 102100039775 Serine/threonine-protein kinase DCLK2 Human genes 0.000 description 2
- 238000005311 autocorrelation function Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 235000019580 granularity Nutrition 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 101000885383 Homo sapiens Serine/threonine-protein kinase DCLK3 Proteins 0.000 description 1
- 102100039774 Serine/threonine-protein kinase DCLK3 Human genes 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
- Optical Communication System (AREA)
Abstract
The invention relates to an adaptive photon correlator on the basis of a CPLD (Complex Programmable Logic Device) and an FPGA (Field Programmable Gate Array), which mainly comprises an FPGA chip circuit, an FPGA clock, reset and reconfiguration circuit, a serial port and USB (Universal Serial Bus) circuit and an encrypting circuit, wherein the FPGA chip circuit is used for realizing a plurality of independent digital correlators; the FPGA clock, reset and reconfiguration circuit is used for realizing driving and synchronous reset of each circuit module in the FPGA and driving of reconfiguration of each circuit module in the FPGA; the serial port and USB circuit is used for realizing communication between the FPGA and a computer and between the CPLD and the computer; and the encrypting circuit is used for encrypting a program configurated on an FPGA chip. For the adaptive photon correlator on the basis of the CPLD and the FPGA, which is disclosed by the invention, a mode that a plurality of configuration chips dynamically selects to configurate one FPGA by the CPLD is adopted, the adaptive dynamical regulation of a configuration scheme of the photon correlator is realized and an obtained correlation function is optimized.
Description
Technical field
The present invention relates to obtain the device of scattered light intensity signal correction function, specifically the self-adaptation photon correlator based on CPLD (being called for short CPLD, lower same) and field programmable gate array (being called for short FPGA, lower same).
Background technology
At present, in photon correlation spectroscopy technology, obtain the device of scattered light intensity signal auto-correlation function and cross correlation function, mainly contain the TurboCorr of Brookhaven Instruments Corporation, the Series correlation devices such as FLEX02 that provide on the German ALV ALV-6000 of company, ALV-7000 series digit correlator and U.S. www.correlator.com website.
Above-mentioned correlator is the chip based on custom-made mostly, or based on dsp chip, expensive.
Summary of the invention
The object of the invention is to the defect existing for prior art, provide a kind of and (be called for short CPLD based on CPLD, lower same) and field programmable gate array (abbreviation FPGA, self-adaptation photon correlator down together), hardware for photon correlation spectroscopy technology light intensity signal related function is realized, it is according to the related function of the default configuration getting, adjust adaptively sampling time, related operation time, postpone channel allocation scheme, finally obtain optimized related function.
CPLD is based on EEPROM technique, after the write-in program of the inside of chip, after system powers on, can work reliably, there is no the loading procedure of configuration data, the Main Function of CPLD is exactly to realize the pin of multiple FPGA configuring chip and the dynamic interconnection of FPGA configuration pin in the present invention.By being stored in the program in CPLD, make multiple FPGA configuring chip and FPGA under the control of CPLD, complete Dynamic Selection configuration.
FPGA be a kind of can be according to a kind of general-purpose chip of application scenario flexible configuration resource, and the large multi-embedding digital operation module that has, is applicable to related operation.FPGA, based on SRAM technique, arranges its duty by the program leaving in on-chip SRAM, and during configuration, fpga chip reads in the data in configuring chip in on-chip SRAM, and after having configured, FPGA enters duty.This characteristic of FPGA makes it easy to dynamic flexible and is configured.A slice FPGA can realize several functions easily by various configurations scheme.
As scheme as shown in l, 2, of the present invention a kind of based on CPLD (Complex Programmable Logic Device, CPLD) and the self-adaptation photon correlator of FPGA (Field Programmable Gate Array, field programmable gate array) mainly comprise:
---fpga chip circuit, realize a plurality of separate digital correlators;
---FPGA clock, reset, reshuffle circuit, realize the driving of each circuit module in FPGA, synchronous reset, the driving reconfiguring;
---serial ports and USB circuit, realize FPGA, CPLD and compunication;
---encrypted circuit, for encryption configuration to the program on fpga chip;
CPLD and multiple FPGA configuring chip circuit, utilize CPLD that the various configurations Scheme Choice ground being stored on multi-disc configuring chip is dynamically configured on fpga chip;
---CPLD clock, reset circuit, realize the driving of each circuit module of CPLD, reset;
---synchronous reset module, be solidificated in FPGA, complete after hardware powers on or FPGA reset key press after the synchronous reset of each module and the loading of acquiescence initial value in fpga chip;
---photon counting module, be solidificated in FPGA, for adding up the number of photon in certain hour interval, and latch output, send into related operation module;
---related operation module, be solidificated in FPGA, the data of photon counting module output are carried out to auto-correlation computation or computing cross-correlation, obtain autocorrelator trace or simple crosscorrelation curve, and latch output, pass through Computer Interface Module, with compunication, realize the output of data;
---Computer Interface Module, be solidificated in FPGA, by serial ports and USB circuit interface and compunication, realize the setting of correlator parameter and auto-correlation computation or the output of computing cross-correlation result data;
---encrypting module, be solidificated in FPGA, complete being configured to the encryption of FPGA Program;
---CPLD reseting module, be solidificated in CPLD, complete after hardware powers on or CPLD reset key press after the reset of each module and the loading of acquiescence initial value in CPLD chip;
---instruction monitoring module, be solidificated in CPLD, for monitoring by serial ports and USB circuit interface, the allocation plan selection instruction of being sent by computer software;
---dynamic-configuration module, be solidificated in CPLD, for dynamically interconnecting storing configuring chip pin and the FPGA configuration pin that instruction chooses allocation plan, and drive FPGA to reconfigure, complete the Dynamic Selection configuration to FPGA.
Preferred version is as follows: described fpga chip main circuit will consist of a slice fpga chip circuit; Described FPGA clock, reset, reshuffle main circuit and will be formed by Block1 circuit.
Described serial ports and USB main circuit will consist of UART & USB circuit; Described encrypted circuit mainly consists of DS28E01 chip circuit.
Described CPLD and multiple FPGA configuring chip main circuit will consist of piece of CPLD chip circuit and multiple FPGA configuring chip circuit; Described CPLD clock, reset circuit mainly consist of Block2 circuit.
Described synchronous reset module mainly comprises the output module of input, external reset signal input and the synchronous reset signal of 50M length of a game.
Described photon counting module mainly comprises the load module of the input Yu50M length of a game of iSampleWord parameter.
Described related operation module mainly consists of shift register and parallel multiplication, optionally realizes auto-correlation computation and computing cross-correlation; Described Computer Interface Module mainly consists of receiving element RxdAll and transmitting element TXDControl.
Described encrypting module is mainly by random 8 figure place generation module RNG_8Bits, and hash algorithm calculates and result correction verification module small_micro_32 and these 3 module compositions of external encryption circuit interface module One_Wire.
Described CPLD reseting module mainly comprises the output module of input, external reset signal input and the CPLD reset signal of 50M time.
Described instruction monitoring module mainly consists of serial ports receiving element RxdAll and allocation plan preset value; Described dynamic-configuration module mainly consists of All circuit.
Principle of work of the present invention is as follows:
System chart of the present invention, as Fig. 1, from photon detector (such as photomultiplier, avalanche photodide etc.) pulse signal out, enters the photon counting module in FPGA.Photon counting module, by default sampling time interval, is carried out equally spaced counting to photon pulse signal, and count results is sent into related operation module.First related operation module sends data into shift register, and according to the channel allocation scheme of setting, start parallel multiplication and carry out computing, complete the related operation of appointment after the time, this result is sent into Computer Interface Module, Computer Interface Module is sent result into computing machine, completes related operation process one time.
As Fig. 1, multi-disc configuring chip is stored respectively different allocation plans, utilize CPLD can change places and make a slice fpga chip realize multiple different related operation in the different moment in conjunction with the software on computing machine, reach the effect of " one-machine-multi-function ", improve function and the performance of photon correlator.The allocation plan selection instruction of being sent by the software on computing machine, by serial ports and USB circuit interface, sends into the instruction monitoring module in CPLD.Instruction monitoring module carries out identification decision to instruction, to determine, that allocation plan is configured in FPGA, and result of determination is sent into dynamic-configuration module.Dynamic-configuration module, according to the result of judging, is chosen the configuring chip pin of allocation plan and FPGA configuration pin dynamically to interconnect by storing, and is driven FPGA to reconfigure, and completes the Dynamic Selection configuration to FPGA.After having configured, the program encryption module in configurator is carried out key verification with the encrypted circuit that is being connected FPGA.After verification is passed through, FPGA has just had the function of choosing scheme.Whole Dynamic Configuration Process is no more than 1 second, and real-time is very strong.
Fig. 2 is that the present invention be take the hardware circuit that four FPGA configuring chips are example and connected total figure.Block1 module produces the 50M global clock of input FPGA, reset signal with reconfigure driving signal, and complete being connected of photomultiplier and this circuit, hardware circuit connects as Fig. 3.FPGA is a slice fpga chip and peripheral circuit thereof, for not realizing in the same time a plurality of separate correlators.Block2 module produces 50M clock and the reset signal of input CPLD, CPLD is piece of CPLD chip and peripheral circuit thereof, for realizing monitoring by the allocation plan selection instruction of UART & USB input, according to instruction, complete the dynamic interconnection of FPGA configuration pin and configuring chip pin, and drive FPGA to reconfigure.EPCS64 (1), EPCS64 (2), EPCS64 (3), EPCS64 (4) are four FPGA configuring chips and peripheral circuit thereof, for storing four kinds of different correlator allocation plans.UART & USB is connected with the instruction monitoring module in CPLD with the Computer Interface Module in FPGA, hardware circuit connects as Fig. 4, completes computing machine transmission allocation plan selection instruction and to CPLD and FPGA, carries out parameter setting and the transmission of related operation curve data of related operation.
Because the programmable resource in FPGA is limited, determined that the assignable port number of photon correlator is limited, if channel time allocative decision is fixed, often can not adapt to well the utilization of different occasions.The linear passageway allocative decision of 200 port numbers of take is example, and in based on photon correlation spectroscopy nano particles measuring technique, the decay of the Intensity correlation function of large grain diameter nano particle is slower.As Fig. 5, particle diameter is that the Intensity correlation function of 1000 nano particles needs the time of about 0.1s to decay, and this just requires the maximum delay time long enough of correlator passage.Suppose that its minimum delay time is 500us, its maximum delay time is 0.1s, but now the minimum delay time of passage is oversize, can not meet the inverting needs of small particle diameter nano particle.In the measurement of small particle diameter nano particle, its Intensity correlation function decay is very fast, as Fig. 5, the Intensity correlation function of the particle of 3 nanometers only needs the time of about 0.1ms just to decay, this just requires the minimum delay time of correlator passage shorter, supposes its minimum delay time 0.5us, and its maximum delay time is 0.1ms, but now its maximum delay time too short, can not meet the inverting needs of large grain diameter nano particle.By the control of the software on computing machine, utilize the configuration of many allocation plans Dynamic Selection, can adaptively obtain optimized correlation curve, thereby meet the needs of measurement and the inverting of various granularities, improve measuring accuracy.
The correlator of storing different passage allocation plans in four configuring chips, has different minimums and maximum delay time, is applicable to respectively obtaining the related function of differential declines rate.Also can in configuring chip, store dissimilar correlator, i.e. autocorrelator and cross-correlator.
Because the adaptive measuring principle of cross-correlator and the adaptive measuring principle of autocorrelator are consistent, the adaptive measuring principle of autocorrelator of therefore take illustrates the principle of its adaptive measuring as example.After system powers on, acquiescence is configured to the autocorrelator allocation plan that meets big-and-middle grain diameter nano particle sizing and inverting in FPGA.When nanometer is measured, complete after auto-correlation computation, autocorrelation function is input in computing machine.Software on computing machine is processed the data of input, attenuation rate with preliminary judgement related function, again according to this attenuation rate, by computer software, send instruction and choose the suitable passage allocation plan being stored in configuring chip, under the control of CPLD, the allocation plan of choosing is configured in FPGA, re-starts related operation and follow-up data processing, such as granularity inverting etc.User starts after measurement, and whole measuring process is controlled automatically by the software on computing machine, possesses adaptive function, simple to operate, and wherein the Dynamic Selection speed of allocation plan is less than 1 second, real-time.Because autocorrelator principle is consistent, therefore, take one of them autocorrelator its principle to be described as example.In Fig. 6, there are 6 input lines, 2 output lines.Having four main functional modules: ResetDelay is synchronous reset module; PhotonCounter is photon counting module; ProCorrelaton1 is auto-correlation computation module; ProOutput1 is Computer Interface Module.Enable is the enable signal of encrypting module output, and for enabling photon counting module, high level is effective.ICLK50M is the global clock input of 50M, for driving each circuit module.IRST is external reset input line, and the reset signal oRESET being produced by ResetDelay module, as overall reset signal, is Low level effective simultaneously.IPhotonPulse is the input of photon pulse signal, for being connected with photon detector.IRX and iUSBRX carry out with computing after as input, can turn serial port chip with USB circuit with serial ports and be connected, be input to ProOutput1 Computer Interface Module, the result data of autocorrelation calculation is conveyed into computing machine by an interface.OTX is that serial ports turns with USB circuit the output line that serial port chip is connected with computer interface with oUSBTX.
If select cross-correlator, its principle and auto-correlation are similar, and the mutual autocorrelator of take here illustrates its principle as example.In Fig. 7, there are 7 input lines, 2 output lines.Having five main functional modules: ResetDelay is synchronous reset module; PhotonCounter is photon counting module, has two separate photon counting modules; ProCorrelaton1 is computing cross-correlation module; ProOutput2 is Computer Interface Module.Enable is the enable signal of encrypting module output, and for enabling photon counting module, high level is effective.ICLK50M is the global clock input of 50M, for driving each modular circuit.IRST is external reset input line, and the reset signal oRESET being produced by ResetDelay module, as overall reset signal, is Low level effective simultaneously.The photon pulse signal input of iPhotonPulse1 Wei Yi road, iPhotonPulse2 is another road photon pulse signal input.IRX and iUSBRX carry out with computing after as input, can turn serial port chip with USB circuit with serial ports and be connected, be input to ProOutput2 Computer Interface Module, the result data of cross-correlation calculation is conveyed into computing machine by an interface.OTX is that serial ports turns with USB circuit the output line that serial port chip is connected with computer interface with oUSBTX.
In the present invention, be solidificated in interior each module more detailed description of FPGA as follows:
Synchronous reset module
Synchronous reset module completes after hardware powers on or FPGA reset key press after each module synchronous reset load with acquiescence initial value.Concrete principle design is as Fig. 8.ICLK is external hardware input clock pulse, and iRST is the level by external key control inputs, and oRESET is output reset signal, Low level effective.
Photon counting module
Photon counting module is the important component part that photon correlator carries out related operation, the function that it is realized is except counting photon signal, the function of the accumulating operation that also comprises that the shift register that starts related operation module be shifted and parallel multiplication multiplies each other, the while is also being controlled the total degree of computing.But correlator of the present invention is this function of maskable also, from external input signal, also can realize related operation.Concrete principle design is as Fig. 9.This circuit has 5 input lines, 2 output lines, and an enumeration data figure place is controlled parameter.Wherein Enable is the enable signal of encrypting module output, and high level is effective.ICLK50M is the clock input of 50M, for controlling the sampling time, and when gate time is identical with the sampling time, output count data.IRST is overall reset signal input line, is Low level effective simultaneously.IPhotonPulse is the input of photon pulse signal, for being connected with photon detector.ISampleWord is the parameter input line of photon counting module, controls sampling time interval, and data are calculated by (sampling time/input clock cycle).IDataWidth is that enumeration data figure place is controlled parameter, for controlling the figure place of count results.ODataCLK is count results clock, during rising edge, result is latched to output.OData[iDataWidth-1..0] be the output of count results.
Related operation module
Related operation module is the core of photon correlator, and in autocorrelator, related operation module is auto-correlation computation module.In cross-correlator, related operation module is computing cross-correlation module.
First introduce auto-correlation computation module, the function that it is realized is mainly that the output data of photon counting module are carried out to auto-correlation computation.It is basis that auto-correlation computation be take shift register and parallel multiplication, and the auto-correlation computation of 4 passages of take illustrates the principle of work of autocorrelator as example, as shown in figure 10.
Shift clock is stored in photon count value in first unit of shift register, and when next shift clock arrives, the numerical value n (1) of first unit of shift register is transferred to second unit, starts multiply-accumulator and carries out computing.After N sampling, use n
irepresent i the photon counting in the sampling time, i=1,2,3 ... N, the numerical value that 4 totalizers in Figure 10 are preserved is respectively:
The 1st totalizer: R (Δ τ)=n
1n
2+ n
2n
3+ ... + n
n-1n
n
The 2nd totalizer: R (2 Δ τ)=n
1n
3+ n
2nn
4+ ... + n
n-2n
n
The 3rd totalizer: R (3 Δ τ)=n
1n
4+ n
2n
5+ ... + n
n-3n
n
The 4th totalizer: R (4 Δ τ)=n
1n
5+ n
2n
6+ ... + n
n-4n
n
In FPGA, the above-mentioned principle of auto-correlation computation module Main Basis has built shift register module and parallel multiplication module.Shift register module completes storage and the shifting function of data, and concrete circuit design is as Figure 11.This circuit has 3 inputs, and iCLK is shift clock, and iEn is enable signal, and high level is effective, iData[idatawidth..0] be the data input pin of first shift register.When iEn enables, during iCLK rising edge, data iData[idatawidth..0] shift-in is in inst unit, inst cell data shift-in inst1 unit simultaneously, by that analogy.
Parallel multiplication module completes multiplying each other and cumulative operation of data.Concrete circuit design is as Figure 12.ICLK50M is the clock input of 50M, and iRST is reset input line, and iEn is enable signal, and high level is effective.ICLK is shift clock, iDataA[3..0] be the data of first shift register in Figure 11, iDataB[119..0] [3..0] be the data of the corresponding shift register of predefined calculative passage.Multiplying in parallel multiplication has been used the high-speed hardware multiplier embedding in FPGA to adopt time-multiplexed method to calculate, and has saved hardware resource.Introduce computing cross-correlation module below, the function that it is realized is mainly that the data of two separate photon counting module outputs are carried out to computing cross-correlation.Computing cross-correlation is also that to take shift register and parallel multiplication be basis, the different photon pulse signal of two-way enters after FPGA, by two separate photon counting modules, count respectively, and send into shift register, according to the channel allocation scheme of setting, carry out computing cross-correlation.The 4 channel cross correlation computings of take describe computing cross-correlation process as example, and theory diagram is as mistake! Do not find Reference source.Shown in.
Photon counting 1 and photon counting 2 modules are counted photon pulse 1 and photon pulse 2 respectively, and photon number is sent into respectively in shift register A and B.Photon count value, under shift clock effect, enters next shift register from a shift register, starts multiply-accumulator simultaneously and carries out computing.Use A
i, B
irepresent respectively photon pulse 1, the photon counting of photon pulse 2 i in the sampling time, i=1,2,3 ... N.After N sampling, a mistake! Do not find Reference source.In the numerical value preserved of first totalizer R (Δ τ) be:
R(Δτ)＝B
1A
2+B
2A
3+…+B
N-1A
N
According to the distribution of cross-correlator passage, calculate corresponding channel cross correlation value.The data of its computing are from the result of two photon counting modules, and are sent in two shift registers of A, B in Figure 13, because computation process is below consistent with auto-correlation computation, therefore, repeat no more.
Computer Interface Module
Computer Interface Module completes communicating by letter of computing machine and correlator in FPGA, sets up serial data receiving element and serial data transmitting element in FPGA.The instruction that receiving element receiving computer sends, transmitting element sends to computing machine by the result data of related operation.
Encrypting module
Encrypting module is the program to FPGA for encryption configuration, and the program of preventing is replicated to be transplanted to other hardware.Concrete principle design is as Figure 14.Have 2 input lines, 2 with output line, and Clock_In is clock signal input line, and Resetn_In inputs for the reset signal of being controlled by external key, and Enable is the enable signal of output.One_Wire is connected with external encryption circuit.Having 3 main functional module: RNG_8Bits is random 8 figure place generation modules; Small_micro_32 is that hash algorithm calculates and result correction verification module; One_Wire is external encryption circuit interface module.
In the present invention, be solidificated in interior each module more detailed description of CPLD as follows:
CPLD reseting module
CPLD reseting module completes after hardware powers on or the loading that each module resets with acquiescence initial value in CPLD after pressing of CPLD reset key.Concrete principle design is as Fig. 8, in full accord with the synchronous reset module in FPGA.
Instruction monitoring module
Instruction monitoring module is for monitoring the allocation plan selection instruction of being sent by computing machine.In CPLD, set up serial data receiving element, the instruction that receiving computer sends.When computing machine sends instruction to CPLD, instruction monitoring module is identified judgement to the instruction receiving, and when being judged to be certain allocation plan selection instruction, result of determination is sent in dynamic-configuration module, if not certain allocation plan selection instruction, keep original state.
Dynamic-configuration module
Dynamic-configuration module is according to the result of determination of instruction monitoring module, dynamically interconnects, and drive FPGA to reconfigure by storing configuring chip pin and the FPGA configuration pin that instruction chooses allocation plan, completes the Dynamic Selection configuration to FPGA.Concrete principle design is as Figure 15.ICLK50M is the input of 50M time clock, iRST is reset signal input, iResult is result of determination input, the configuration pin that DCLK, nCS, ASDI, DATA are FPGA, DCLK1, nCS1, ASDI1, DATA1 are the pin of first configuring chip, DCLK2, nCS2, ASDI2, DATA2 are the pin of second configuring chip, DCLK3, nCS3, ASDI3, DATA3 are the pin of the 3rd configuring chip, DCLK4, nCS4, ASDI4, DATA4 are the pin of the 4th configuring chip, and oConfig is that FPGA reshuffles the output of driving signal.
The present invention compared with prior art tool has the following advantages:
1, the present invention is based on a slice fpga chip and multiple FPGA configuring chip, by the dynamic interconnection of piece of CPLD chip controls FPGA configuration pin and multi-disc configuring chip pin, adopt the mode of Quartus II Design of Software Platform to realize self-adaptation photon correlator.This method for designing has following several features: (1), use Quartus II Software for Design circuit program, utilize USB Blaster downloading wire and jtag interface or AS download interface to download on circuit board; (2), can to program, change by Quartus II software, thereby realize the improvement of the present invention to photon correlator; (3), can apply the wave simulation in Quartus II software platform, to synchronous reset module, the modules such as photon counting module are carried out emulation.
2, the present invention adopts the mode of multiple FPGA configuring chip dynamic-configuration FPGA, has realized auto-correlation computation and computing cross-correlation, and user can be by the software on computing machine, and which kind of related operation scheme interactively selects to adopt.Change places and expanded the dynamic range of correlator time delay, thereby improve function and the performance of correlator, reach the effect of " one-machine-multi-function ".
3, parallel multiplication of the present invention, the high-speed multiplier embedding based on FPGA, adopts time-division multiplex technology, thereby has improved the speed of related operation, has optimized hardware resource.
4, the present invention adopts high density fpga chip, synchronous reset module, and photon counting module, related operation module, Computer Interface Module, encrypting module, is solidificated in FPGA, thereby improves the stability of correlator circuit, reduces circuit power consumption.
5, the present invention is based on universal field-programmable chip FPGA and realize self-adaptation photon correlator, resource distribution is flexible, is easy to properties of product upgrading.
6, the present invention utilizes CPLD chip, CPLD reseting module, and instruction monitoring module, dynamic-configuration module, is solidificated in CPLD, thereby has improved the expansibility of correlator allocation plan.
7, the present invention adopts encrypting module and the cipher mode that external encryption circuit combines in FPGA, has improved the confidentiality of program.
8, the present invention combines with the software on computing machine, and in measurement, according to the feature of correlation curve, adaptive adjustment allocation plan, makes the optimization of obtaining of correlation curve.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present invention;
Fig. 2 is that hardware circuit of the present invention connects total figure;
Fig. 3 is global clock, external reset in Fig. 1, reshuffles driving, signal input hardware circuit connection diagram;
Fig. 4 is USB and the serial ports hardware circuit connection layout in Fig. 1;
Fig. 5 is the Intensity correlation function figure of four kinds of different-grain diameter nano particles;
Fig. 6 is the flow chart of the interior autocorrelator of fpga chip in Fig. 1;
Fig. 7 is the flow chart of the interior cross-correlator of fpga chip in Fig. 1;
Fig. 8 is the synchronous reset module circuit diagram being solidificated in Fig. 5, Fig. 6 in fpga chip;
Fig. 9 is the photon counting module circuit diagram being solidificated in Fig. 5, Fig. 6 in fpga chip;
Figure 10 is the cumulative schematic diagram of the multiplication in auto-correlation computation module;
Figure 11 is the shift register schematic diagram in the related operation module being solidificated in fpga chip;
Figure 12 is the parallel multiplication schematic diagram in the related operation module being solidificated in fpga chip;
Figure 13 is the cumulative schematic diagram of the multiplication in computing cross-correlation module;
Figure 14 is the flow chart of the interior encrypting module of fpga chip in Fig. 1;
Figure 15 is the dynamic-configuration module circuit diagram being solidificated in CPLD chip;
Figure 16 is synchronous reset module sequential simulation waveform figure;
Figure 17 is photon counting modular simulation oscillogram;
Figure 18 is related operation module sequential chart;
Figure 19 is the computer interface receiver module circuit diagram being solidificated in fpga chip;
Figure 20 is the computer interface sending module circuit diagram being solidificated in fpga chip.
Embodiment
Synchronous reset module
ICLK is external hardware input clock pulse, and iRST is external reset signal input, and oRESET is output reset signal.Figure 16 is simulation waveform, after powering on or FPGA reset key iCLK is counted after pressing, when being less than the value 16 (this value can be revised) of setting, be output as low level, each module is in the meantime in reseting stage, simultaneously the initial value data of load default.Thereafter export high level, each module is normally worked.
Photon counting module
Photon counting modular simulation waveform is as Figure 17.When iRST is high level, counting module is normally worked, the clock input that iCLK50M is 50M, iPhotonPulse is photon pulse signal, and iSampleWord is sampling time parameter setting, with the 5us sampling time, 50M clock is input as example, iSampleWord=(5x10
-6/ (1/50x10
6))=250.ODataCLK is the output clock of data, during rising edge, data is latched to output.When 5us timing, arrive, oDataCLK draws into high level, from oData[iDataWidth-1..0] output data.IDataWidth is that data bits is controlled parameter, can, according to the length in sampling time, select.With the 5us sampling time, 1 second related operation time was example, and when iDataWidth is set to 4, the tolerable photon number of maximum per second is (1/ (5x10
-6)) x (2
4-1)=3M.In simulation waveform, iSampleWord is set to 250, and first 5us is in the time, and photon pulse number is 2, the second 2us in the time, and photon pulse number is 4.
Related operation module
Related operation module completes related operation, and concrete work schedule process is as Figure 18.When iRST is low level, circuit is in reseting stage, and when becoming high level, circuit is normally worked.When iEn is high level, parallel multiplication enables, during low level, and parallel multiplication zero clearing.ICLK is the clock of photon counting module output, and the inversion clock that MacCLK is iCLK, for controlling the calculating of parallel multiplication.During high level, parallel multiplication carries out related operation with the speed of 50M.
Computer Interface Module
Computer Interface Module completes communicating by letter of computing machine and correlator, receiving element RxdAll and transmitting element TXDControl, consists of.RxdALL, as shown in figure 19, has 3 input ends, 3 output terminals.IRX is the receiving end of data, and iCLK50M is the input of 50M clock, and iRST is reset signal.OEn is for receiving the effective output line of data, and high level is effective.OData[605..0] [7..0] for receiving data buffering, oRxdNum[9..0] data amount check received of indication.TXDControl, as shown in figure 20, has 6 input ends, 2 output terminals.ICLK is the input of 50M clock signal.IRST is reset signal, Low level effective.IEn is output enable signal, and high level is effective.ITxdNum[9..0] be transmission data amount check input parameter.IData[605..0] [7..0] for transmission data buffering.IStart is that transmission of control signals starts control signal, and high level is effective.ODone controls settling signal for transmission, and high level is effective.OTX is DOL Data Output Line.
Encrypting module
Encrypting module and external encryption circuit are combined encryption configuration to the program in FPGA.As shown in figure 14, its concrete encryption principle is: after device powers on or external reset key press 8 random numbers that rear FPGA produces RNG_8Bits module and send in external encryption circuit by small_micro_32 and One_Wire module, FPGA reads the unique sequence number of external encryption circuit, external encryption circuit starts hash algorithm and calculates, and FPGA reads one group of message authentication code that external encryption circuit produces.Small_micro_32 module starts hash algorithm and calculates the other one group of message authentication code of generation, and two groups of Message Authentication Codes carry out verification.If verification is passed through, Enable is output as high level, enables photon counter module, if verification is not passed through, Enable is output as low level, forbids photon counter module, thereby reaches the object of encryption.
CPLD reseting module
The embodiment of CPLD reseting module and the synchronous reset module in fpga chip are in full accord, therefore, repeat no more.
Instruction monitoring module
Serial data receiving element and the receiving element RxdALL in the Computer Interface Module in FPGA in instruction monitoring module are in full accord, as shown in figure 19.The default value of the instruction that the computing machine receiving is sent and program contrasts.When the instruction value default with which kind of allocation plan is consistent, which kind of allocation plan is selected.When all inconsistent, keep original allocation plan.
Dynamic-configuration module
Dynamic-configuration module is carried out dynamic-configuration according to the result of determination of instruction monitoring module.As Figure 15, when the first allocation plan is selected, tetra-pins of DCLK, nCS, ASDI, DATA of FPGA configuration pass through the inside of CPLD chip and DCLK1, the nCS1 of first configuring chip, ASDI1, tetra-pins of DATA1 are corresponding is connected, and oConfig exports a low pulse, drive FPGA to reconfigure, complete the dynamic-configuration of the first allocation plan.When the second allocation plan is selected, tetra-pins of DCLK, nCS, ASDI, DATA of FPGA configuration pass through the inside of CPLD chip and DCLK2, the nCS2 of second configuring chip, ASDI2, tetra-pins of DATA2 are corresponding is connected, and oConfig exports a low pulse, drive FPGA to reconfigure, complete the dynamic-configuration of the second allocation plan.By that analogy, can realize the selectivity dynamic-configuration of various configurations scheme.
Claims (10)
1. the self-adaptation photon correlator based on CPLD and field programmable gate array, is characterized in that comprising:
---fpga chip circuit, realize a plurality of separate digital correlators, by a slice fpga chip, formed;
---FPGA clock, reset, reshuffle circuit, realize the driving of each circuit module in FPGA, synchronous reset, the driving reconfiguring;
---serial ports and USB circuit, realize FPGA, CPLD and compunication;
---for the encrypted circuit of photon correlator, for encryption configuration to the program on fpga chip;
---for CPLD and the multiple FPGA chip configuration circuit of photon correlator, utilize CPLD that the various configurations Scheme Choice ground being stored on multi-disc configuring chip is dynamically configured on fpga chip;
---CPLD clock, reset circuit, realize the driving of each circuit module of CPLD, reset;
---synchronous reset module, be solidificated in FPGA, complete after hardware powers on or FPGA reset key press after the synchronous reset of each module and the loading of acquiescence initial value in fpga chip;
---photon counting module, be solidificated in FPGA, for adding up the number of photon in certain hour interval, and latch output, send into related operation module;
---related operation module, be solidificated in FPGA, the data of photon counting module output are carried out to auto-correlation computation or computing cross-correlation, obtain autocorrelator trace or simple crosscorrelation curve, and latch output, pass through Computer Interface Module, with compunication, realize the output of data;
---Computer Interface Module, be solidificated in FPGA, by serial ports and USB circuit interface and compunication, realize the setting of correlator parameter and auto-correlation computation or the output of computing cross-correlation result data;
---encrypting module, be solidificated in FPGA, complete being configured to the encryption of FPGA Program;
---CPLD reseting module, be solidificated in CPLD, complete after hardware powers on or CPLD reset key press after the reset of each module and the loading of acquiescence initial value in CPLD chip;
---the instruction monitoring module for photon correlator, be solidificated in CPLD, for monitoring by serial ports and USB circuit interface, the allocation plan selection instruction of being sent by computer software;
---for the dynamic-configuration module of photon correlator, be solidificated in CPLD, for dynamically interconnecting storing configuring chip pin and the FPGA configuration pin that instruction chooses allocation plan, and drive FPGA to reconfigure, complete the Dynamic Selection configuration to FPGA.
2. self-adaptation photon correlator according to claim 1, is characterized in that described FPGA clock, resets, reshuffles circuit and consist of Block1 circuit.
3. self-adaptation photon correlator according to claim 1 and 2, is characterized in that described serial ports and USB circuit consist of UART & USB circuit; Described encrypted circuit consists of DS28E01 chip circuit.
4. self-adaptation photon correlator according to claim 3, is characterized in that described CPLD and multiple FPGA configuring chip circuit consist of piece of CPLD chip circuit and multiple FPGA chip configuration circuit; Described CPLD clock, reset circuit consist of Block2 circuit.
5. self-adaptation photon correlator according to claim 4, is characterized in that described synchronous reset module mainly comprises the output module of the input of 50M length of a game, external reset signal input and synchronous reset signal.
6. self-adaptation photon correlator according to claim 5, is characterized in that described photon counting module mainly comprises the load module of the input Yu50M length of a game of iSampleWord parameter.
7. self-adaptation photon correlator according to claim 6, is characterized in that described related operation module consists of shift register and parallel multiplication, optionally realizes auto-correlation computation and computing cross-correlation; Described Computer Interface Module consists of receiving element RxdAll and transmitting element TXDControl.
8. self-adaptation photon correlator according to claim 7, it is characterized in that described encrypting module is by random 8 figure place generation module RNG_8Bits, hash algorithm calculates and result correction verification module small_micro_32 and these 3 module compositions of external encryption circuit interface module One_Wire.
9. the self-adaptation photon correlator of stating according to Claim 8, is characterized in that described CPLD reseting module mainly comprises the output module of the input of 50M time, external reset signal input and CPLD reset signal.
10. self-adaptation photon correlator according to claim 9, is characterized in that described instruction monitoring module consists of serial ports receiving element RxdAll and allocation plan preset value; Described dynamic-configuration module mainly consists of All circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110194051.9A CN102313604B (en) | 2011-07-12 | 2011-07-12 | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110194051.9A CN102313604B (en) | 2011-07-12 | 2011-07-12 | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102313604A CN102313604A (en) | 2012-01-11 |
| CN102313604B true CN102313604B (en) | 2014-04-09 |
Family
ID=45426971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110194051.9A Expired - Fee Related CN102313604B (en) | 2011-07-12 | 2011-07-12 | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102313604B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102798582A (en) * | 2012-05-22 | 2012-11-28 | 山东理工大学 | Proportional photon correlator based on digital signal processor (DSP) annular buffer area |
| CN104792670B (en) * | 2015-04-09 | 2018-04-03 | 华南师范大学 | A kind of multiplexing photon correlator based on field programmable gate array |
| CN106648791B (en) * | 2016-12-29 | 2019-11-05 | 成都多沐汽车工程有限公司 | Data load method and device |
| CN111339484B (en) * | 2020-02-20 | 2022-07-01 | 中国科学院自动化研究所 | FPGA-based large-scale radio interference array correlator realization method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109801A (en) * | 2007-07-06 | 2008-01-23 | 东南大学 | Correlator circuit for global positioning system |
| CN101256230A (en) * | 2007-11-21 | 2008-09-03 | 北京理工大学 | Continuous wave chaos phase-modulation radio fuse detection system and demodulation method |
| CN101562486A (en) * | 2009-06-09 | 2009-10-21 | 中国传媒大学 | Method for adding associated audio frequency signaling to frequency modulation synchronized broadcast |
| CN101576867A (en) * | 2009-06-17 | 2009-11-11 | 北京星网锐捷网络技术有限公司 | Extended universal asynchronous serial interface method, device and system |
| CN101726452A (en) * | 2009-12-08 | 2010-06-09 | 华南师范大学 | Photon correlator based on field programmable gate array (FPGA) |
-
2011
- 2011-07-12 CN CN201110194051.9A patent/CN102313604B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109801A (en) * | 2007-07-06 | 2008-01-23 | 东南大学 | Correlator circuit for global positioning system |
| CN101256230A (en) * | 2007-11-21 | 2008-09-03 | 北京理工大学 | Continuous wave chaos phase-modulation radio fuse detection system and demodulation method |
| CN101562486A (en) * | 2009-06-09 | 2009-10-21 | 中国传媒大学 | Method for adding associated audio frequency signaling to frequency modulation synchronized broadcast |
| CN101576867A (en) * | 2009-06-17 | 2009-11-11 | 北京星网锐捷网络技术有限公司 | Extended universal asynchronous serial interface method, device and system |
| CN101726452A (en) * | 2009-12-08 | 2010-06-09 | 华南师范大学 | Photon correlator based on field programmable gate array (FPGA) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102313604A (en) | 2012-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101726452B (en) | Photon correlator based on field programmable gate array (FPGA) | |
| CN105807263B (en) | A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing | |
| CN102313604B (en) | Adaptive photon correlator on basis of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) | |
| CN104901719B (en) | A kind of common satellite interference signal generation method | |
| CN102736891A (en) | Design of parallel adjustable pseudorandom sequence generator | |
| CN103984560A (en) | Embedded reconfigurable system based on large-scale coarseness and processing method thereof | |
| CN103577373A (en) | Techniques for aligning and reducing skew in serial data signals | |
| CN102945224A (en) | High-speed variable point FFT (Fast Fourier Transform) processor based on FPGA (Field-Programmable Gate Array) and processing method of high-speed variable point FFT processor | |
| CN103870421A (en) | FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core | |
| CN102446557B (en) | A kind of a kind of method of chip and chip parallel test | |
| CN103078729B (en) | Based on the double precision chaos signal generator of FPGA | |
| CN201589663U (en) | Photon correlator based on field-programmable gate arrays (FPGA) | |
| CN101888209A (en) | Gaussian white noise generator based on FPGA (Field Programmable Gate Array) | |
| CN106030543A (en) | Interference testing | |
| CN102033032B (en) | Digital correlator for photon correlated nanometer zetasizer | |
| CN202395792U (en) | Double precision chaotic signal generator based on FPGA | |
| CN103699355B (en) | Variable-order pipeline serial multiply-accumulator | |
| CN109217617A (en) | A kind of the pumping signal searching method and electronic equipment of motor | |
| CN105955705B (en) | A kind of restructural multi-channel detection algorithm accelerator | |
| CN100588981C (en) | On-site programmable gate array duplex selector verification method | |
| CN106385311A (en) | Chaotic signal generator of complex chaotic simplified system based on FPGA | |
| CN102117264B (en) | Fast Walsh transform realization method based on FPGA (Field Programmable Gate Array) | |
| CN104635215B (en) | A kind of interfering well cluster device based on SOPC | |
| CN103577151A (en) | Multi-path pseudorandom sequence generation chip | |
| CN104794002A (en) | Multi-channel parallel dividing method based on specific resources and hardware architecture of multi-channel parallel dividing method based on specific resources |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140409 |