CN104681542A - Semiconductor electrostatic discharge protection device - Google Patents
Semiconductor electrostatic discharge protection device Download PDFInfo
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- CN104681542A CN104681542A CN201310628550.3A CN201310628550A CN104681542A CN 104681542 A CN104681542 A CN 104681542A CN 201310628550 A CN201310628550 A CN 201310628550A CN 104681542 A CN104681542 A CN 104681542A
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Abstract
The invention discloses a semiconductor electrostatic discharge protection device, which comprises a first electric transistor, a second electric trap region, a second electric protection ring and a semiconductor separation region, wherein the first electric transistor is formed in the second electric trap region, the second electric protection ring surrounds the first electric transistor, the semiconductor separation region is positioned between the first electric transistor and the second electric protection ring, and surrounds the first electric transistor, and in addition, the semiconductor separation region is a non-doping region, a first electric doping region or a second electric doping region with the doping concentration being smaller than that of the second electric trap region.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit element, and particularly relate to a kind of semiconductor electrostatic discharge protector.
Background technology
Static discharge is the phenomenon that a kind of electrostatic charge be positioned on non-conducting surfaces is moved by electric conducting material.Because electrostatic potential is usually quite high, static discharge can damage substrate and other elements of an integrated circuit easily.In order to Protective IC avoids the infringement suffering static discharge, have conducting static electricity discharging current to ground surface function device be integrated in integrated circuit.
With grounded gate n-type Metal-oxide-semicondutor conductor Gate Grounded n-type Metal-Oxide-Semiconductor, GGNMOS) transistor unit is example, its grid, source electrode and element base ground connection, when there is (ESD zapping) in static discharge, rapid time collapse (snapback) causes grounded gate n-type metal-oxide semiconductor transistor unit meeting conducting, so that a large static discharge current (ESD current) is conducted between its drain electrode structure and source configuration, again static discharge current is conducted to ground, reach the defencive function of static discharge.
But traditional grounded gate n-type Metal-oxide-semicondutor conductor transistor unit, the easy impact extending out effect (base push-out effect) because being subject to parasitic NPN double carriers junction transistor, there is secondary and suddenly return collapse phenomenon, to make excessive leakage current by parasitic double carriers junction transistor by emitter-base bandgap grading and ground connection base stage, again by element base (parasitic base) conduct to ground, cause grounded gate n-type Metal-oxide-semicondutor conductor transistor unit eventual failure.
Therefore, how to prevent the parasitic double carriers junction transistor electric leakage of semiconductor electrostatic discharge protector, become a major challenge in electrostatic discharge protective design.
Summary of the invention
For solving the problem, one aspect of the present invention is to provide a kind of semiconductor electrostatic discharge protector, comprising: have the first electrical the first transistor, the second electrical well region, the second electrical guard ring and semiconductor spacer region.The first transistor is formed among the second electrical well region.Second electrical guard ring, around the first transistor.Semiconductor spacer region, between the first transistor and the second electrical guard ring, and around the first transistor.Wherein, semiconductor spacer region is undoped region, the first electrical doped region or doping content be less than the second electrical doped region of the second electrical well region.
Among one embodiment of the invention, semiconductor electrostatic discharge protector, also comprises a shallow trench isolation structure, between the first transistor and the second electrical guard ring.Wherein, semiconductor spacer region is the below being positioned at shallow trench isolation structure.
Among one embodiment of the invention, semiconductor electrostatic discharge protector, also comprises a shallow trench isolation structure, between the first transistor and the second electrical guard ring.Wherein, semiconductor spacer region is between shallow trench isolation structure and the second electrical guard ring.
Among one embodiment of the invention, first is electrically that N-type is electrical, and second is electrically that P type is electrical.Among one embodiment of the invention, first is electrically that P type is electrical, and second is electrically that N-type is electrical.
Among one embodiment of the invention, the first transistor comprises grid structure, source electrode, drain electrode and the second electrical high-concentration dopant district.Grid structure is formed on the second electrical well region.Source electrode is formed among the second electrical well region, and adjoins gate structure.Drain electrode is formed among the second electrical well region, and adjoins gate structure.Second electrical high-concentration dopant district, is positioned among the second electrical well region below drain electrode, and has the doping content higher than the second electrical well region.
Among one embodiment of the invention, wherein semiconductor electrostatic discharge protector also comprises a substrate contact district, is adjacent to the second electrical well region and the second electrical guard ring.Wherein, substrate contact district and source electrode common ground, and drain electrode is electrically connected with an I/o pad (I/O pad).
Among one embodiment of the invention, semiconductor electrostatic discharge protector also comprises and has the first electrical transistor seconds and third transistor.Wherein the first transistor, transistor seconds and third transistor have a common drain.
Among one embodiment of the invention, semiconductor electrostatic discharge protector, also comprises trap contact zone (Well Pick-Up) and has the first electrical transistor seconds and third transistor.Wherein, the first transistor, transistor seconds and third transistor have a common source, around trap contact zone.
The present invention is providing a kind of semiconductor electrostatic discharge protector on the other hand, comprising: multiple first conductive crystal pipe, the second electrical guard ring and trap contact zone.Wherein, the second electrical guard ring, around this few first conductive crystal pipe; And this few first conductive crystal pipe, around trap contact zone.
Among one embodiment of the invention, semiconductor electrostatic discharge protector also comprises, the first electrical guard ring, between this few first conductive crystal pipe and the second electrical guard ring, and around this few first conductive crystal pipe.
Among one embodiment of the invention, each the first transistor comprises a grid structure, one source pole and a drain electrode.Grid structure is formed on one second electrical well region.Drain electrode is formed among the second electrical well region, and adjoins gate structure is away from the side of trap contact zone.Source electrode is formed among the second electrical well region, and adjoins gate structure is near the side of trap contact zone.
Among one embodiment of the invention, trap contact zone and source electrode common ground, and drain electrode is electrically connected with an I/o pad.
Among one embodiment of the invention, each the first transistor also comprises one second electrical high-concentration dopant district, is positioned among the second electrical well region below drain electrode, and has the doping content higher than the second electrical well region.
According to above-described embodiment; of the present inventionly be to provide a kind of semiconductor electrostatic discharge protector; among one embodiment of the invention, semiconductor electrostatic discharge protector at least comprises: be formed at 1 among element base first conductive crystal pipe, around one second electrical guard ring of the first conductive crystal pipe and the semiconductor spacer region between the first conductive crystal pipe and the second electrical guard ring.Wherein, semiconductor spacer region is undoped region, the first electrical doped region or doping content be less than the second electrical doped region of the second electrical well region.By between the firstth conductive crystal pipe and the second electrical guard ring; the mode of semiconductor spacer region is set; with the distance between the electrical guard ring of drain electrode and second increasing by the first conductive crystal pipe; and then the resistance increased between double carriers junction transistor emitter-base bandgap grading parasitic in semiconductor electrostatic discharge protector and ground connection base stage; reduce leakage current and conduct to ground by draining by element base, and then promote the ESD protection of semiconductor electrostatic discharge protector.
In still another embodiment of the present invention, semiconductor electrostatic discharge protector at least comprises: be formed at the multiple first conductive crystal pipes among element base, around the first conductive crystal pipe the second electrical guard ring and by this few first conductive crystal circumference of cannon bone around trap contact zone.By specific wire laying mode; increase the distance between the drain electrode of the first conductive crystal pipe and trap contact zone; and then the resistance increased between double carriers junction transistor emitter-base bandgap grading parasitic in semiconductor electrostatic discharge protector and ground connection base stage; reduce leakage current and conduct to ground by draining by trap contact zone, and then promote the ESD protection of semiconductor electrostatic discharge protector.
Accompanying drawing explanation
For above and other object of the present invention, feature and advantage can be become apparent, several preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Figure 1A is the structure schematic top plan view of the semiconductor electrostatic discharge protector illustrated according to one embodiment of the invention;
Figure 1B is the part-structure generalized section of the semiconductor electrostatic discharge protector illustrated along the tangent line S1 of Figure 1A;
Fig. 2 A is the structure schematic top plan view of semiconductor electrostatic discharge protector illustrated according to another embodiment of the present invention;
Fig. 2 B is the part-structure generalized section of the semiconductor electrostatic discharge protector illustrated along the tangent line S2 of Fig. 2 A;
Fig. 3 A is the structure schematic top plan view of semiconductor electrostatic discharge protector illustrated according to still another embodiment of the invention;
Fig. 3 B is the part-structure generalized section of the semiconductor electrostatic discharge protector illustrated along the tangent line S3 of Fig. 3 A;
Fig. 4 A is the structure schematic top plan view of the semiconductor electrostatic discharge protector illustrated according to one more embodiment of the present invention;
Fig. 4 B is the part-structure generalized section of the semiconductor electrostatic discharge protector illustrated along the tangent line S4 of Fig. 4 A;
Fig. 5 A is the structure schematic top plan view of the semiconductor electrostatic discharge protector that another embodiment again according to the present invention illustrates;
Fig. 5 B is the part-structure generalized section of the semiconductor electrostatic discharge protector illustrated along the tangent line S5 of Fig. 5 A.
Main device symbol description
100: semiconductor electrostatic discharge protector
101: substrate 101a: substrate surface
102: guard ring
103: metal-oxide semiconductor transistor
103a: grid structure 103b: drain electrode
103c: source electrode 104:P type well region
105: shallow trench isolation structure 106: semiconductor spacer region
107: substrate contact district 108a: conductive contact
108b: conductive contact 109: conductive contact
110: I/o pad 111:P type high-concentration dopant district
200: semiconductor electrostatic discharge protector
206: semiconductor spacer region 207: substrate contact district
300: semiconductor electrostatic discharge protector
306: semiconductor spacer region 307: substrate contact district
400: semiconductor electrostatic discharge protector
403: metal-oxide semiconductor transistor
403a: grid 403b: common drain
403c: source electrode 407: substrate contact district
500: semiconductor electrostatic discharge protector
503: metal-oxide semiconductor transistor
503a: grid 503c: drain electrode
503b: common source 507: substrate contact district
512:N type guard ring S1: tangent line
S2: tangent line S3: tangent line
S4: tangent line S5: tangent line
Embodiment
The present invention is providing a kind of semiconductor electrostatic discharge protector, can reduce leakage current and conduct to ground by element base, promotes the ESD protection of semiconductor electrostatic discharge protector.For above and other object of the present invention, feature and advantage can be become apparent, several preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below.
Please refer to Figure 1A and 1B, Figure 1A is the structure schematic top plan view of the semiconductor electrostatic discharge protector 100 illustrated according to one embodiment of the invention.Figure 1B is the part-structure generalized section of the semiconductor electrostatic discharge protector 100 illustrated along the tangent line S1 of Figure 1A.Wherein, semiconductor electrostatic discharge protector 100 at least comprises one and is formed among semiconductor base 101; and by the second electrical guard ring 102 around the first conductive metal-Oxidc-Semiconductor (Metal-Oxide-Semiconductor, MOS) transistor 103.
Among some embodiments of the present invention, in order to bear sufficiently high static discharge current, semiconductor electrostatic discharge protector 100 generally comprises multiple metal-oxide semiconductor transistor 103 unit.And in order to save shared layout area; on integrated circuit layout; generally semiconductor electrostatic discharge protector 100 is designed to, many finger-like (multi-finger) structure that is made up of the metal-oxide semiconductor transistor 103 of multiple finger-like (as Figure 1A illustrate).
Among some embodiments of the present invention, first electrically can be N-type electrically, and second is electrically that P type is electrical.Such as among the present embodiment, each metal-oxide semiconductor transistor 103, all has a grid structure 103a, a drain electrode 103b and one source pole 103c.Wherein, grid structure 103a comprises, and is positioned at the gate dielectric layer 103a1 on P type trap zone 104 and gate electrode 103a2.Drain electrode 103b is a highly doped doped region (representing with N+), is extended among P type trap zone 104 by the surperficial 101a of substrate 101, and the side of adjoins gate structure 103a.Source electrode 103c is also a highly doped doped region, is extended among P type trap zone 104 by the surperficial 101a of substrate 101, and the opposite side of adjoins gate structure 103a.Guard ring 102, for being extended into a highly dope p-type doped region (representing with P+) of P type trap zone 104 by the surperficial 101a of substrate 101, is used for around these N-type metal-oxide semiconductor transistors 103.
But it should be noted that among other embodiments of the present invention, first is electrically that P type is electrical, and relative second is electrically then that N-type is electrical.That is, among following embodiment, semiconductor electrostatic discharge protector 100 regional electrical and nonspecific.It can along with metal-oxide semiconductor transistor 103 and guard ring 102 the reality select electrically, and to change with making relativity.
In addition, between metal-oxide semiconductor transistor 103 and the second electrical guard ring 102, also comprise a shallow trench isolation structure 105 and semiconductor spacer region 106, and around metal-oxide semiconductor transistor 103.Among some embodiments of the present invention, shallow trench isolation structure 105 extends into dielectric material structure among substrate 101 by the surperficial 101a of substrate 101.Semiconductor spacer region 106 is then the below being positioned at shallow trench isolation structure 105.Among some embodiments of the present invention, semiconductor spacer region 106, then can between shallow trench isolation structure 105 and guard ring 102.And among the present embodiment, semiconductor spacer region 106 is N-type doped regions, extended downwards among substrate 101 by the lower edge of shallow trench isolation structure 105, and around metal-oxide semiconductor transistor 103.
In some embodiments of the invention; source electrode 103c and guard ring 102; respectively by conductive contact 108a and 109 common grounds, and drain electrode 103b is electrically connected with an I/o pad 110 by conductive contact 108b, to provide I/o pad 110 electrostatic discharge (ESD) protection.Due to, each metal-oxide semiconductor transistor 103, being the substrate contact district 107 via comprising a part of substrate 101 being adjacent to P type trap zone 104 and the second electrical guard ring 102, electrically connecting with guard ring 102.Therefore, between source electrode 103c, drain electrode 103b, the second electrical guard ring 102 three, double carriers junction (NPN junction) transistor of a parasitism can be formed.
And the setting of shallow trench isolation structure 105 and semiconductor spacer region 106; just can increase the distance (i.e. the length in substrate contact district 107) between drain electrode 103b and guard ring 102; and then the resistance increased between the emitter-base bandgap grading of parasitic double carriers junction transistor and ground connection base stage; reduce leakage current and conduct to ground by the 103b that drains by substrate contact district 107, to promote the electrostatic discharge (ESD) protection degree of semiconductor electrostatic discharge protector 100.
In addition, in order to promote the resistance between the emitter-base bandgap grading of parasitic double carriers junction transistor and ground connection base stage, in some embodiments of the invention, can also optionally drain electrode 103b below P type trap zone 104 among, one P type high-concentration dopant district 111 is set, makes it have the doping content higher than P type trap zone 104.
It should be noted that the electrical of semiconductor spacer region 106, be not defined as N-type doped region.Such as, please refer to Fig. 2 A and 2B, Fig. 2 A is the structure schematic top plan view of semiconductor electrostatic discharge protector 200 illustrated according to another embodiment of the present invention.Fig. 2 B is the part-structure generalized section of the semiconductor electrostatic discharge protector 200 illustrated along the tangent line S2 of Fig. 2 A.Wherein, semiconductor electrostatic discharge protector 100 structure that semiconductor electrostatic discharge protector 200 and Figure 1A with 1B illustrate is large to identical, and difference is only, semiconductor spacer region 206 is P type light doping sections that doping content is less than P type trap zone 104.
In addition, referring again to Fig. 3 A and 3B, Fig. 3 A be the structure schematic top plan view of semiconductor electrostatic discharge protector 300 illustrated according to still another embodiment of the invention.Fig. 3 B is the part-structure generalized section of the semiconductor electrostatic discharge protector 300 illustrated along the tangent line S3 of Fig. 3 A.Wherein, semiconductor electrostatic discharge protector 100 structure that semiconductor electrostatic discharge protector 300 and Figure 1A with 1B illustrate is also large to identical, and difference is only, semiconductor spacer region 306 is undoped regions.
And no matter be adopt P type lightly doped semiconductor spacer region 306 or undoped semiconductor spacer region 206; the distance (i.e. the length in substrate contact district 207 or 307) increased between drain electrode 103b and guard ring 102 can be reached; and then the resistance increased between the emitter-base bandgap grading of parasitic double carriers junction transistor and ground connection base stage; reduce leakage current and conduct to ground, to promote the electrostatic discharge (ESD) protection degree of semiconductor electrostatic discharge protector 200 or 300 by the 103b that drains by substrate contact district 207 or 307.
In addition, also by changing the wire laying mode of semiconductor electrostatic discharge protector, the effect of the resistance between emitter-base bandgap grading and ground connection base stage increasing parasitic double carriers junction transistor can be reached.Please refer to Fig. 4 A and 4B, Fig. 4 A is the structure schematic top plan view of semiconductor electrostatic discharge protector 300 illustrated according to still another embodiment of the invention.Fig. 4 B is the part-structure generalized section of the semiconductor electrostatic discharge protector 400 illustrated along the tangent line S4 of Fig. 4 A.Wherein, semiconductor electrostatic discharge protector 400 is large to identical with semiconductor electrostatic discharge protector 300 structure that Fig. 3 A with 3B illustrates.Difference is only, the layout type of the metal-oxide semiconductor transistor 403 of semiconductor electrostatic discharge protector 400.
Among some embodiments of the present invention; semiconductor electrostatic discharge protector 400 at least comprises multiple N-type metal-oxide semiconductor transistor 403 with a common drain 403b; and the grid 403a of these first conductive metal-Oxidc-Semiconductor transistor 403 and source electrode 403 form a circulus, around this common drain 403b.Among the present embodiment, grid 403a and the source electrode 403 of four the first conductive metal-Oxidc-Semiconductor transistors 403 form a circulus, around this common drain 403b (see Fig. 4 A).Thus; common drain 403b can be made to be positioned at the side of the first conductive metal-Oxidc-Semiconductor transistor 403 away from guard ring 102; reach the distance (i.e. the length in substrate contact district 407) increased between drain electrode 403b and guard ring 102, increase the effect of the resistance of parasitic double carriers junction transistor emitter-base bandgap grading and ground connection base stage.And then reduce leakage current and conduct to ground, to promote the electrostatic discharge (ESD) protection degree of semiconductor electrostatic discharge protector 400 by the 103b that drains by substrate contact district 407.
According to the structure schematic top plan view of semiconductor electrostatic discharge protector 500 that illustrates of an embodiment more again of the present invention referring again to Fig. 5 A and 5B, Fig. 5 A.Fig. 5 B is the part-structure generalized section of the semiconductor electrostatic discharge protector 500 illustrated along the tangent line S5 of Fig. 5 A.Wherein, the semiconductor electrostatic discharge protector 400 that semiconductor electrostatic discharge protector 500 and Fig. 4 A and 4B illustrate is similar, and difference is only that the layout of metal-oxide semiconductor transistor 503 is different.
Among some embodiments of the present invention, semiconductor electrostatic discharge protector 500 at least comprises a trap contact zone 507, and multiple N-type metal-oxide semiconductor transistor 503.Wherein, trap contact zone 507 is arranged in the trap contact zone 507 of P type trap zone 104, and one end ground connection.And multiple N-type metal-oxide semiconductor transistor 503 has a ring-type common source 503c.In detail, among the present embodiment, four the first conductive metal-Oxidc-Semiconductor transistors 503, grid 503a and the drain electrode 503c of these metal-oxide semiconductor transistors 503 can form a ring type structure, are used for around this ring-type common source 503b.And this ring-type common source 503b, again around the trap contact zone 507 (see Fig. 4 A) of ground connection.Thus, the drain electrode 503c of each metal-oxide semiconductor transistor 503 can be made all away from trap contact zone 507, reach the distance increased between drain electrode 503c and trap contact zone 507, increase the effect of the resistance of parasitic double carriers junction transistor emitter-base bandgap grading and ground connection base stage.And then reduce leakage current and conduct to ground, to promote the electrostatic discharge (ESD) protection degree of semiconductor electrostatic discharge protector 500 by the 503c that drains by trap contact zone 507.
In addition; in order to avoid producing component locking (latch-up) effect, in the present embodiment, better meeting is between guard ring 502 and metal-oxide semiconductor transistor 503; one N-type guard ring 512 is set, and around the first conductive metal-Oxidc-Semiconductor transistor 503.In addition; N-type guard ring 512; simultaneously also can as semiconductor spacer region; be used for increasing the distance between drain electrode 503c and the guard ring 102 of ground connection; and the resistance increased between the emitter-base bandgap grading of parasitic double carriers junction transistor and ground connection base stage, to promote the electrostatic discharge (ESD) protection degree of semiconductor electrostatic discharge protector 500.
According to above-described embodiment; of the present inventionly be to provide a kind of semiconductor electrostatic discharge protector; among one embodiment of the invention, semiconductor electrostatic discharge protector at least comprises: be formed at 1 among element base first conductive crystal pipe, around one second electrical guard ring of the first conductive crystal pipe and the semiconductor spacer region between the first conductive crystal pipe and the second electrical guard ring.Wherein, semiconductor spacer region is undoped region, the first electrical doped region or doping content be less than the second electrical doped region of the second electrical well region.By between the firstth conductive crystal pipe and the second electrical guard ring; the mode of semiconductor spacer region is set; with the distance between the electrical guard ring of drain electrode and second increasing by the first conductive crystal pipe; and then the resistance increased between double carriers junction transistor emitter-base bandgap grading parasitic in semiconductor electrostatic discharge protector and ground connection base stage; reduce leakage current and conduct to ground by draining by element base, and then promote the ESD protection of semiconductor electrostatic discharge protector.
In still another embodiment of the present invention, semiconductor electrostatic discharge protector at least comprises: be formed at the multiple first conductive crystal pipes among element base, around the first conductive crystal pipe the second electrical guard ring and by this few first conductive crystal circumference of cannon bone around trap contact zone.By specific wire laying mode; increase the distance between the drain electrode of the first conductive crystal pipe and trap contact zone; and then the resistance increased between double carriers junction transistor emitter-base bandgap grading parasitic in semiconductor electrostatic discharge protector and ground connection base stage; reduce leakage current and conduct to ground by draining by trap contact zone, and then promote the ESD protection of semiconductor electrostatic discharge protector.
Although disclose the present invention in conjunction with above preferred embodiment, however itself and be not used to limit the present invention.Be familiar with this operator in this field any, without departing from the spirit and scope of the present invention, a little change and retouching can be done.What therefore protection scope of the present invention should define with the claim of enclosing is as the criterion.
Claims (14)
1. a semiconductor electrostatic discharge protector, comprising:
The first transistor has first electrically, is formed among one second electrical well region;
Second electrical guard ring, around this first transistor; And
Semiconductor spacer region, between this first transistor and this second electrical guard ring, and around this first transistor, and this semiconductor spacer region be undoped region, the first electrical doped region or doping content be less than the second electrical doped region of this second electrical well region.
2. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises shallow trench isolation structure, between this first transistor and this second electrical guard ring; Wherein this semiconductor spacer region is positioned at below this shallow trench isolation structure.
3. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises shallow trench isolation structure, between this first transistor and this second electrical guard ring; Wherein this semiconductor spacer region is between this shallow trench isolation structure and this second electrical guard ring.
4. semiconductor electrostatic discharge protector as claimed in claim 1, wherein this first be electrically that N-type is electrical, and this second electrical be that P type is electrical.
5. semiconductor electrostatic discharge protector as claimed in claim 1, wherein this first be electrically that P type is electrical, and this second electrical be that N-type is electrical.
6. semiconductor electrostatic discharge protector as claimed in claim 1, wherein this first transistor comprises:
Grid structure, is formed on this second electrical well region;
Source electrode, is formed among this second electrical well region, and this grid structure adjacent;
Drain electrode, is formed among this second electrical well region, and this grid structure adjacent; And
Second electrical high-concentration dopant district, is positioned among this second electrical well region below this drain electrode, and has the doping content higher than this second electrical well region.
7. semiconductor electrostatic discharge protector as claimed in claim 6, also comprises substrate contact district (body contact), is adjacent to this second electrical well region and this second electrical guard ring, and with this source electrode common ground; And this drain electrode is electrically connected with an I/o pad (I/O pad).
8. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises:
Transistor seconds, has that this is first electrical; And
Third transistor, has that this is first electrical;
Wherein, this first transistor, this transistor seconds and this third transistor have a common drain.
9. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises:
Trap contact zone (well pick-up region), is formed among this second electrical well region
Transistor seconds, has that this is first electrical; And
Third transistor, has that this is first electrical;
Wherein, this first transistor, this transistor seconds and this third transistor have a ring-type common source, around this trap contact zone.
10. a semiconductor electrostatic discharge protector, comprising:
Multiple first conductive crystal pipe;
Second electrical guard ring, around those the first conductive crystal pipes; And
Trap contact zone, wherein those the first conductive crystal pipes, around this trap contact zone.
11. semiconductor electrostatic discharge protectors as claimed in claim 10, also comprise one first electrical guard ring, between those the first conductive crystal pipes and this second electrical guard ring, and around those the first conductive crystal pipes.
12. semiconductor electrostatic discharge protectors as claimed in claim 10, wherein each those the first conductive crystal pipe comprises:
Grid structure, is formed on one second electrical well region;
Drain electrode, is formed among this second electrical well region, and this grid structure adjacent is away from the side of this trap contact zone; And
Source electrode, is formed among this second electrical well region, and this grid structure adjacent is near the side of this trap contact zone.
13. semiconductor electrostatic discharge protectors as claimed in claim 12, wherein this trap contact zone and this source electrode common ground, and this drain electrode is electrically connected with an I/o pad.
14. semiconductor electrostatic discharge protectors as claimed in claim 12; wherein each those the first conductive crystal pipe also comprises one second electrical high-concentration dopant district; be positioned among this second electrical well region below this drain electrode, and there is the doping content higher than this second electrical well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310628550.3A CN104681542A (en) | 2013-11-29 | 2013-11-29 | Semiconductor electrostatic discharge protection device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310628550.3A CN104681542A (en) | 2013-11-29 | 2013-11-29 | Semiconductor electrostatic discharge protection device |
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| CN104681542A true CN104681542A (en) | 2015-06-03 |
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| CN201310628550.3A Pending CN104681542A (en) | 2013-11-29 | 2013-11-29 | Semiconductor electrostatic discharge protection device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304625A (en) * | 2015-10-30 | 2016-02-03 | 北京时代民芯科技有限公司 | SRAM type FPGA double-array-hole electrostatic discharge protection layout structure for aerospace |
| CN106328648A (en) * | 2015-07-03 | 2017-01-11 | 台湾类比科技股份有限公司 | Integrated circuit and self-protection output buffer |
| CN111326568A (en) * | 2020-03-10 | 2020-06-23 | 苏州晶界半导体有限公司 | Nitride device with guard ring structure |
| CN113097181A (en) * | 2019-12-23 | 2021-07-09 | 南亚科技股份有限公司 | Semiconductor structure |
-
2013
- 2013-11-29 CN CN201310628550.3A patent/CN104681542A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328648A (en) * | 2015-07-03 | 2017-01-11 | 台湾类比科技股份有限公司 | Integrated circuit and self-protection output buffer |
| CN105304625A (en) * | 2015-10-30 | 2016-02-03 | 北京时代民芯科技有限公司 | SRAM type FPGA double-array-hole electrostatic discharge protection layout structure for aerospace |
| CN113097181A (en) * | 2019-12-23 | 2021-07-09 | 南亚科技股份有限公司 | Semiconductor structure |
| CN113097181B (en) * | 2019-12-23 | 2024-03-22 | 南亚科技股份有限公司 | Semiconductor structure |
| CN111326568A (en) * | 2020-03-10 | 2020-06-23 | 苏州晶界半导体有限公司 | Nitride device with guard ring structure |
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Application publication date: 20150603 |