CN104679565B - The programming system and method for flash memory in a kind of optical communication equipment production - Google Patents
The programming system and method for flash memory in a kind of optical communication equipment production Download PDFInfo
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Abstract
The programming system and method for flash memory in a kind of optical communication equipment production, it is related to optical communication equipment production technical field, the system includes board management unit buckle and ARM equipment, the ARM equipment includes string line debugging interface and ARM chips, and the board management unit buckle is connected by string line with string line debugging interface；The ARM chips include high performance bus access interface, kernel, high-performance interconnected bus and memory, wherein, the high performance bus access interface is connected by debugging access interface bus with string line debugging interface, and the high-performance interconnected bus is connected with high performance bus access interface, kernel and memory respectively.Present invention saves equipment and reduce production cost；Improve production efficiency；Solve the problems, such as maloperation and emulation downloader damage.
Description
Technical field
The present invention relates to optical communication equipment production technical field, is specifically flash memory in a kind of optical communication equipment production
Programming system and method.
Background technology
At present, all ARM of optic communication manufacturing enterprise (Advanced RISC Machines) chip application software program
FLASH (flash memory) programming uses PC and emulation downloader (such as JLINK emulation downloader) to carry out, and concrete mode is to pass through
Downloading wire inserts JTAG (Joint Test Action Group, joint test working group) winding displacement mouth, with reference to Software tool (example
Such as J-FLASH ARM Software tools) carry out flash memory program burn writing.
However, because traditional programming process is larger to PC and emulation downloader demand, cause cost higher；And
, it is necessary to which the artificial emulation downloader of plug repeatedly, has a strong impact on operating efficiency during ARM chip application program escalation process；In addition, survey
When examination personnel carry out the operation of flashburn tools by PC, man-machine interaction is more and without foolproof function, causes easily to occur grasping by mistake
The problem of making and emulating downloader damage.
The content of the invention
For defect present in prior art, flash memory in being produced it is an object of the invention to provide a kind of optical communication equipment
Programming system and method, present invention saves equipment and reduce production cost；Improve production efficiency；Solves maloperation
And the problem of emulation downloader damage.
To achieve the above objectives, the present invention adopts the technical scheme that：The programming of flash memory in a kind of optical communication equipment production
System, including board management unit buckle and ARM equipment, the ARM equipment includes string line debugging interface and ARM chips, described
Board management unit buckle is connected by string line with string line debugging interface；The ARM chips include high performance bus access and connect
Mouth, kernel, high-performance interconnected bus and memory, wherein, the high performance bus access interface is connect by debugging access
Mouthful bus is connected with string line debugging interface, the high-performance interconnected bus respectively with high performance bus access interface, interior
Core and memory are connected.
On the basis of above-mentioned technical proposal, the string line debugging interface includes string line clock port, serial line number
According to input/output port, reset pin；The board management unit buckle includes the first I/O port, the second I/O port, the 3rd I/O port；It is described
String line clock port is connected with the first I/O port, and string line data input output ports are connected with the second I/O port, reset pin with
3rd I/O port is connected.
On the basis of above-mentioned technical proposal, the board management unit buckle also includes 3V3 pins and the first GND pin,
ARM equipment also includes VCC pin and the second GND pin；Wherein, the 3V3 pins are connected with VCC pin, the first GND pin and
Second GND pin is connected.
On the basis of above-mentioned technical proposal, the high performance bus access interface includes control and status word register,
Direction of transfer, transmission size and transmission type for control data；Transmit address register, the transmission for director data
Address；Data read/write register, for depositing or storing the data transmitted.
On the basis of above-mentioned technical proposal, the ARM chips also include authentication code register, for providing relevant string
The identification information of line debugging interface；Stop register, for forcing DAP to stop and removing mistake and adhesive tape flag condition；
Control/status register, for providing the control to string line debugging interface and the state letter about string line debugging interface
Breath；Debugging management status register is diagnosed, for providing system safety, flash memory erasing starts, acknowledgement state information；Diagnosis debugging
Control register is managed, for providing system debug request, control debugging is forbidden, control flash memory erasing；Debugging stop control and
Status register, for providing the information about ARM chip status, kernel tailoring is enabled, realize that ARM chips stop and single step is grasped
Make；Debugging is abnormal and monitors control register, for debugging monitoring control.
The present invention also provides a kind of programming method of flash memory in optical communication equipment production based on said system, the ARM
Equipment includes authentication code register, stops register, control/status register, diagnosis debugging management status register, diagnosis
Debugging management control register；This method comprises the following steps：Step S1. initializes each I/O port of board management unit buckle；Step
Rapid S2. carries out ARM chip resets, and ARM chips are converted into SWD patterns by JTAG mode；Step S3. is posted by authentication code
The authentication code of storage reading device；Step S4. sets the error flag for clearly stopping register；Step S5. is controlled by setting
System/status register, enabled systems power-up request and debugging power-up request；Step S6. is according to diagnosis debugging management Status register
Device judges whether ARM chips flash memory is encrypted, if so, then going to step S7；If it is not, then go to step S8；Step S7. passes through diagnosis
Debugging management control register performs overall erasing operation, carries out the decryption processing of ARM chips；Step S8. is stopped by debugging
Control and status register enable the DEBUG patterns of ARM chips, are then called by debugging abnormal and monitoring control register
ARM chips, it is set to handle halted state；Step S9. performs the flash memory initialization of ARM chips, is wiped and programming function, complete
Into the ARM chip flash memory programmings of specified application file.
On the basis of above-mentioned technical proposal, the string line debugging interface includes string line clock port, serial line number
According to input/output port, reset pin；The board management unit buckle includes the first I/O port, the second I/O port, the 3rd I/O port；It is described
String line clock port is connected with the first I/O port, and string line data input output ports are connected with the second I/O port, reset pin with
3rd I/O port is connected.
On the basis of above-mentioned technical proposal, in step S1, each I/O port of initialization board management unit buckle is specially just
The I/O port of beginningization first exports, and the 3rd I/O port output, the second I/O port switches over as data input output.
On the basis of above-mentioned technical proposal, in step S2, ARM chip resets are carried out by the 3rd I/O port；Pass through first
I/O port, the second I/O port send default value sequence, and ARM chips are converted into SWD patterns by JTAG mode.
The beneficial effects of the present invention are：
1st, BMU (board management unit) buckles in the present invention pass through string line and the string line debugging interface phase of ARM equipment
Even, therefore without using downloading emulator, you can by the I/O ports of BMU buckles simulate SWD (Serial Wire Debug, serially
Line debugs agreement) agreement, the programming that application program is carried out to ARM chips flash memory is realized, equipment has been saved and has reduced and be produced into
This.
2nd, without using downloading emulator in the present invention, therefore in ARM chip application program escalation process, it is not necessary to people
Work plugs emulation downloader repeatedly, avoids the damage of emulation downloader, it is not necessary to and manual operation configures special programming software,
Save production cost and improve production efficiency again.
3rd, without using downloading emulator in the present invention, therefore during tester's progress programming operation, in the absence of man-machine friendship
Mutually, maloperation and emulation downloader damage are solved the problems, such as.
Brief description of the drawings
Fig. 1 is the hardware connection figure of the programming system of flash memory in optical communication equipment of the present invention production；
Fig. 2 is the theory diagram of the programming system of flash memory in optical communication equipment of the present invention production；
Fig. 3 is the programming method flow diagram of flash memory in optical communication equipment of the present invention production.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
It is shown in Figure 1, the programming system of flash memory in a kind of optical communication equipment production, including BMU buckles and ARM equipment,
The ARM equipment includes SW-DP (string line debugging interface) and ARM chips, and the BMU buckles pass through SW lines (string line) and string
Line debugging interface is connected；The string line debugging interface includes SWD_TCK (string line clock port), SWD_DIO (string lines
Data input output ports), NRST (reset pin)；The BMU buckles include the first I/O port, the second I/O port, the 3rd I/O port；Institute
State string line clock port with the first I/O port to be connected, string line data input output ports are connected with the second I/O port, reset pin
It is connected with the 3rd I/O port.Preferably, the BMU buckles also include 3V3 pins and the first GND pin, and ARM equipment also includes VCC
Pin and the second GND pin；Wherein, the 3V3 pins are connected with VCC pin, and the first GND pin and the second GND pin are connected.
Referring to shown in Fig. 1 and Fig. 2, the ARM chips include AHB-AP (high performance bus access interface), kernel, Gao Xing
Energy interconnected bus (AHB) and memory, wherein, by DAP buses, (debugging access connects the high performance bus access interface
Mouthful bus) be connected with string line debugging interface, the high-performance interconnected bus respectively with high performance bus access interface, interior
Core and memory are connected.
The high performance bus access interface includes CSW registers (control and status word register), for control data
Direction of transfer, transmission size and transmission type；TAR registers (transmission address register), the transmission for director data
Address；DRW registers (data read/write register), for depositing or storing the data transmitted.Due to the storage of RAM chip
For device not in internal memory addressing range, the kernel of outside BMU buckles and ARM chips can not directly access the memory of ARM chips,
Memory can only be accessed by high-performance interconnected bus.And during the memory of BMU buckles access ARM chips, pass through string
External signal is converted into DAP bus signals by line, then by high performance bus access interface, is passed by transmitting address register
Send IA, the data to be read and write of data read/write register transfer, control and the status word register transmission direction to be needed
Debugging access interface bus signals are converted into high-performance interconnected bus after (read/write), size of data and data type
On data transmission, the memories of ARM chips is accessed by high-performance interconnected bus.
The ARM chips also include IDCODE registers (authentication code register), for providing relevant string line debugging
The identification information of interface；ABORT registers (termination register), for forcing DAP to stop and removing mistake and adhesive tape mark
Condition；CTRL/STAT registers (control/status register), for providing control to string line debugging interface and relevant
The status information of string line debugging interface；MDM-AP Status register registers (diagnosis debugging management Status register
Device), for providing system safety, flash memory erasing starts, acknowledgement state information；MDM-AP Control Register registers
(diagnosis debugging management control register), for providing system debug request, control debugging is forbidden, control flash memory erasing；DHCSR
Register (debugging stops control and status register), for providing the information about ARM chip status, enables kernel tailoring,
Realize the stopping of ARM chips and single -step operation；DEMCR registers (debugging is abnormal and monitors control register), are monitored for debugging
Control.
It is shown in Figure 3, the programming method of flash memory in the optical communication equipment production based on said system, including following step
Suddenly：
Step S1. initializes each I/O port of BMU buckles；Specifically, each I/O port of initialization BMU buckles is specially to initialize
First I/O port exports, and the 3rd I/O port output, the second I/O port switches over as data input output.
Step S2. carries out ARM chip resets, and ARM chips are converted into SWD patterns by JTAG mode；Specifically, pass through
3rd I/O port carries out ARM chip resets；Default value sequence (0xE79E sequences) is sent by the first I/O port, the second I/O port, will
ARM chips are converted into SWD patterns by JTAG mode.
The authentication code that step S3. passes through authentication code register reading device.
Step S4. sets the error flag for clearly stopping register.
Step S5. is by setting control/status register, enabled systems power-up request and debugging power-up request.
Step S6. judges whether ARM chips flash memory is encrypted according to diagnosis debugging management status register, if so, then going to
Step S7；If it is not, then go to step S8.
Step S7. performs overall erasing operation by diagnosing debugging management control register, at the decryption for carrying out ARM chips
Reason.
Step S8. stops the DEBUG patterns of control and the enabled ARM chips of status register by debugging, and then passes through tune
Examination is abnormal and monitoring control register calls ARM chips, it is handled halted state.
Step S9. performs the flash memory initialization of ARM chips, is wiped and programming function, completion specified application are literary
The ARM chip flash memory programmings of part.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
On the premise of the principle of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as the protection of the present invention
Within the scope of.The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Claims (7)
1. the programming system of flash memory in a kind of optical communication equipment production, including board management unit buckle and ARM equipment, its feature exist
In：The ARM equipment includes string line debugging interface and ARM chips, and the board management unit buckle is by string line and serially
Line debugging interface is connected；
The ARM chips include high performance bus access interface, kernel, high-performance interconnected bus and memory, wherein, institute
State high performance bus access interface and be connected by debugging access interface bus with string line debugging interface, the high-performance internal mutual
Connection bus is connected with high performance bus access interface, kernel and memory respectively；
The string line debugging interface includes string line clock port, string line data input output ports, reset pin；It is described
Board management unit buckle includes the first I/O port, the second I/O port, the 3rd I/O port；The string line clock port and the first I/O port phase
Even, string line data input output ports are connected with the second I/O port, and reset pin is connected with the 3rd I/O port.
2. the programming system of flash memory in optical communication equipment production as claimed in claim 1, it is characterised in that：The board management list
First buckle also includes 3V3 pins and the first GND pin, and ARM equipment also includes VCC pin and the second GND pin；Wherein, it is described
3V3 pins are connected with VCC pin, and the first GND pin and the second GND pin are connected.
3. the programming system of flash memory in optical communication equipment production as claimed in claim 1, it is characterised in that：The high-performance is total
Line access interface includes
Control and status word register, direction of transfer, transmission size and transmission type for control data；
Transmit address register, the transfer address for director data；
Data read/write register, for depositing or storing the data transmitted.
4. the programming system of flash memory in optical communication equipment production as claimed in claim 1, it is characterised in that：The ARM chips
Also include
Authentication code register, for providing the identification information about string line debugging interface；
Stop register, for forcing DAP to stop and removing mistake and adhesive tape flag condition；
Control/status register, for providing the control to string line debugging interface and the shape about string line debugging interface
State information；
Debugging management status register is diagnosed, for providing system safety, flash memory erasing starts, acknowledgement state information；
Debugging management control register is diagnosed, for providing system debug request, control debugging is forbidden, control flash memory erasing；
Debugging stops control and status register, for providing the information about ARM chip status, enables kernel tailoring, realizes
ARM chips stop and single -step operation；
Debugging is abnormal and monitors control register, for debugging monitoring control.
5. the programming method of flash memory in the optical communication equipment production based on system described in claim 1, it is characterised in that described
ARM equipment include authentication code register, stop register, control/status register, diagnosis debugging management status register,
Diagnose debugging management control register；This method comprises the following steps：
Step S1. initializes each I/O port of board management unit buckle；
Step S2. carries out ARM chip resets, and ARM chips are converted into SWD patterns by JTAG mode；
The authentication code that step S3. passes through authentication code register reading device；
Step S4. sets the error flag for clearly stopping register；
Step S5. is by setting control/status register, enabled systems power-up request and debugging power-up request；
Step S6. judges whether ARM chips flash memory is encrypted according to diagnosis debugging management status register, if so, then going to step
S7；If it is not, then go to step S8；
Step S7. performs overall erasing operation by diagnosing debugging management control register, carries out the decryption processing of ARM chips；
Step S8. stops the DEBUG patterns of control and the enabled ARM chips of status register by debugging, then different by debugging
Often and monitoring control register calls ARM chips, its is handled halted state；
Step S9. performs the flash memory initialization of ARM chips, is wiped and programming function, completes specified application file
ARM chip flash memory programmings.
6. the programming method of flash memory in optical communication equipment production as claimed in claim 5, it is characterised in that：In step S1, just
Each I/O port of beginningization board management unit buckle is specially to initialize the output of the first I/O port, the output of the 3rd I/O port, the second I/O port conduct
Data input output switches over.
7. the programming method of flash memory in optical communication equipment production as claimed in claim 5, it is characterised in that：In step S2, lead to
Cross the 3rd I/O port and carry out ARM chip resets；By the first I/O port, the second I/O port send default value sequence, by ARM chips by
JTAG mode is converted into SWD patterns.
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| CN201510109917.XA CN104679565B (en) | 2015-03-12 | 2015-03-12 | The programming system and method for flash memory in a kind of optical communication equipment production |
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| US20040049617A1 (en) * | 2002-09-05 | 2004-03-11 | Integrated Circuit Solution Inc. | Method of firmware update by USB interface |
| TWM328039U (en) * | 2007-08-16 | 2008-03-01 | Inventec Appliances Corp | Flash memory burner |
| CN103677885B (en) * | 2012-09-21 | 2019-03-05 | 厦门雅迅网络股份有限公司 | A kind of method of ARM FLASH simple program programming |
| CN103838585A (en) * | 2012-11-20 | 2014-06-04 | 广州市暨华医疗器械有限公司 | Method for achieving automatic recording of ARM9 embedded system based on SD card |
| CN203982359U (en) * | 2014-06-27 | 2014-12-03 | 国家电网公司 | Can connect the FLASH program burn writing device of multiple modules simultaneously |
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