WO2016184170A1 - Smi interface device debugging apparatus and method, and storage medium - Google Patents

Smi interface device debugging apparatus and method, and storage medium Download PDF

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Publication number
WO2016184170A1
WO2016184170A1 PCT/CN2016/073096 CN2016073096W WO2016184170A1 WO 2016184170 A1 WO2016184170 A1 WO 2016184170A1 CN 2016073096 W CN2016073096 W CN 2016073096W WO 2016184170 A1 WO2016184170 A1 WO 2016184170A1
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Prior art keywords
interface
smi
processor
instruction
level
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PCT/CN2016/073096
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French (fr)
Chinese (zh)
Inventor
付玉堂
段向阳
封葳
庞辉
王雪松
王文静
黄翔
黄瑞华
王玺
曾凯平
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中兴通讯股份有限公司
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Publication of WO2016184170A1 publication Critical patent/WO2016184170A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3852—Converter between protocols

Definitions

  • the present invention relates to communications technologies, and in particular, to a debugging apparatus and method for an SMI interface device, and a storage medium.
  • SMI Serial Management Interface
  • BBU baseband processing unit
  • the current debugging method is controlled by a CPU connected to the device of the SMI interface in the board, and a software program of the CPU needs to be written for processing.
  • a software program of the CPU needs to be written for processing.
  • the writing of the software is complicated due to the difference of the registers of the CPU and the SMI interface device, and the cycle is also increased. If there is a problem during the debugging process, the program needs to be modified to locate the fault point. Will reduce development efficiency.
  • SMI interface management method and programmable logic device including: SMI interface register, and the SMI interface connected thereto The transceiver and the decoder; the SMI interface register is connected to the processor CPU via the bus; the SMI interface of the SMI interface transceiver expands the main SMI interface with the same number of managed SMI interface devices through the decoder;
  • the main SMI interface uses two I/O pins of the PLD, each of which is connected to a slave SMI interface device; the main SMI interface for different level applications is located in a different logical area of the I/O group of the input and output ports of the PLD.
  • the I/O pins of each BANK are set to The level mode of the same level of the main SMI interface in BANK.
  • This method is suitable for use in the design of a single board. It is used to manage multiple SMI interface devices in the board.
  • the logic device PLD is not added for transfer, but the SMI interface is directly powered. After the flat match, it is hung on the SMI interface bus of the CPU, and the solution described in the patent cannot avoid complicated program development and cycle in debugging, and cannot quickly locate the fault, and the actual R&D efficiency is not significantly improved.
  • the debugging mode of the existing SMI interface device is limited by the development of the CPU debugger, which not only affects the R&D efficiency of the SMI interface device, but also fails to quickly locate the fault of the SMI interface device in the debug mode.
  • Embodiments of the present invention provide a debugging apparatus and method for an SMI interface device.
  • a debugging apparatus for an SMI interface device includes: a PC interface, a processor, and an SMI cable interface;
  • the processor is configured to receive an instruction sent by the host computer that accesses the debugging device by using the PC interface, convert the instruction into SMI format data, and send the SMI format data to the through-simulated SMI interface.
  • the SMI cable interface is connected to the debugged SMI interface device of the debugging device; and receives information fed back by the debugged SMI interface device after executing the command through the simulated SMI interface, parses the information, and extracts useful information. Send it to the host computer.
  • an interface conversion is arranged between the PC interface and the processor.
  • the chip is used to implement the conversion of the interface supported by the processor to the PC interface and the interface supported by the PC interface to the processor.
  • the debugging apparatus of the present invention further includes: a level matching module disposed between the processor and the SMI cable interface, configured to be debugged by the SMI interface When the device is connected to the debugging device through the SMI cable interface, detecting an interface level of the debugged SMI interface device, and leveling a signal between the processor and the debugged SMI interface device Conversion.
  • a level matching module disposed between the processor and the SMI cable interface, configured to be debugged by the SMI interface When the device is connected to the debugging device through the SMI cable interface, detecting an interface level of the debugged SMI interface device, and leveling a signal between the processor and the debugged SMI interface device Conversion.
  • the level matching module specifically includes: a level detecting unit and a level converting unit;
  • the level detecting unit is configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and report the detection result to the The processor;
  • the level conversion unit includes: an analog switch and a plurality of voltage dividing resistor networks;
  • Each of the voltage dividing resistor networks divides a level supported by the processor to obtain a level required by different SMI interface devices;
  • the analog switch is configured to gate a voltage divider resistor network corresponding to an interface level of the debugged SMI interface device for level conversion and transmission of signals based on control of the processor.
  • the processor simulates the SMI interface by simulating the communication interface used by the processor as a clock signal interface and a simulation as a data interface.
  • the type of the instruction sent by the upper computer includes: a read register instruction and a write register instruction;
  • the instruction When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
  • a method for debugging an SMI interface device including:
  • the processor converts the instructions of the host computer passed to the PC interface side into the number of SMI formats. according to;
  • the processor parses the received information, extracts the useful information, and sends the information to the upper computer through the PC interface.
  • the method before the debugging, the method further includes: detecting, when the debugged SMI interface device accesses the debugging device through the SMI cable interface, detecting the debugged SMI interface device An interface level, the level shifting branch is selected according to an interface level of the debugged SMI interface device, such that the level shifting branch is to the processor and the debugged SMI interface device during debugging The signals that interact between are level shifted.
  • the analog SMI interface is implemented by the processor by simulating a communication interface used by the processor as a clock signal interface and a channel simulation as a data interface.
  • the instruction type of the upper computer includes: a read register instruction and a write register instruction;
  • the instruction When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
  • the SMI interface device can be directly debugged by the instruction of the host computer (such as register read and write operations), and when the program of the CPU control program is not written or the program is written, It can be easily debugged, and this debugging method helps to quickly locate faults and significantly improves hardware development efficiency.
  • FIG. 1 is a structural block diagram of a debugging apparatus for an SMI interface device according to Embodiment 1 of the present invention
  • FIG. 2 is a structural block diagram of a debugging apparatus for an SMI interface device according to Embodiment 2 of the present invention
  • FIG. 3 is a schematic circuit diagram of a level matching module according to Embodiment 2 of the present invention.
  • FIG. 5 is a flowchart of a method for debugging an SMI interface device according to Embodiment 3 of the present invention.
  • the embodiment of the invention provides a debugging device for an SMI interface device.
  • the device includes: a PC interface, a processor, and an SMI cable interface; wherein:
  • a PC interface configured to access the host computer
  • the SMI cable interface is configured to access the debugged SMI interface device
  • a processor configured to receive, sent by the host computer that accesses the debugging device by using the PC interface Directing, converting the instruction into SMI format data, and transmitting the SMI format data to the debugged SMI interface device connected to the debug device through the SMI cable interface through the analog SMI interface; and passing the simulated SMI
  • the interface receives the information fed back by the debugged SMI interface device after executing the instruction, parses the information, extracts the useful information, and sends the information to the upper computer.
  • the processor simulates the SMI interface by simulating the communication interface used by the processor as a clock signal interface and a simulation as a data interface.
  • the communication interface includes but is not limited to being an IO interface.
  • the type of the instruction sent by the host computer includes: a read register instruction and a write register instruction; when the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register When the instruction is executed, the instruction contains the data written to the register and the address information of the register.
  • an interface conversion chip is disposed between the PC interface and the processor, It is used to implement the conversion of the interface supported by the processor to the PC interface and the interface supported by the PC interface to the processor.
  • the processor and the A level matching module is disposed between the SMI cable interfaces;
  • the level matching module is configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device of the embodiment through the SMI cable interface, and A signal is exchanged between the processor and the signal being exchanged between the debugged SMI interface device.
  • the level matching module includes: a level detecting unit and a level converting unit; wherein:
  • a level detecting unit configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and report the detection result to the processor
  • a level shifting unit comprising: an analog switch and a plurality of voltage dividing resistor networks;
  • Each of the voltage dividing resistor networks divides a level supported by the processor to obtain a level required by different SMI interface devices;
  • the analog switch is configured to gate a voltage divider resistor network corresponding to an interface level of the debugged SMI interface device for level conversion and transmission of signals based on control of the processor.
  • the structure of the level matching module described in this embodiment is only one of a plurality of level conversion schemes that can be implemented, and the present invention does not uniquely limit the structure, as long as it can implement a scheme for converting between different levels. All are within the scope of the protection idea of the present invention.
  • the debugging apparatus described in this embodiment can directly send the instruction of the upper computer to the SMI interface device to perform debugging of the device, and realize that when there is no problem in programming the CPU control program or writing the program,
  • the technology can also be conveniently debugged.
  • the SMI interface device can be conveniently debugged, when the SMI interface device fails, the host computer can quickly locate the fault according to the debugging information. Improve the efficiency of hardware development.
  • the embodiment of the present invention provides a debugging device for an SMI interface device.
  • the debugging device is implemented by using a single chip microcomputer system as a processor.
  • the debugging device of the SMI interface device in this embodiment is shown in FIG. 2 .
  • the type of the PC interface is usually a USB interface or an RS232 interface, and the PC interface is an external interface of the upper computer connected to the debugging device;
  • the interface conversion chip is disposed between the PC interface and the single chip system, and can realize the conversion function of the UART interface supported by the single chip system to the USB/RS232 interface;
  • the single chip microcomputer system receives the instruction information sent by the upper computer transmitted by the PC interface and the interface conversion chip; extracts the instruction information, and generates the SMI format data according to the SMI protocol; further, the single chip system can realize the SMI
  • the simulation of the SMI interface is implemented in advance by software to transmit the SMI format data to the level matching module through the analog SMI interface.
  • the analog mode of the SMI interface can be: Assume that the level matching module and the single chip system are directly connected through the IO port. Then, the single chip system needs to provide an analog SMI interface through the IO port. Specifically, the single chip system is used as the main device to connect the IO port. One way of simulation is the clock signal interface, and the other is analog data interface, which realizes the simulation of the SMI interface.
  • the functions of the level matching module include functions before debugging and functions during debugging;
  • the function before debugging includes: detecting the interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debug device through the SMI cable interface, according to the interface level of the debugged SMI interface device , select the level shifting branch;
  • the functions in the debugging process include: level shifting the signals exchanged between the single chip system and the debugged SMI interface device during the debugging process based on the level shifting branch selected before the debugging.
  • the structure of the level matching module is as shown in FIG. 3, including: a level detecting unit and a level converting unit, and the level converting unit includes two sets of analog switches and two sets of four.
  • the voltage divider resistor network realizes that the debugging device is directly connected to the SMI interface devices of different levels through the structure, and realizes plug and play.
  • 4 are only parameters in a specific application example, and those skilled in the art can increase or decrease according to requirements.
  • the level detecting unit is connected to the single chip system, and is configured to be used when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and the debugged SMI interface device The interface level of the device is detected, and the detection result is reported to the single chip microcomputer system;
  • the four voltage divider resistor networks can divide the TTL level of 5V supported by the MCU system to obtain the required level of different SMI interface devices. For example, 5V to 5V, 3.3V, and 2.5 can be realized through 4 voltage divider resistor networks. V, 1.8V.
  • the MCU system consists of four IO pins, which are respectively connected to two 2-way strobe control pins of the analog switch.
  • the MCU system controls the analog switch to realize two sets of four-selection functions according to the level information reported by the level detection unit.
  • the two sets of optional interfaces of the switch are respectively connected to one of the four voltage divider resistor networks to achieve 5V to 5V, 3.3V, 2.5V or 1.8V. Among them, the selected two sets of lines, one for transmitting clock signals and one for transmitting data.
  • the SMI cable interface is connected to the tested SMI interface device through a pin header or a test point.
  • the SMI cable interface is three wires, which are a clock signal line, a data signal line, and a power ground line.
  • the debugging device is connected to the host computer through the PC interface, and is connected to the corresponding SMI interface device to be debugged through the SMI cable interface, and then, the single chip system detects the SMI interface according to the level detecting unit in the level matching module.
  • the interface level value of the device, the analog switch in the automatic control level matching module selects the corresponding voltage divider resistor network for level matching.
  • the MCU system starts to receive the instruction of the host computer, and determines whether it is a read operation or a write operation and a register address and data through data analysis. If it is a read operation, the MCU system processes the data and communicates with the debugged SMI interface device through the analog SMI interface to read the data of the corresponding register. If it is a write operation, the microcontroller system processes the register address and the data to be written, and then operates the corresponding register of the debugged SMI interface device through the analog SMI interface.
  • the process information of the above process is shown in FIG. 4 .
  • the implementation process of the write operation to the register is as follows:
  • the PC interface of the debugging device receives the write to the SMI interface device register sent by the host computer. Data and register address information, and send the received information to the interface conversion chip;
  • the interface conversion chip converts the PC interface into a UART interface, so as to transmit information transmitted by the PC interface to the single chip system;
  • the single chip system After receiving the information sent by the interface conversion chip, the single chip system extracts the register address and the data written into the register, and generates the SMI format data according to the SMI protocol format, and sends the SMI format data to the simulated SMI interface to the SMI interface.
  • Level matching module
  • the level matching module performs level conversion on the received signal and sends it to the debugged SMI interface device through the SMI cable interface, thereby realizing the write operation of the register.
  • the MCU system receives the register address sent by the host computer software and the data to be written through the interface conversion chip and the PC interface.
  • the MCU system parses the received command, extracts the register-related data, and then passes the simulated SMI.
  • the interface writes data to the specified register for write operations.
  • the process of reading the register is as follows:
  • the PC interface of the debugging device receives the register address information of the data in the read register sent by the host computer, and sends the information to the interface conversion chip;
  • the interface conversion chip converts the PC interface into a UART interface, so as to transmit information transmitted by the PC interface to the single chip system;
  • the single chip system After receiving the information sent by the interface conversion chip, the single chip system extracts the register address information, and generates the SMI format data according to the SMI protocol format, and sends the SMI format data to the level matching module through the analog SMI interface;
  • the level matching module performs level conversion on the received signal and sends it to the debugged SMI interface device through the SMI cable interface to read the data of the register in the SMI interface device;
  • the SMI cable interface sends data of the read register sent by the SMI interface to the level matching module
  • the level matching module performs level conversion on the received signal and sends it to the single chip system
  • the single chip system extracts the data of the register in the information according to the clock signal, and sends the extracted data to the interface conversion chip;
  • the interface conversion chip converts the UART interface into a PC interface, and sends the data extracted by the single-chip microcomputer system to the PC interface, and then sends the data to the upper computer through the PC interface.
  • the MCU system first receives the information of the register that needs to read data from the host computer, and then the MCU system obtains the specified register data of the device through the SMI interface, and processes the data through the UART interface after the data extraction and conversion process.
  • Chip to PC interface complete data communication with the host computer. That is, the read operation of the register is realized.
  • the embodiment of the invention provides a debugging method for implementing an SMI interface device by using the debugging device according to the first embodiment or the second embodiment. As shown in FIG. 5, the method includes:
  • Step S501 when debugging, the processor converts the instruction of the host computer transmitted from the PC interface side into SMI format data
  • the instruction type of the upper computer includes: a read register instruction and a write register instruction;
  • the instruction When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
  • Step S502 the processor sends the SMI format data to the SMI cable interface through the simulated SMI interface, to send the SMI format data to the debugged SMI interface device by using the SMI cable interface;
  • the analog SMI interface is preferably implemented by the processor by simulating a communication interface used by the processor as a clock signal interface and a channel simulation as a data interface.
  • Step S503 the processor receives information that is sent back by the debugged SMI interface device on the SMI cable interface side to perform the instruction;
  • Step S504 the processor parses the received information, extracts the useful information, and sends the information to the upper computer through the PC interface.
  • the following operations are further performed: when the debugged SMI interface device accesses the debug device through the SMI cable interface, detecting the debugged SMI interface device An interface level, the level shifting branch is selected according to an interface level of the debugged SMI interface device, such that the level shifting branch is to the processor and the debugged SMI interface device during debugging The signals that interact between are level shifted.
  • the SMI interface device can be directly debugged by the instruction of the upper computer (for example, the read/write operation of the register), and the method can be conveniently implemented when the CPU control program is not written or the program is written. Debugging, and this debugging method helps to quickly locate faults, significantly improving the efficiency of hardware development.
  • the invention directly debugs the SMI interface device by the instruction of the upper computer (such as the read/write operation of the register), and realizes that the debugging can be conveniently performed when the program of the CPU control program is not written or the program is written.
  • the debugging method helps to quickly locate faults and significantly improves hardware development efficiency.

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Abstract

Disclosed are an SMI (Serial Management Interface) interface device debugging apparatus and method, the apparatus comprising: a PC interface, a processor, and an SMI cable interface; the processor is configured to receive an instruction sent by an upper computer for access to this debugging apparatus through the PC interface, convert the instruction into SMI format data, and send the SMI format data, through an analog SMI interface, to a debugged SMI interface device which is connected to this debugging apparatus through the SMI cable interface; and information, which is fed back after the instruction is executed by the debugged SMI interface device, is received through the analog SMI interface and then analyzed, and useful information is extracted and sent to the upper computer. The debugging apparatus and method enable a convenient debugging for SMI interface devices when no CPU control program is written or the programs written are problematic, improving the efficiency in hardware development.

Description

SMI接口器件的调试装置及方法、存储介质SMI interface device debugging device and method, storage medium 技术领域Technical field
本发明涉及通信技术，尤其涉及一种SMI接口器件的调试装置及方法、存储介质。The present invention relates to communications technologies, and in particular, to a debugging apparatus and method for an SMI interface device, and a storage medium.
背景技术Background technique
随着网络技术的发展及产品IT化演进，在目前的BBU(基带处理单元)及其他的产品中会应用大量的SMI(Serial Management Interface，串行管理接口)接口的器件，如PHY、交换芯片等，通过这些器件实现设备与以太网、光纤网络的高速通信，这些器件均需要进行配置及调试，来确保其正确稳定的工作。With the development of network technology and the evolution of product IT, a large number of SMI (Serial Management Interface) interface devices such as PHY and switch chip are used in current BBU (baseband processing unit) and other products. In these devices, high-speed communication between devices and Ethernet and fiber-optic networks is required. These devices need to be configured and debugged to ensure correct and stable operation.
目前的调试方式是通过在电路板内与SMI接口的器件连接的CPU来进行控制，需要编写CPU的软件程序来进行处理。这样在调试很多的SMI接口的器件时会因处理CPU及SMI接口器件的寄存器差异而导致编写软件比较复杂，同时也会增加周期，如果调试过程中出现问题还需要修改程序去定位故障点，这会降低开发效率。The current debugging method is controlled by a CPU connected to the device of the SMI interface in the board, and a software program of the CPU needs to be written for processing. In this way, when debugging a lot of devices of the SMI interface, the writing of the software is complicated due to the difference of the registers of the CPU and the SMI interface device, and the cycle is also increased. If there is a problem during the debugging process, the program needs to be modified to locate the fault point. Will reduce development efficiency.
在中国专利申请《SMI接口管理方法及可编程逻辑器件》，申请号：CN201310181278，申请日期：2013.05.15中描述了一种可编程逻辑器件PLD，包括：SMI接口寄存器、以及与其相连的SMI接口收发器和译码器；SMI接口寄存器与处理器CPU通过总线相连；SMI接口收发器的SMI接口通过译码器扩展出与被管理的从SMI接口器件数量相同的主SMI接口；每个扩展出的主SMI接口使用PLD的2个I/O管脚，每个主SMI接口与一个从SMI接口器件相连；不同电平应用的主SMI接口位于PLD的输入输出端口I/O组不同的逻辑区域BANK中，每个BANK的I/O管脚设置成与该 BANK内主SMI接口的电平相同的电平模式。这种方法适用于单板内设计时使用，用来进行板内的多片SMI接口器件管理，但实际应用中一般不会额外增加逻辑器件PLD来进行转接，而是直接将SMI接口做电平匹配后挂在CPU的SMI接口总线上，并且该专利所述的方案不能避免调试中的复杂的程序开发及周期，不能快速定位故障，在实际的研发效率上没有明显提升。In the Chinese patent application "SMI interface management method and programmable logic device", application number: CN201310181278, application date: 2013.05.15 describes a programmable logic device PLD, including: SMI interface register, and the SMI interface connected thereto The transceiver and the decoder; the SMI interface register is connected to the processor CPU via the bus; the SMI interface of the SMI interface transceiver expands the main SMI interface with the same number of managed SMI interface devices through the decoder; The main SMI interface uses two I/O pins of the PLD, each of which is connected to a slave SMI interface device; the main SMI interface for different level applications is located in a different logical area of the I/O group of the input and output ports of the PLD. In BANK, the I/O pins of each BANK are set to The level mode of the same level of the main SMI interface in BANK. This method is suitable for use in the design of a single board. It is used to manage multiple SMI interface devices in the board. However, in practical applications, the logic device PLD is not added for transfer, but the SMI interface is directly powered. After the flat match, it is hung on the SMI interface bus of the CPU, and the solution described in the patent cannot avoid complicated program development and cycle in debugging, and cannot quickly locate the fault, and the actual R&D efficiency is not significantly improved.
可见，现有的SMI接口器件的调试方式受限于CPU调试程序的开发，不仅影响SMI接口器件研发效率，而且在该调试方式还不能快速定位SMI接口器件的故障。It can be seen that the debugging mode of the existing SMI interface device is limited by the development of the CPU debugger, which not only affects the R&D efficiency of the SMI interface device, but also fails to quickly locate the fault of the SMI interface device in the debug mode.
发明内容Summary of the invention
本发明实施例提供一种SMI接口器件的调试装置及方法。Embodiments of the present invention provide a debugging apparatus and method for an SMI interface device.
依据本发明实施例的一个方面，提供一种SMI接口器件的调试装置，包括：PC接口、处理器、以及SMI线缆接口；According to an aspect of an embodiment of the present invention, a debugging apparatus for an SMI interface device includes: a PC interface, a processor, and an SMI cable interface;
所述处理器，配置为接收通过所述PC接口接入本调试装置的上位机发送的指令，将所述指令转换为SMI格式数据，并将所述SMI格式数据通过模拟的SMI接口发送至通过所述SMI线缆接口连接至本调试装置的被调试SMI接口器件；以及通过模拟的SMI接口接收所述被调试SMI接口器件执行所述指令后反馈的信息，解析该信息，提取出有用信息后将其发送至所述上位机。The processor is configured to receive an instruction sent by the host computer that accesses the debugging device by using the PC interface, convert the instruction into SMI format data, and send the SMI format data to the through-simulated SMI interface. The SMI cable interface is connected to the debugged SMI interface device of the debugging device; and receives information fed back by the debugged SMI interface device after executing the command through the simulated SMI interface, parses the information, and extracts useful information. Send it to the host computer.
作为一种实现方式，本发明所述的调试装置中，当与所述上位机对接的PC接口与所述处理器支持的接口不相同时，在所述PC接口与处理器之间布设接口转换芯片，用以实现处理器所支持接口到PC接口以及PC接口到处理器所支持接口的转换。As an implementation manner, in the debugging apparatus of the present invention, when the PC interface docked with the upper computer is different from the interface supported by the processor, an interface conversion is arranged between the PC interface and the processor. The chip is used to implement the conversion of the interface supported by the processor to the PC interface and the interface supported by the PC interface to the processor.
作为一种实现方式，本发明所述的调试装置还包括：电平匹配模块，布设在所述处理器与所述SMI线缆接口之间，配置为在被调试SMI接口器 件通过所述SMI线缆接口接入本调试装置时，检测所述被调试SMI接口器件的接口电平，并对所述处理器与所述被调试SMI接口器件之间交互的信号进行电平转换。As an implementation manner, the debugging apparatus of the present invention further includes: a level matching module disposed between the processor and the SMI cable interface, configured to be debugged by the SMI interface When the device is connected to the debugging device through the SMI cable interface, detecting an interface level of the debugged SMI interface device, and leveling a signal between the processor and the debugged SMI interface device Conversion.
作为一种实现方式，本发明所述的调试装置中，所述电平匹配模块，具体包括：电平检测单元和电平转换单元；As an implementation manner, in the debugging apparatus of the present invention, the level matching module specifically includes: a level detecting unit and a level converting unit;
所述电平检测单元，配置为在被调试SMI接口器件通过所述SMI线缆接口接入本调试装置时，对所述被调试SMI接口器件的接口电平进行检测，并将检测结果上报至所述处理器；The level detecting unit is configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and report the detection result to the The processor;
所述电平转换单元，包括：模拟开关和若干分压电阻网络；The level conversion unit includes: an analog switch and a plurality of voltage dividing resistor networks;
各所述分压电阻网络，将所述处理器支持的电平进行分压得到不同SMI接口器件所需的电平；Each of the voltage dividing resistor networks divides a level supported by the processor to obtain a level required by different SMI interface devices;
所述模拟开关，配置为基于所述处理器的控制，选通与所述被调试SMI接口器件的接口电平相对应的分压电阻网络，以进行信号的电平转换及传输。The analog switch is configured to gate a voltage divider resistor network corresponding to an interface level of the debugged SMI interface device for level conversion and transmission of signals based on control of the processor.
作为一种实现方式，本发明所述的调试装置中，所述处理器通过将其使用的通信接口一路模拟为时钟信号接口、一路模拟为数据接口的方式，实现对SMI接口的模拟。As an implementation manner, in the debugging apparatus of the present invention, the processor simulates the SMI interface by simulating the communication interface used by the processor as a clock signal interface and a simulation as a data interface.
作为一种实现方式，本发明所述的调试装置中，所述上位机发送的指令的类型包括：读寄存器指令和写寄存器指令；As an implementation manner, in the debugging apparatus of the present invention, the type of the instruction sent by the upper computer includes: a read register instruction and a write register instruction;
当所述指令为读寄存器指令时，指令中包含寄存器的地址信息；当所述指令为写寄存器指令时，指令中包含写入寄存器的数据和寄存器的地址信息。When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
依据本发明实施例的另一个方面，提供一种SMI接口器件的调试方法，包括：According to another aspect of the embodiments of the present invention, a method for debugging an SMI interface device is provided, including:
调试时，处理器将PC接口侧传入的上位机的指令转换为SMI格式数 据；During debugging, the processor converts the instructions of the host computer passed to the PC interface side into the number of SMI formats. according to;
处理器将所述SMI格式数据通过模拟的SMI接口发送至SMI线缆接口，以通过所述SMI线缆接口将所述SMI格式数据发送至被调试SMI接口器件；Transmitting, by the processor, the SMI format data to the SMI cable interface through the simulated SMI interface, to send the SMI format data to the debugged SMI interface device by using the SMI cable interface;
处理器接收所述SMI线缆接口侧传入的所述被调试SMI接口器件执行所述指令后反馈的信息；Receiving, by the processor, information that is sent back by the debugged SMI interface device on the SMI cable interface side to perform the instruction;
处理器解析接收到的信息，提取出有用信息后通过所述PC接口发送至所述上位机。The processor parses the received information, extracts the useful information, and sends the information to the upper computer through the PC interface.
作为一种实现方式，本发明所述方法中，调试前，所述方法还包括：当被调试SMI接口器件通过所述SMI线缆接口接入调试装置时，检测所述被调试SMI接口器件的接口电平，根据所述被调试SMI接口器件的接口电平，选择电平转换支路，以使所述电平转换支路在调试过程中对所述处理器与所述被调试SMI接口器件之间交互的信号进行电平转换。As an implementation manner, in the method of the present invention, before the debugging, the method further includes: detecting, when the debugged SMI interface device accesses the debugging device through the SMI cable interface, detecting the debugged SMI interface device An interface level, the level shifting branch is selected according to an interface level of the debugged SMI interface device, such that the level shifting branch is to the processor and the debugged SMI interface device during debugging The signals that interact between are level shifted.
作为一种实现方式，本发明所述方法中，所述模拟SMI接口为所述处理器通过将其使用的通信接口一路模拟为时钟信号接口、一路模拟为数据接口实现的。As an implementation manner, in the method of the present invention, the analog SMI interface is implemented by the processor by simulating a communication interface used by the processor as a clock signal interface and a channel simulation as a data interface.
作为一种实现方式，本发明所述方法中，所述上位机的指令类型包括：读寄存器指令和写寄存器指令；As an implementation manner, in the method of the present invention, the instruction type of the upper computer includes: a read register instruction and a write register instruction;
当所述指令为读寄存器指令时，指令中包含寄存器的地址信息；当所述指令为写寄存器指令时，指令中包含写入寄存器的数据和寄存器的地址信息。When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
采用本发明所述的装置及方法，可以通过上位机的指令直接对SMI接口器件进行调试(如寄存器的读写操作)，实现了在没有进行CPU控制程序编写或所编写的程序有问题时，可以方便的进行调试，且这种调试方式有助于快速定位故障，明显地提高了硬件的研发效率。 By using the device and method of the invention, the SMI interface device can be directly debugged by the instruction of the host computer (such as register read and write operations), and when the program of the CPU control program is not written or the program is written, It can be easily debugged, and this debugging method helps to quickly locate faults and significantly improves hardware development efficiency.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is merely some embodiments of the present invention, and those skilled in the art can obtain other drawings according to the drawings without any inventive labor.
图1为本发明实施例一提供的一种SMI接口器件的调试装置的结构框图；1 is a structural block diagram of a debugging apparatus for an SMI interface device according to Embodiment 1 of the present invention;
图2为本发明实施例二提供的一种SMI接口器件的调试装置的结构框图；2 is a structural block diagram of a debugging apparatus for an SMI interface device according to Embodiment 2 of the present invention;
图3为本发明实施例二中电平匹配模块的电路示意图；3 is a schematic circuit diagram of a level matching module according to Embodiment 2 of the present invention;
图4为本发明实施例二所述调试装置的调试流程图；4 is a flowchart of debugging of a debugging apparatus according to Embodiment 2 of the present invention;
图5为本发明实施例三提供的一种SMI接口器件的调试方法的流程图。FIG. 5 is a flowchart of a method for debugging an SMI interface device according to Embodiment 3 of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
实施例一Embodiment 1
本发明实施例提供一种SMI接口器件的调试装置，如图1所示，所述装置包括：PC接口、处理器、以及SMI线缆接口；其中：The embodiment of the invention provides a debugging device for an SMI interface device. As shown in FIG. 1 , the device includes: a PC interface, a processor, and an SMI cable interface; wherein:
PC接口，配置为接入上位机；a PC interface configured to access the host computer;
SMI线缆接口配置为接入被调试SMI接口器件；The SMI cable interface is configured to access the debugged SMI interface device;
处理器，配置为接收通过所述PC接口接入本调试装置的上位机发送的 指令，将所述指令转换为SMI格式数据，并将所述SMI格式数据通过模拟的SMI接口发送至通过所述SMI线缆接口连接至本调试装置的被调试SMI接口器件；以及通过模拟的SMI接口接收所述被调试SMI接口器件执行所述指令后反馈的信息，解析该信息，提取出有用信息后将其发送至所述上位机。a processor configured to receive, sent by the host computer that accesses the debugging device by using the PC interface Directing, converting the instruction into SMI format data, and transmitting the SMI format data to the debugged SMI interface device connected to the debug device through the SMI cable interface through the analog SMI interface; and passing the simulated SMI The interface receives the information fed back by the debugged SMI interface device after executing the instruction, parses the information, extracts the useful information, and sends the information to the upper computer.
本实施例中，所述处理器通过将其使用的通信接口一路模拟为时钟信号接口、一路模拟为数据接口的方式，实现对SMI接口的模拟。其中，通信接口包括但不限于为IO接口。In this embodiment, the processor simulates the SMI interface by simulating the communication interface used by the processor as a clock signal interface and a simulation as a data interface. The communication interface includes but is not limited to being an IO interface.
进一步地，本实施例中，上位机发送的指令的类型包括：读寄存器指令和写寄存器指令；当所述指令为读寄存器指令时，指令中包含寄存器的地址信息；当所述指令为写寄存器指令时，指令中包含写入寄存器的数据和寄存器的地址信息。Further, in this embodiment, the type of the instruction sent by the host computer includes: a read register instruction and a write register instruction; when the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register When the instruction is executed, the instruction contains the data written to the register and the address information of the register.
在本发明的一个优选实施例中，考虑到处理器所支持的接口与PC接口的类型可能不同，为了能够实现信息交互，优选地，在所述PC接口与处理器之间布设接口转换芯片，用以实现处理器所支持接口到PC接口以及PC接口到处理器所支持接口的转换。In a preferred embodiment of the present invention, in view of the fact that the type of the interface supported by the processor and the PC interface may be different, in order to enable information interaction, preferably, an interface conversion chip is disposed between the PC interface and the processor, It is used to implement the conversion of the interface supported by the processor to the PC interface and the interface supported by the PC interface to the processor.
在本发明的另一个优选实施例中，考虑到不同的被调试SMI接口器件的接口电平可能不同，为了增加本发明所述装置的普适性，优选地，在所述处理器与所述SMI线缆接口之间布设电平匹配模块；In another preferred embodiment of the present invention, in view of the fact that the interface levels of different debug SMI interface devices may be different, in order to increase the universality of the apparatus of the present invention, preferably, the processor and the A level matching module is disposed between the SMI cable interfaces;
所述电平匹配模块，配置为在被调试SMI接口器件通过所述SMI线缆接口接入本实施例所述调试装置时，检测所述被调试SMI接口器件的接口电平，并对所述处理器与所述被调试SMI接口器件之间交互的信号进行电平转换。The level matching module is configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device of the embodiment through the SMI cable interface, and A signal is exchanged between the processor and the signal being exchanged between the debugged SMI interface device.
在本发明的一个具体实施例中，电平匹配模块包括：电平检测单元和电平转换单元；其中： In a specific embodiment of the present invention, the level matching module includes: a level detecting unit and a level converting unit; wherein:
电平检测单元，配置为在被调试SMI接口器件通过所述SMI线缆接口接入本调试装置时，对所述被调试SMI接口器件的接口电平进行检测，并将检测结果上报至所述处理器；a level detecting unit configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and report the detection result to the processor;
电平转换单元，包括：模拟开关和若干分压电阻网络；a level shifting unit comprising: an analog switch and a plurality of voltage dividing resistor networks;
各所述分压电阻网络，将所述处理器支持的电平进行分压得到不同SMI接口器件所需的电平；Each of the voltage dividing resistor networks divides a level supported by the processor to obtain a level required by different SMI interface devices;
所述模拟开关，配置为基于所述处理器的控制，选通与所述被调试SMI接口器件的接口电平相对应的分压电阻网络，以进行信号的电平转换及传输。The analog switch is configured to gate a voltage divider resistor network corresponding to an interface level of the debugged SMI interface device for level conversion and transmission of signals based on control of the processor.
当然，本实施例所述的电平匹配模块的结构形式只是众多可以实现电平转换方案中的一种，本发明并不唯一限定该结构形式，只要其能够实现不同电平之间转换的方案都在本发明的保护思想范围之内。Certainly, the structure of the level matching module described in this embodiment is only one of a plurality of level conversion schemes that can be implemented, and the present invention does not uniquely limit the structure, as long as it can implement a scheme for converting between different levels. All are within the scope of the protection idea of the present invention.
综上所述，可知本实施例所述的调试装置，可以直接将上位机的指令发送至SMI接口器件进行器件的调试，实现了在没有进行CPU控制程序编写或所编写的程序有问题时，也可以方便的进行调试的技术；另外，本发明中，由于可以方便的对SMI接口器件进行调试，那么当SMI接口器件出现故障时，上位机也可以根据调试信息，快速的定位出故障，明显的提高了硬件的研发效率。In summary, it can be seen that the debugging apparatus described in this embodiment can directly send the instruction of the upper computer to the SMI interface device to perform debugging of the device, and realize that when there is no problem in programming the CPU control program or writing the program, The technology can also be conveniently debugged. In addition, in the present invention, since the SMI interface device can be conveniently debugged, when the SMI interface device fails, the host computer can quickly locate the fault according to the debugging information. Improve the efficiency of hardware development.
实施例二Embodiment 2
本发明实施例提供一种SMI接口器件的调试装置，该调试装置中，以单片机***作为处理器来实施，具体的，本实施例所述的SMI接口器件的调试装置，如图2所示，包括：单片机***，接口转换芯片，PC接口，电平匹配模块，SMI线缆接口。The embodiment of the present invention provides a debugging device for an SMI interface device. The debugging device is implemented by using a single chip microcomputer system as a processor. Specifically, the debugging device of the SMI interface device in this embodiment is shown in FIG. 2 . Including: single-chip system, interface conversion chip, PC interface, level matching module, SMI cable interface.
其中，PC接口的类型通常为USB接口或者RS232接口，该PC接口为上位机连接本调试装置的对外接口； The type of the PC interface is usually a USB interface or an RS232 interface, and the PC interface is an external interface of the upper computer connected to the debugging device;
接口转换芯片，布设在PC接口与单片机***之间，可以实现单片机***支持的UART接口到USB/RS232接口的转换功能；The interface conversion chip is disposed between the PC interface and the single chip system, and can realize the conversion function of the UART interface supported by the single chip system to the USB/RS232 interface;
单片机***，作为核心处理单元，接收PC接口和接口转换芯片传递过来的所述上位机发送的指令信息；提取出指令信息，并按照SMI协议生成SMI格式数据；进一步地，单片机***为了可以实现SMI格式数据的传输，预先需要通过软件方式，来实现SMI接口的模拟，以通过模拟的SMI接口将SMI格式数据传递至电平匹配模块。The single chip microcomputer system, as a core processing unit, receives the instruction information sent by the upper computer transmitted by the PC interface and the interface conversion chip; extracts the instruction information, and generates the SMI format data according to the SMI protocol; further, the single chip system can realize the SMI For the transmission of format data, the simulation of the SMI interface is implemented in advance by software to transmit the SMI format data to the level matching module through the analog SMI interface.
关于SMI接口的模拟方式，可以为：假设电平匹配模块与单片机***通过IO口直连，那么，单片机***需要通过IO口提供模拟的SMI接口，具体的，将单片机***作为主设备将IO口一路模拟为时钟信号接口，一路模拟为数据接口，从而实现对SMI接口的模拟。The analog mode of the SMI interface can be: Assume that the level matching module and the single chip system are directly connected through the IO port. Then, the single chip system needs to provide an analog SMI interface through the IO port. Specifically, the single chip system is used as the main device to connect the IO port. One way of simulation is the clock signal interface, and the other is analog data interface, which realizes the simulation of the SMI interface.
电平匹配模块的功能包括调试前的功能和调试过程中的功能；The functions of the level matching module include functions before debugging and functions during debugging;
调试前的功能包括：当被调试SMI接口器件通过所述SMI线缆接口接入调试装置时，检测所述被调试SMI接口器件的接口电平，根据所述被调试SMI接口器件的接口电平，选择电平转换支路；The function before debugging includes: detecting the interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debug device through the SMI cable interface, according to the interface level of the debugged SMI interface device , select the level shifting branch;
调试过程中的功能包括：基于调试前选择的电平转换支路，在调试过程中对所述单片机***与所述被调试SMI接口器件之间交互的信号进行电平转换。The functions in the debugging process include: level shifting the signals exchanged between the single chip system and the debugged SMI interface device during the debugging process based on the level shifting branch selected before the debugging.
为了实现上述功能，本实施例中，电平匹配模块的结构如图3所示，包括：电平检测单元和电平转换单元，而电平转换单元又包括两组模拟开关和两组4个分压电阻网络，通过该结构来实现调试装置与不同电平的SMI接口器件直连，实现即插即用。其中，4个只是一种具体应用示例中的参数，本领域技术人员可以根据需求增加或减少。In order to achieve the above functions, in the embodiment, the structure of the level matching module is as shown in FIG. 3, including: a level detecting unit and a level converting unit, and the level converting unit includes two sets of analog switches and two sets of four. The voltage divider resistor network realizes that the debugging device is directly connected to the SMI interface devices of different levels through the structure, and realizes plug and play. Among them, 4 are only parameters in a specific application example, and those skilled in the art can increase or decrease according to requirements.
其中，电平检测单元，与单片机***连接，配置为在被调试SMI接口器件通过所述SMI线缆接口接入本调试装置时，对所述被调试SMI接口器 件的接口电平进行检测，并将检测结果上报至所述单片机***；The level detecting unit is connected to the single chip system, and is configured to be used when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and the debugged SMI interface device The interface level of the device is detected, and the detection result is reported to the single chip microcomputer system;
4个分压电阻网络可以将单片机***支持的5V的TTL电平进行分压得到不同SMI接口器件所需的电平，如分别通过4个分压电阻网络可以实现5V转5V、3.3V、2.5V、1.8V。The four voltage divider resistor networks can divide the TTL level of 5V supported by the MCU system to obtain the required level of different SMI interface devices. For example, 5V to 5V, 3.3V, and 2.5 can be realized through 4 voltage divider resistor networks. V, 1.8V.
单片机***包含四个IO管脚，分两组分别连接模拟开关的2路选通控制引脚，单片机***根据电平检测单元上报的电平信息，控制模拟开关实现两组四选一功能，模拟开关的两组可选接口分别连接四个分压电阻网络中的1个，实现5V转5V、3.3V、2.5V或1.8V。其中，选择的两组线路，一组用于传递时钟信号，一组用于传递数据。The MCU system consists of four IO pins, which are respectively connected to two 2-way strobe control pins of the analog switch. The MCU system controls the analog switch to realize two sets of four-selection functions according to the level information reported by the level detection unit. The two sets of optional interfaces of the switch are respectively connected to one of the four voltage divider resistor networks to achieve 5V to 5V, 3.3V, 2.5V or 1.8V. Among them, the selected two sets of lines, one for transmitting clock signals and one for transmitting data.
SMI线缆接口与被调测的SMI接口器件通过排针或测试点连接，SMI线缆接口为三根线，分别为时钟信号线，数据信号线，电源地线。The SMI cable interface is connected to the tested SMI interface device through a pin header or a test point. The SMI cable interface is three wires, which are a clock signal line, a data signal line, and a power ground line.
基于上述结构阐述，下面对利用本实施例所述的调试装置实现调试控制的实施过程进行详细说明，以更好的说明上述结构部件的具体工作过程。Based on the above structure, the implementation process of the debugging control by using the debugging device described in this embodiment will be described in detail to better explain the specific working process of the above structural components.
本实施例中，调试装置通过PC接口与上位机连接，通过SMI线缆接口与相应要调试的SMI接口器件连接，然后，单片机***会根据电平匹配模块中电平检测单元检测到的SMI接口器件的接口电平值，自动控制电平匹配模块中的模拟开关选择相应的分压电阻网络来进行电平匹配。在电平匹配成功后单片机***开始接收上位机的指令，通过数据解析确定是读操作还是写操作以及寄存器地址和数据。如果是读操作，单片机***将数据处理好后通过模拟的SMI接口与调试的SMI接口器件通信，读取相应寄存器的数据。如果是写操作，单片机***将寄存器地址及将要写入的数据处理后通过模拟的SMI接口对调试的SMI接口器件的相应寄存器进行操作，上述过程的流程信息如图4所示。In this embodiment, the debugging device is connected to the host computer through the PC interface, and is connected to the corresponding SMI interface device to be debugged through the SMI cable interface, and then, the single chip system detects the SMI interface according to the level detecting unit in the level matching module. The interface level value of the device, the analog switch in the automatic control level matching module selects the corresponding voltage divider resistor network for level matching. After the level matching is successful, the MCU system starts to receive the instruction of the host computer, and determines whether it is a read operation or a write operation and a register address and data through data analysis. If it is a read operation, the MCU system processes the data and communicates with the debugged SMI interface device through the analog SMI interface to read the data of the corresponding register. If it is a write operation, the microcontroller system processes the register address and the data to be written, and then operates the corresponding register of the debugged SMI interface device through the analog SMI interface. The process information of the above process is shown in FIG. 4 .
具体地，本实施例中，对寄存器的写操作的实施过程如下：Specifically, in this embodiment, the implementation process of the write operation to the register is as follows:
调试装置的PC接口接收到上位机发送的写入SMI接口器件内寄存器 的数据及寄存器地址信息，并将接收到的信息发送至接口转换芯片；The PC interface of the debugging device receives the write to the SMI interface device register sent by the host computer. Data and register address information, and send the received information to the interface conversion chip;
接口转换芯片将PC接口转换为UART接口，以实现将PC接口传递来的信息发送至单片机***；The interface conversion chip converts the PC interface into a UART interface, so as to transmit information transmitted by the PC interface to the single chip system;
单片机***接收到接口转换芯片发送的信息后，提取出寄存器地址和写入寄存器的数据，并将提取出的信息按照SMI协议格式生成SMI格式数据，并将SMI格式数据通过模拟的SMI接口发送至电平匹配模块；After receiving the information sent by the interface conversion chip, the single chip system extracts the register address and the data written into the register, and generates the SMI format data according to the SMI protocol format, and sends the SMI format data to the simulated SMI interface to the SMI interface. Level matching module;
电平匹配模块将接收到的信号进行电平转换后通过SMI线缆接口发送至调试的SMI接口器件，从而实现了寄存器的写操作。The level matching module performs level conversion on the received signal and sends it to the debugged SMI interface device through the SMI cable interface, thereby realizing the write operation of the register.
总的来说，单片机***通过接口转换芯片及PC接口来接收上位机软件发送的寄存器地址及将要写入的数据，单片机***将接收到的指令解析，提取寄存器相关的数据，之后通过模拟的SMI接口将数据写入指定的寄存器而实现写操作。In general, the MCU system receives the register address sent by the host computer software and the data to be written through the interface conversion chip and the PC interface. The MCU system parses the received command, extracts the register-related data, and then passes the simulated SMI. The interface writes data to the specified register for write operations.
具体的，本实施例中，对寄存器的读操作实施过程如下：Specifically, in this embodiment, the process of reading the register is as follows:
调试装置的PC接口接收到上位机发送的读取寄存器内数据的寄存器地址信息，并将该信息发送到接口转换芯片；The PC interface of the debugging device receives the register address information of the data in the read register sent by the host computer, and sends the information to the interface conversion chip;
接口转换芯片将PC接口转换为UART接口，以实现将PC接口传递来的信息发送至单片机***；The interface conversion chip converts the PC interface into a UART interface, so as to transmit information transmitted by the PC interface to the single chip system;
单片机***接收到接口转换芯片发送的信息后，提取出寄存器地址信息，并将提取出的信息按照SMI协议格式生成SMI格式数据，并将SMI格式数据通过模拟的SMI接口发送至电平匹配模块；After receiving the information sent by the interface conversion chip, the single chip system extracts the register address information, and generates the SMI format data according to the SMI protocol format, and sends the SMI format data to the level matching module through the analog SMI interface;
电平匹配模块将接收到的信号进行电平转换后通过SMI线缆接口发送至调试的SMI接口器件，以读取SMI接口器件内寄存器的数据；The level matching module performs level conversion on the received signal and sends it to the debugged SMI interface device through the SMI cable interface to read the data of the register in the SMI interface device;
SMI线缆接口将SMI接口器发送的读取的寄存器的数据发送到电平匹配模块；The SMI cable interface sends data of the read register sent by the SMI interface to the level matching module;
电平匹配模块将接收到的信号进行电平转换后发送至单片机***； The level matching module performs level conversion on the received signal and sends it to the single chip system;
单片机***根据时钟信号，提取出信息中的寄存器的数据，并将提取出的数据发送至接口转换芯片；The single chip system extracts the data of the register in the information according to the clock signal, and sends the extracted data to the interface conversion chip;
接口转换芯片将UART接口转换为PC接口，以将单片机***提取出的数据发送至PC接口，进而通过PC接口发送至上位机。The interface conversion chip converts the UART interface into a PC interface, and sends the data extracted by the single-chip microcomputer system to the PC interface, and then sends the data to the upper computer through the PC interface.
总的来说，单片机***先从上位机接收需要读取数据的寄存器的信息，之后单片机***通过SMI接口获取器件的指定寄存器数据，经过数据提取及转换程序进行处理后通过UART接口传给信号转换芯片至PC接口，与上位机完成数据通信。即实现了寄存器的读操作。In general, the MCU system first receives the information of the register that needs to read data from the host computer, and then the MCU system obtains the specified register data of the device through the SMI interface, and processes the data through the UART interface after the data extraction and conversion process. Chip to PC interface, complete data communication with the host computer. That is, the read operation of the register is realized.
实施例三Embodiment 3
本发明实施例提供一种利用实施例一或二所述的调试装置实现SMI接口器件的调试方法，如图5所示，包括：The embodiment of the invention provides a debugging method for implementing an SMI interface device by using the debugging device according to the first embodiment or the second embodiment. As shown in FIG. 5, the method includes:
步骤S501，调试时，处理器将PC接口侧传入的上位机的指令转换为SMI格式数据；Step S501, when debugging, the processor converts the instruction of the host computer transmitted from the PC interface side into SMI format data;
该步骤中，所述上位机的指令类型包括：读寄存器指令和写寄存器指令；In this step, the instruction type of the upper computer includes: a read register instruction and a write register instruction;
当所述指令为读寄存器指令时，指令中包含寄存器的地址信息；当所述指令为写寄存器指令时，指令中包含写入寄存器的数据和寄存器的地址信息。When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
步骤S502，处理器将所述SMI格式数据通过模拟的SMI接口发送至SMI线缆接口，以通过所述SMI线缆接口将所述SMI格式数据发送至被调试SMI接口器件；Step S502, the processor sends the SMI format data to the SMI cable interface through the simulated SMI interface, to send the SMI format data to the debugged SMI interface device by using the SMI cable interface;
本实施例中，所述模拟SMI接口优选为所述处理器通过将其使用的通信接口一路模拟为时钟信号接口、一路模拟为数据接口实现的。In this embodiment, the analog SMI interface is preferably implemented by the processor by simulating a communication interface used by the processor as a clock signal interface and a channel simulation as a data interface.
步骤S503，处理器接收所述SMI线缆接口侧传入的所述被调试SMI接口器件执行所述指令后反馈的信息； Step S503, the processor receives information that is sent back by the debugged SMI interface device on the SMI cable interface side to perform the instruction;
步骤S504，处理器解析接收到的信息，提取出有用信息后通过所述PC接口发送至所述上位机。Step S504, the processor parses the received information, extracts the useful information, and sends the information to the upper computer through the PC interface.
在本发明的一个优选实施例中，在调试前，优选地，还进行如下操作：当被调试SMI接口器件通过所述SMI线缆接口接入调试装置时，检测所述被调试SMI接口器件的接口电平，根据所述被调试SMI接口器件的接口电平，选择电平转换支路，以使所述电平转换支路在调试过程中对所述处理器与所述被调试SMI接口器件之间交互的信号进行电平转换。In a preferred embodiment of the present invention, before debugging, preferably, the following operations are further performed: when the debugged SMI interface device accesses the debug device through the SMI cable interface, detecting the debugged SMI interface device An interface level, the level shifting branch is selected according to an interface level of the debugged SMI interface device, such that the level shifting branch is to the processor and the debugged SMI interface device during debugging The signals that interact between are level shifted.
本发明实施例所述方法，可以通过上位机的指令直接对SMI接口器件进行调试(如寄存器的读写操作)，实现了在没有进行CPU控制程序编写或所编写的程序有问题时，可以方便的进行调试，且这种调试方式有助于快速定位故障，明显的提高了硬件的研发效率。According to the method of the embodiment of the present invention, the SMI interface device can be directly debugged by the instruction of the upper computer (for example, the read/write operation of the register), and the method can be conveniently implemented when the CPU control program is not written or the program is written. Debugging, and this debugging method helps to quickly locate faults, significantly improving the efficiency of hardware development.
本发明中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是其与其他实施例的不同之处。尤其对于方法实施例而言，由于其实施过程基本相似与装置实施例，所以，描述的比较简单，相关之处参见装置实施例的部分说明即可。The various embodiments of the present invention are described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. Especially for the method embodiment, since the implementation process is basically similar to the device embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the device embodiment.
虽然通过实施例描述了本申请，本领域的技术人员知道，本申请有许多变形和变化而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。While the present invention has been described by the embodiments of the invention, it will be understood that Thus, it is intended that the present invention cover the modifications and modifications of the invention
工业实用性Industrial applicability
本发明通过上位机的指令直接对SMI接口器件进行调试(如寄存器的读写操作)，实现了在没有进行CPU控制程序编写或所编写的程序有问题时，可以方便的进行调试，且这种调试方式有助于快速定位故障，明显地提高了硬件的研发效率。 The invention directly debugs the SMI interface device by the instruction of the upper computer (such as the read/write operation of the register), and realizes that the debugging can be conveniently performed when the program of the CPU control program is not written or the program is written. The debugging method helps to quickly locate faults and significantly improves hardware development efficiency.

Claims (11)

  1. 一种SMI接口器件的调试装置，包括：PC接口、处理器、以及SMI线缆接口；A debugging device for an SMI interface device, comprising: a PC interface, a processor, and an SMI cable interface;
    所述处理器，配置为接收通过所述PC接口接入本调试装置的上位机发送的指令，将所述指令转换为SMI格式数据，并将所述SMI格式数据通过模拟的SMI接口发送至通过所述SMI线缆接口连接至本调试装置的被调试SMI接口器件；以及通过模拟的SMI接口接收所述被调试SMI接口器件执行所述指令后反馈的信息，解析该信息，提取出有用信息后将其发送至所述上位机。The processor is configured to receive an instruction sent by the host computer that accesses the debugging device by using the PC interface, convert the instruction into SMI format data, and send the SMI format data to the through-simulated SMI interface. The SMI cable interface is connected to the debugged SMI interface device of the debugging device; and receives information fed back by the debugged SMI interface device after executing the command through the simulated SMI interface, parses the information, and extracts useful information. Send it to the host computer.
  2. 如权利要求1所述的调试装置，其中，当与所述上位机对接的PC接口与所述处理器支持的接口不相同时，在所述PC接口与处理器之间布设接口转换芯片，用以实现处理器所支持接口到PC接口以及PC接口到处理器所支持接口的转换。The debugging device according to claim 1, wherein when the PC interface docked with the upper computer is different from the interface supported by the processor, an interface conversion chip is disposed between the PC interface and the processor, To achieve the conversion of the interface supported by the processor to the PC interface and the interface supported by the PC interface to the processor.
  3. 如权利要求1所述的调试装置，其中，所述调试装置还包括：The debugging device of claim 1, wherein the debugging device further comprises:
    电平匹配模块，布设在所述处理器与所述SMI线缆接口之间，配置为在被调试SMI接口器件通过所述SMI线缆接口接入本调试装置时，检测所述被调试SMI接口器件的接口电平，并对所述处理器与所述被调试SMI接口器件之间交互的信号进行电平转换。a level matching module, disposed between the processor and the SMI cable interface, configured to detect the debugged SMI interface when the debugged SMI interface device accesses the debugging device through the SMI cable interface The interface level of the device and level shifting the signals between the processor and the debugged SMI interface device.
  4. 如权利要求3所述的调试装置，其中，所述电平匹配模块，具体包括：电平检测单元和电平转换单元；The debugging device according to claim 3, wherein the level matching module comprises: a level detecting unit and a level converting unit;
    所述电平检测单元，配置为在被调试SMI接口器件通过所述SMI线缆接口接入本调试装置时，对所述被调试SMI接口器件的接口电平进行检测，并将检测结果上报至所述处理器；The level detecting unit is configured to detect an interface level of the debugged SMI interface device when the debugged SMI interface device accesses the debugging device through the SMI cable interface, and report the detection result to the The processor;
    所述电平转换单元，包括：模拟开关和若干分压电阻网络；The level conversion unit includes: an analog switch and a plurality of voltage dividing resistor networks;
    各所述分压电阻网络，将所述处理器支持的电平进行分压得到不同 SMI接口器件所需的电平；Each of the voltage dividing resistor networks divides the level supported by the processor to obtain a different voltage The level required by the SMI interface device;
    所述模拟开关，配置为基于所述处理器的控制，选通与所述被调试SMI接口器件的接口电平相对应的分压电阻网络，以进行信号的电平转换及传输。The analog switch is configured to gate a voltage divider resistor network corresponding to an interface level of the debugged SMI interface device for level conversion and transmission of signals based on control of the processor.
  5. 如权利要求1或2或3或4所述的调试装置，其中，所述处理器通过将其使用的通信接口一路模拟为时钟信号接口、一路模拟为数据接口的方式，实现对SMI接口的模拟。The debugging device according to claim 1 or 2 or 3 or 4, wherein the processor simulates the SMI interface by simulating the communication interface used by the processor as a clock signal interface and a simulation as a data interface. .
  6. 如权利要求1或2或3或4所述的调试装置，其中，所述上位机发送的指令的类型包括：读寄存器指令和写寄存器指令；The debugging device according to claim 1 or 2 or 3 or 4, wherein the type of the instruction sent by the host computer comprises: a read register instruction and a write register instruction;
    当所述指令为读寄存器指令时，指令中包含寄存器的地址信息；当所述指令为写寄存器指令时，指令中包含写入寄存器的数据和寄存器的地址信息。When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
  7. 一种应用权利要求1所述调试装置实现SMI接口器件的调试方法，包括：A debugging method for implementing an SMI interface device by using the debugging device of claim 1, comprising:
    调试时，处理器将PC接口侧传入的上位机的指令转换为SMI格式数据；During debugging, the processor converts the instructions of the host computer transmitted from the PC interface side into SMI format data;
    处理器将所述SMI格式数据通过模拟的SMI接口发送至SMI线缆接口，以通过所述SMI线缆接口将所述SMI格式数据发送至被调试SMI接口器件；Transmitting, by the processor, the SMI format data to the SMI cable interface through the simulated SMI interface, to send the SMI format data to the debugged SMI interface device by using the SMI cable interface;
    处理器接收所述SMI线缆接口侧传入的所述被调试SMI接口器件执行所述指令后反馈的信息；Receiving, by the processor, information that is sent back by the debugged SMI interface device on the SMI cable interface side to perform the instruction;
    处理器解析接收到的信息，提取出有用信息后通过所述PC接口发送至所述上位机。The processor parses the received information, extracts the useful information, and sends the information to the upper computer through the PC interface.
  8. 如权利要求7所述的方法，其中，调试前，所述方法还包括：当被调试SMI接口器件通过所述SMI线缆接口接入调试装置时，检测所述被调 试SMI接口器件的接口电平，根据所述被调试SMI接口器件的接口电平，选择电平转换支路，以使所述电平转换支路在调试过程中对所述处理器与所述被调试SMI接口器件之间交互的信号进行电平转换。The method of claim 7, wherein before the debugging, the method further comprises: detecting the adjusted when the debugged SMI interface device accesses the debug device through the SMI cable interface Testing an interface level of the SMI interface device, selecting a level shifting branch according to an interface level of the debugged SMI interface device, such that the level shifting branch is in the debugging process to the processor and the The signals exchanged between the debug SMI interface devices are level shifted.
  9. 如权利要求7所述的方法，其中，所述模拟SMI接口为所述处理器通过将其使用的通信接口一路模拟为时钟信号接口、一路模拟为数据接口实现的。The method of claim 7, wherein the analog SMI interface is implemented by the processor by simulating a communication interface used by the processor as a clock signal interface and a channel simulation as a data interface.
  10. 如权利要求7或8或9所述的方法，其中，所述上位机的指令类型包括：读寄存器指令和写寄存器指令；The method of claim 7 or 8 or 9, wherein the instruction type of the host computer comprises: a read register instruction and a write register instruction;
    当所述指令为读寄存器指令时，指令中包含寄存器的地址信息；当所述指令为写寄存器指令时，指令中包含写入寄存器的数据和寄存器的地址信息。When the instruction is a read register instruction, the instruction includes address information of the register; when the instruction is a write register instruction, the instruction includes data written to the register and address information of the register.
  11. 一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行权利要求7至10任一项所述的调试方法。 A storage medium storing a computer program, the computer program being configured to perform the debugging method of any one of claims 7 to 10.
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