CN104679095A - Current source, current source array, read-out circuit, control method of read-out circuit and amplification circuit - Google Patents
Current source, current source array, read-out circuit, control method of read-out circuit and amplification circuit Download PDFInfo
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Abstract
The invention provides a current source, a current source array, a read-out circuit, a control method of the read-out circuit and an amplification circuit. A mirror current source comprises an I-V (current to voltage) conversion unit, a V-I (voltage to current) conversion unit, a switch and a capacitor, wherein the first input end of the I-V conversion unit is connected to the output end of a reference current source, the voltage output end of the I-V conversion unit is connected with the first input end of the V-I conversion unit through the switch, the second input end of the I-V conversion unit is connected with first voltage, the capacitor is in span connection between the first input end of the V-I conversion unit and the first voltage, the second input end of the V-I conversion unit is connected to the first voltage, and the current output end of the V-I conversion unit is connected with the output end of the mirror current source. The mirror current source has the advantages that the introduction of the noise of the reference current source and a transistor is avoided, and the performance of the mirror current source is improved.
Description
Technical field
The present invention relates to electronic applications, particularly relate to a kind of current source and array, sensing circuit and control method thereof, amplifying circuit.
Background technology
Mirror current source is a kind of common biasing circuit, by the current replication of input branch road to output branch road, for other subsystems provide current offset.Will the current replication of input branch road to exporting the process of branch road, by electric current and control end voltage one to one device come, namely pass through I-V converting unit and the V-I converting unit current replication with reference to current source to exporting branch road.Fig. 1 is a kind of existing mirror current source, be made up of reference current source 11, first metal-oxide-semiconductor 121 and the second metal-oxide-semiconductor 122, wherein the first metal-oxide-semiconductor 121 completes the function of I-V converting unit, and the second metal-oxide-semiconductor 122 completes the function of V-I converting unit, and image current is exported by the first output end p 1.
Mirror current source is widely used, but the simple mirror current source as shown in Figure 1 that utilizes is biased, and can introduce the noise of reference current source and transistor.
Summary of the invention
The problem that the embodiment of the present invention solves how to reduce the noise of reference current source.
For solving the problem, the embodiment of the present invention provides a kind of mirror current source, and described mirror current source comprises: I-V converting unit, V-I converting unit, switch, electric capacity;
Described I-V converting unit first input end is connected to described reference current source output terminal, and described I-V switching cell voltage output terminal connects V-I converting unit first input end by switch, and described I-V converting unit second inputs termination first voltage;
Described electric capacity is connected across between described V-I converting unit first input end and described first voltage, and V-I converting unit second input end is connected to the first voltage, and described V-I converting unit current output terminal is described image current source output terminal.
Optionally, described reference current source comprises band gap reference.
Optionally, described mirror current source also comprises:
Control module, is connected between described V-I converting unit current output terminal and image current source output terminal;
Described control module input end is connected to described V-I converting unit current output terminal;
Described control module control end selectivity is connected to the second voltage or tertiary voltage;
Described control module output terminal is connected to described image current source output terminal.
Optionally, described mirror current source also comprises: the second control module;
Described second control module input end is connected to described reference current source output terminal;
Described second control module output terminal is connected to described I-V converting unit input end;
The control voltage output terminal of described second control module is connected to described second voltage.
Optionally, described I-V converting unit comprises:
First NMOS tube; Described V-I unit comprises: the second NMOS tube;
The drain electrode of described first NMOS tube and grid are connected to the first input end of described I-V converting unit jointly;
The grid of described first NMOS tube is connected to the voltage output end of described I-V converting unit;
The source electrode of described first NMOS tube is connected to the second input end of described I-V converting unit;
The drain electrode of described second NMOS tube is connected to described V-I converting unit current output terminal;
The grid of described second NMOS tube is connected to described V-I converting unit first input end;
The source electrode of described second NMOS tube is connected to described V-I converting unit second input end.
Optionally, described control module comprises: the 3rd NMOS tube;
The drain electrode of the first NMOS tube and grid are connected to the first input end of described I-V converting unit jointly;
The grid of described first NMOS tube is connected to the voltage output end of described I-V converting unit;
The source electrode of described first NMOS tube is connected to the second input end of described I-V converting unit;
The drain electrode of the second NMOS tube is connected to described V-I converting unit current output terminal;
The grid of described second NMOS tube is connected to described V-I converting unit first input end;
The source electrode of described second NMOS tube is connected to described V-I converting unit second input end;
The source electrode of described 3rd NMOS tube is connected to described control module input end;
The grid of described 3rd NMOS tube is connected to described control module control end;
The drain electrode of described 3rd NMOS tube is described control module output terminal.
Optionally, described first voltage comprises: ground.
Optionally, described second voltage is higher than described tertiary voltage.
Optionally, NMOS tube is substituted by PMOS.
Optionally, described first voltage is determined by described PMOS.
Optionally, described second voltage is lower than described tertiary voltage.
The embodiment of the present invention also provides a kind of mirror current source array, and described mirror current source array also comprises: reference current source, I-V converting unit, N number of V-I converting unit, N number of switch, N number of electric capacity, N be more than or equal to 2 natural number;
Described I-V converting unit first input end is connected to described reference current source output terminal, described I-V switching cell voltage output terminal is connected to the n-th V-I converting unit first input end by the n-th switch, 1≤n≤N, described I-V converting unit second input end is connected to the first voltage;
Described n-th electric capacity is connected across the n-th V-I converting unit first input end and describedly connects between the first voltage, described each V-I converting unit second input end is connected to the first voltage, and described n-th V-I converting unit current output terminal connects described mirror current source array n-th output terminal.
Optionally, described mirror current source array also comprises the N number of control module corresponding respectively to N row pixel cell, and described N number of control module is connected between described N number of V-I converting unit current output terminal and image current source output terminal;
N-th control module input end is connected to the n-th V-I converting unit current output terminal, 1≤n≤N;
A described n-th control module control end choosing point appraise and select is connected to the second voltage or tertiary voltage;
Described n-th control module output terminal is connected to described mirror current source array n-th output terminal.
The embodiment of the present invention also provides a kind of cmos image sensor sensing circuit, and described cmos image sensor sensing circuit comprises: mirror current source array, pixel unit array, pixel cell sensing circuit;
Described mirror current source array n-th output terminal is connected to the n-th pixel cell;
Described pixel cell sensing circuit is connected with described pixel unit array.
The embodiment of the present invention also provides a kind of control method of described cmos image sensor sensing circuit, it is characterized in that, comprising:
N-th switch disconnects, and described control module control end is connected to described tertiary voltage;
N-th switch disconnects, and described control module control end is connected to described second voltage;
N-th switch closes;
N-th switch disconnects, and carries out read operation to described pixel cell.
The embodiment of the present invention also provides a kind of amplifying circuit being applicable to cmos image sensor, is suitable for being configured at often amplifying circuit described in row pixel cell and comprises: operational amplifier, the first electric capacity, the second electric capacity, amplifier switch;
In the two ends of the first electric capacity described in each, wherein one end connects described amp.in, and the other end is for connecting the described pixel cell sensing circuit output terminal of each row in the cmos image sensor sensing circuit described in claim 15;
Described amplifier second electric capacity two ends are connected with described amp.in, output terminal respectively;
Described amplifier switch two ends are connected with described amp.in, output terminal respectively;
Described amplifier current bias input end is connected with described mirror current source row output terminal.
Optionally, described amplifier first electric capacity and amplifier second electric capacity are used in the PMOS realization made in P trap.
Compared with prior art, the technical scheme of the embodiment of the present invention has the following advantages:
I-V switching cell voltage output terminal is connect V-I converting unit first input end by switch, electric capacity is connected across between described V-I converting unit first input end and described first voltage, make the output voltage of I-V converting unit can remain on electric capacity two ends, cut-off switch can avoid the noise of reference current source to produce interference to the output of mirror current source, thus avoid the noise introducing reference current source and transistor, promote the performance of mirror current source.
Further, control by being connected to the duty of control module to mirror current source between described V-I converting unit current output terminal and image current source output terminal, mirror current source is not worked when not needing to provide electric current, thus reduce power consumption.
In addition, in the embodiment of the present invention, the mirror current source array of cmos image sensor sensing circuit inserts a less switch and a less electric capacity at the bias current sources grid end of each pixel cell, first all switch conductions, every row bias current sources grid end electric capacity is charged, cut-off switch after voltage stabilization on electric capacity, the bias voltage of current source just remains on the small capacitances two ends of its grid end respectively; Read the stage at pixel cell signal, because switch disconnects, the bias voltage of noise on pixel cell that reference current source and the transistor be attached thereto produce does not affect, thus avoids the noise introducing reference current source and transistor.Simultaneously, due to insert P cock and small capacitances be local, when the amplitude of pixel cell output signal is larger, the grid end of other row current source can't be recalcitrated by the grid source electric capacity of current source, also the bias current of other row pixel cell would not be had influence on, being expert in the highlighted place of image also can not be abnormal, thus promotes the picture quality of cmos image sensor.
Accompanying drawing explanation
Fig. 1 is a kind of existing mirror current source;
Fig. 2 is a kind of mirror current source in the embodiment of the present invention;
Fig. 3 is another kind of mirror current source in the embodiment of the present invention;
Fig. 4 is another mirror current source in the embodiment of the present invention;
Fig. 5 is another mirror current source in the embodiment of the present invention;
Fig. 6 is new a kind of mirror current source in the embodiment of the present invention;
Fig. 7 is a kind of mirror current source array in the embodiment of the present invention;
Fig. 8 is another kind of mirror current source array in the embodiment of the present invention;
Fig. 9 is a kind of cmos image sensor sensing circuit in the embodiment of the present invention;
Figure 10 is the sequential chart of the control method of a kind of cmos image sensor sensing circuit in the embodiment of the present invention;
Figure 11 is a kind of amplifying circuit in the embodiment of the present invention;
Figure 12 is a kind of PMOS in Nwell diagrammatic cross-section in the embodiment of the present invention;
Figure 13 is the C-V curve of a kind of PMOS in Nwell electric capacity in the embodiment of the present invention;
Figure 14 is a kind of PMOS in Pwel diagrammatic cross-section in the embodiment of the present invention;
Figure 15 is the C-V curve of a kind of PMOS in Pwell electric capacity in the embodiment of the present invention.
Embodiment
Mirror current source is widely used as previously mentioned, but the simple mirror current source as shown in Figure 1 that utilizes is biased, and can introduce the noise of reference current source and transistor.
I-V switching cell voltage output terminal is connect V-I converting unit first input end by switch by the embodiment of the present invention, electric capacity is connected across between described V-I converting unit first input end and described first voltage, make the output voltage of I-V converting unit can remain on electric capacity two ends, cut-off switch can avoid the noise of reference current source to produce interference to the output of mirror current source, thus avoid the noise introducing reference current source and transistor, promote the performance of mirror current source.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 2 is a kind of mirror current source in the embodiment of the present invention, comprising: I-V converting unit 22, V-I converting unit 25, switch 23, electric capacity 24.I-V converting unit 22 first input end is connected to described reference current source 21 output terminal, and I-V converting unit 22 voltage output end connects V-I converting unit 25 first input end by switch 23, and I-V converting unit 22 second input end P22 connects the first voltage; Electric capacity 24 is connected across between described V-I converting unit 25 first input end and described first voltage, and V-I converting unit second input end p22 is connected to the first voltage, and V-I converting unit 25 current output terminal P21 connects described image current source output terminal.I-V converting unit 22 produces the output voltage of different size according to the electric current of the different sizes of reference current source, and V-I converting unit 25 exports the electric current of different size by port P21 according to the control of above-mentioned voltage.I-V converting unit 22 voltage output end is connect V-I converting unit 25 first input end by switch 23, electric capacity 24 is connected across between described V-I converting unit 25 first input end and described first voltage, make the control voltage of I-V converting unit 22 can remain on electric capacity 24 two ends, cut-off switch 23 can avoid the noise of reference current source 21 and I-V converting unit 22 to produce interference to the output of mirror current source, thus avoid the noise introducing reference current source and transistor, promote the performance of mirror current source.
In concrete enforcement, reference current source can be band gap reference.
In concrete enforcement, mirror current source also comprises: be connected to the control module between described V-I converting unit current output terminal and image current source output terminal; Described control module input end is connected to described V-I converting unit current output terminal; Described control module control end selectivity is connected to the second voltage or tertiary voltage; Described control module output terminal is connected to described image current source output terminal.
Fig. 3 is another kind of mirror current source in the embodiment of the present invention, can find out, in current source as shown in Figure 3, reference current source 31, I-V converting unit 32, switch 33, electric capacity 34 and V-I converting unit 35 are consistent with current source as shown in Figure 2, do not repeat them here.Also comprise control module 36 in current source as shown in Figure 3, the input end of control module 36 is connected to V-I converting unit 35 current output terminal; Described control module control end P33 selectivity is connected to the second voltage or tertiary voltage; Control module output terminal P31 is connected to described image current source output terminal.Control module 36 is connected to the duty of the second voltage or tertiary voltage control mirror current source by control end P33, when not needing to provide image current to export, by control module, mirror current source is not worked, thus reduces the power consumption of mirror current source.
In concrete enforcement, mirror current source also comprises: the second control module; Described second control module input end is connected to described reference current source output terminal; Described second control module output terminal is connected to described I-V converting unit input end; The control voltage output terminal of described second control module is connected to described second voltage.
Fig. 4 is another mirror current source in the embodiment of the present invention, in current source as shown in Figure 4, reference current source 41, I-V converting unit 43, switch 44, electric capacity 45, V-I converting unit 46 and control module 47 are consistent with current source as shown in Figure 3, do not repeat them here.Also comprise the second control module 42, second control module 42 input end in current source as shown in Figure 4 and be connected to reference current source 41 output terminal; Second control module 42 output terminal is connected to I-V converting unit 43 input end; The control voltage output terminal of the second control module 42 when current source outgoing mirror image current, for control module 47 provides the second voltage.
In concrete enforcement, I-V converting unit comprises: the first NMOS tube; Described V-I unit comprises: the second NMOS tube; The drain electrode of described first NMOS tube and grid are connected to the first input end of described I-V converting unit jointly; The grid of described first NMOS tube is connected to the voltage output end of described I-V converting unit; The source electrode of described first NMOS tube is connected to the second input end of described I-V converting unit; The drain electrode of described second NMOS tube is connected to described V-I converting unit current output terminal; The grid of described second NMOS tube is connected to described V-I converting unit first input end; The source electrode of described second NMOS tube is connected to described V-I converting unit second input end.
Fig. 5 is another mirror current source in the embodiment of the present invention, comprising: reference current source 51, first NMOS tube 52, switch 53, electric capacity 54, second NMOS tube 55.The drain electrode of the first NMOS tube 52 and grid are connected to the output terminal of reference current source 51 jointly; The grid of the first NMOS tube 52 is connected to one end of switch 53; The source electrode of the first NMOS tube 52 connects the first voltage by port P52; The drain electrode of the second NMOS tube 55 by port P51 as image current source output terminal; The grid of the second NMOS tube 55 is connected to the other end of switch 53, and the source electrode of the second NMOS tube 55 connects the first voltage by port P52, between the grid that electric capacity 54 is connected across the second NMOS tube 55 and port P52.First NMOS tube 52 produces the output voltage of different size according to the electric current of the different sizes of reference current source 51, and the second NMOS tube 55 exports the electric current of different size by port P21 according to the control of above-mentioned voltage.First NMOS tube 52 voltage output end is connect the second NMOS tube 55 first input end by switch 23, electric capacity 54 is connected across between described second NMOS tube 55 first input end and described first voltage, make the control voltage of the first NMOS tube 52 can remain on electric capacity 54 two ends, cut-off switch can avoid the noise of reference current source 51 to produce interference to the output of mirror current source, thus avoid the noise introducing reference current source and transistor 52, promote the performance of mirror current source.
In an alternative embodiment of the invention, described I-V converting unit comprises: the drain electrode of described first NMOS tube and grid are connected to the first input end of described I-V converting unit jointly; The grid of described first NMOS tube is connected to the voltage output end of described I-V converting unit; The source electrode of described first NMOS tube is connected to the second input end of described I-V converting unit; The drain electrode of described second NMOS tube is connected to described V-I converting unit current output terminal; The grid of described second NMOS tube is connected to described V-I converting unit first input end; The source electrode of described second NMOS tube is connected to described V-I converting unit second input end; The source electrode of described 3rd NMOS tube is connected to described control module input end; The grid of described 3rd NMOS tube is connected to described control module control end; The drain electrode of described 3rd NMOS tube is connected to described control module output terminal.
Fig. 6 is new a kind of mirror current source in the embodiment of the present invention, and wherein, reference current source 61, first NMOS tube 62, switch 63, electric capacity 64 and the second NMOS tube 65 are consistent with mirror current source as shown in Figure 5, do not repeat them here.Mirror current source as shown in Figure 6 also comprises the 3rd NMOS tube 66, the source electrode of the 3rd NMOS tube 66 is connected to the drain electrode of the second NMOS tube 65, the grid of the 3rd NMOS tube 66 connects the second voltage or tertiary voltage by control end P63, control the duty of mirror current source, the drain electrode of the 3rd NMOS tube 66 is as the output terminal of mirror current source.3rd NMOS tube 66 is connected to the duty of the second voltage or tertiary voltage control mirror current source by control end P63, when not needing to provide image current to export, by the 3rd NMOS tube 66, mirror current source is not worked, thus reduce the power consumption of mirror current source.
In concrete enforcement, being connected to the first voltage can be ground connection.
In concrete enforcement, described second voltage can higher than described tertiary voltage.
In concrete enforcement, NMOS tube can be substituted by PMOS.Described first voltage is determined by described PMOS., described second voltage is lower than described tertiary voltage.
In concrete enforcement, the current mirror that I-V converting unit, V-I converting unit, control module, the second control module form jointly not only comprises simple current mirror, such as shown in Fig. 1, also comprise the current mirror of cascode structure, Wilson structure, high swing structure or other structure.
The embodiment of the present invention also provides a kind of mirror current source array, comprising: reference current source, I-V converting unit, N number of V-I converting unit, N number of switch, N number of electric capacity, N be more than or equal to 2 natural number; Described I-V converting unit first input end is connected to described reference current source output terminal, described I-V switching cell voltage output terminal is connected to the n-th V-I converting unit first input end by the n-th switch, 1≤n≤N, described I-V converting unit second input end is connected to the first voltage; Described n-th electric capacity is connected across the n-th V-I converting unit first input end and describedly connects between the first voltage, described each V-I converting unit second input end is connected to the first voltage, and described n-th V-I converting unit current output terminal connects described mirror current source array n-th output terminal.
Fig. 7 is a kind of mirror current source array in the embodiment of the present invention, and wherein, N value is 2, I-V converting unit is that in figure, the first NMOS tube the 72, one V-I converting unit is NMOS tube 75, and the 2nd V-I converting unit is NMOS tube 78.Concerning mirror current source first exports P71, by NMOS tube 72 voltage output end namely its grid connect NMOS tube 75 first input end by switch 73, electric capacity is connected across between described NMOS tube 75 first input end and described first voltage, the control voltage that NMOS tube 72 is provided can remain on electric capacity two ends, cut-off switch can avoid the noise of reference current source to produce interference to the output of mirror current source, thus avoid the noise introducing reference current source and transistor, promote the performance of mirror current source.Same principle is suitable for mirror current source second and exports P72.In addition, the every road due to mirror current source exports all switches different separately and electric capacity, nothing between different output branch road is influenced each other, further increases the performance of mirror current source.
In concrete enforcement, mirror current source array also comprises the N number of control module corresponding respectively to N row pixel cell, and described N number of control module is connected between described N number of V-I converting unit current output terminal and image current source output terminal; N-th control module input end is connected to the n-th V-I converting unit current output terminal, 1≤n≤N; Described n-th control module control end respectively selectivity is connected to the second voltage or tertiary voltage; Described n-th control module output terminal is connected to described mirror current source array n-th output terminal.
Fig. 8 is a kind of mirror current source array in the embodiment of the present invention, wherein, wherein, N value is 2, I-V converting unit is the first NMOS tube 84 in figure, first V-I converting unit is NMOS tube 86, second V-I converting unit metal-oxide-semiconductor 88, first control module is NMOS tube 82, second control module is NMOS tube 83, and two control modules, all by port P83 Access Control voltage, export the two-way of mirror current source array and control, mirror current source array is not worked when not needing to provide electric current, thus reduces power consumption.In figure, remaining circuit principle is consistent with aforementioned mirror current source array, does not repeat them here.
The embodiment of the present invention also provides a kind of cmos image sensor sensing circuit, comprising: mirror current source array, pixel unit array, pixel cell sensing circuit; Described mirror current source array n-th output terminal is connected to the n-th pixel cell; Described pixel cell sensing circuit is connected with described pixel unit array.
Fig. 9 is a kind of cmos image sensor sensing circuit in the embodiment of the present invention, the mirror current source array comprising two row pixel cells He have two-way to export.As can be seen from the figure, first pixel cell 91 is connected to the first output terminal of mirror current source array, second pixel cell 92 is connected to the second output terminal of mirror current source array, pixel cell sensing circuit 93 is connected with the second pixel cell with the first pixel cell respectively, for reading pixel cell data.
The embodiment of the present invention also provides a kind of control method of cmos image sensor sensing circuit: the n-th switch disconnects as shown in Figure 9, and described control module control end is connected to described tertiary voltage; N-th switch disconnects, and described control module control end is connected to described second voltage; N-th switch closes; N-th switch disconnects, and carries out read operation to described pixel cell.
Figure 10 is the sequential chart of the control method of a kind of cmos image sensor sensing circuit in the embodiment of the present invention, being a kind of control method for cmos image sensor sensing circuit as shown in Figure 9, is the first sequential chart arranged for first row pixel cell in Fig. 9 and mirror current source array.In figure, S1 is in low level representative graph 9 breaker in middle S1 and disconnects, and is in high level representation switch S1 and closes.The each node voltage of assumed initial state is 0, and in the phi1 stage, switch S 1 disconnects, and VN2 is low, M1 and M2 is operated in cut-off region, and the first pixel cell bias current is 0; In the phi2 stage, VN2 is high, and because node N1 voltage is still that 0, M2 is operated in dark linear zone, node N3 voltage can raise, and capacitance partial pressure makes the voltage of node N1 also raise; In the phi3 stage, switch S 1 conducting, reference current source charges to node N1, and M1 and M2 is all operated in state of saturation, and the first pixel cell bias current is determined by M1; In the phi4 stage, switch S 1 disconnects, and the bias voltage of M1 is kept by electric capacity C1, and the noise from reference current source and mirror image pipe is disconnected, and the first pixel cell signal is read out at this one-phase; In the phi5 stage, switch S 1 disconnects, and VN2 is low, and node N1 voltage can decline a little because of charge injection when S1 disconnects, and M1 is operated in linear zone, and M2 is operated in cut-off region, and the first pixel cell bias current is 0.For whole cmos image sensor sensing circuit, work schedule is also periodically through phi2 ~ phi5 stage, as can be seen from work schedule, the signal of pixel cell read in the phi4 stage, can not be subject to the impact from reference current source and mirror image pipe noise; Pel array only reading the stage by current source bias, after the reading stage, bias current sources electric current is 0, reduces power consumption; And the charging in phi4 stage is carried out on phi3 basis, and the duration of charging can greatly reduce.
In the embodiment of the present invention, the mirror current source array of cmos image sensor sensing circuit inserts a less switch and a less electric capacity at the bias current sources grid end of each pixel cell, first all switch conductions, every row bias current sources grid end electric capacity is charged, cut-off switch after voltage stabilization on electric capacity, the bias voltage of current source just remains on the small capacitances two ends of its grid end respectively; Read the stage at pixel cell signal, because switch disconnects, the bias voltage of noise on pixel cell that reference current source and the transistor be attached thereto produce does not affect, thus avoids the noise introducing reference current source and transistor.Simultaneously, due to insert P cock and small capacitances be local, when the amplitude of pixel cell output signal is larger, the grid end of other row current source can't be recalcitrated by the grid source electric capacity of current source, also the bias current of other row pixel cell would not be had influence on, being expert in the highlighted place of image also can not be abnormal, thus promotes the picture quality of cmos image sensor.
The embodiment of the present invention also provides a kind of amplifying circuit being applicable to cmos image sensor, is suitable for being configured at often row pixel cell, as shown in figure 11, comprises: operational amplifier OP, the first electric capacity C1, the second electric capacity C2, amplifier switch S1; In the two ends of described first electric capacity C1, wherein one end connects described operational amplifier OP input end, and the other end is suitable for being connected to cmos image sensor pixel cell signal output part; Operational amplifier OP second electric capacity C2 two ends are connected with described operational amplifier OP input end, output terminal respectively; Amplifier switch S11 two ends are connected with described operational amplifier OP input end, output terminal respectively; Operational amplifier OP current offset input end is connected with described mirror current source row output terminal.
Described pixel cell sensing circuit comprises: mirror current source array, pixel unit array, pixel cell sensing circuit; Described mirror current source array n-th output terminal is connected to the n-th pixel cell; Described pixel cell sensing circuit is connected with described pixel unit array.Described mirror current source array, comprising: reference current source, I-V converting unit, N number of V-I converting unit, N number of switch, N number of electric capacity, N be more than or equal to 2 natural number; Described I-V converting unit first input end is connected to described reference current source output terminal, described I-V switching cell voltage output terminal is connected to the n-th V-I converting unit first input end by the n-th switch, 1≤n≤N, described I-V converting unit second input end is connected to the first voltage; Described n-th electric capacity is connected across the n-th V-I converting unit first input end and describedly connects between the first voltage, described each V-I converting unit second input end is connected to the first voltage, and described n-th V-I converting unit current output terminal connects described mirror current source array n-th output terminal.The concrete structure of pixel cell sensing circuit and principle of work, see the cmos image sensor sensing circuit shown in mirror current source array as shown in Figure 8 and Fig. 9, do not repeat them here.
In order to obtain better picture quality and higher speed, in cmos image sensor sensing circuit, the signal of pixel cell often first amplifies through above-mentioned amplifying circuit, then delivers to next stage.The course of work being applicable to the amplifying circuit of cmos image sensor is as follows: first switch S 1 closes, and the electric charge of the upper preservation of C2 is released; Then switch S 1 disconnects, and after operational amplifier OP feedback re-establishes, the signal of pixel cell can be exported to next stage by the anti-phase amplification of operational amplifier OP, and gain is the ratio of C1 and C2.
The embodiment of the present invention also provides a kind of control method of amplifying circuit, for amplifying circuit in such as Figure 11: first switch S 1 closes, and the electric charge of the upper preservation of C2 is released; Then switch S 1 disconnects, and after amplifier feed-back re-establishes, the signal of pixel cell can be exaggerated the anti-phase amplification of device and export next stage to, and gain is the ratio of C1 and C2.
In concrete enforcement, amplifier first electric capacity and amplifier second electric capacity are used in the PMOS made in P trap and realize.The electric capacity that general amplifying circuit adopts is PIP capacitor, MOM capacitor, MIM capacitor etc., and the square capacitance (capacitance of unit area) of these electric capacity is less, and the area spent by electric capacity realizing certain capacitance is larger; In addition, adopt PIP capacitor and MIM capacitor to need additionally to increase mask plate, each of which increases the cost of chip.Based on this, propose a kind of electric capacity usage of uniqueness, this electric capacity is realized by PMOS in Pwell, and namely PMOS is produced in Pwell.Usually, PMOS is produced in Nwell, i.e. PMOS in Nwell, and its diagrammatic cross-section as shown in figure 12.As shown in figure 13, horizontal ordinate is gate source voltage to the C-V curve of PMOS in Nwell electric capacity, and ordinate is grid source electric capacity, time less demanding to capacitor's capacity, can be used as bias voltage filter capacitor etc.When gate source voltage is from 0 to negative change, PMOS in Nwell be in successively exhaust, weak transoid, strong inversion state, capacitance in this three stages acute variation, therefore and be not suitable for use in the gain capacitances of amplifier.If the C-V curve of Figure 13 to left, making the flat region of curve start from gate source voltage is near 0, then this electric capacity may be used for amplifier.By process simulation, test, the C-V curve of PMOS in Pwell electric capacity as shown in figure 14 as shown in figure 15, it is near 0 that its flat region starts from gate source voltage, when gate source voltage is comparatively negative, C-V curve is very smooth, therefore PMOS in Pwell electric capacity can be used as the gain capacitances of row amplifying circuit.The more important thing is, when input signals are small, the gate source voltage of input capacitance is more negative, be in the flat region of C-V curve, and the gate source voltage of feedback capacity is near 0, its capacitance is less than value during flat region, therefore the gain when gain of input signal hour is larger slightly larger than input signal.Therefore, adopt the natural advantage with anti-γ of PMOS in Pwell electric capacity, when dark scene, gain is bigger, and during bright field scape, gain is smaller, is more conducive to realize high-dynamics image.
I-V switching cell voltage output terminal is connect V-I converting unit first input end by switch by the embodiment of the present invention, electric capacity is connected across between described V-I converting unit first input end and described first voltage, make the control voltage of I-V converting unit can remain on electric capacity two ends, cut-off switch can avoid the noise of reference current source to produce interference to the output of mirror current source, thus avoid the noise introducing reference current source and transistor, promote the performance of mirror current source.Control by being connected to the duty of control module to mirror current source between described V-I converting unit current output terminal and image current source output terminal, mirror current source is not worked when not needing to provide electric current, thus reduce power consumption.
In addition, in the embodiment of the present invention, the mirror current source array of cmos image sensor sensing circuit inserts a less switch and a less electric capacity at the bias current sources grid end of each pixel cell, first all switch conductions, every row bias current sources grid end electric capacity is charged, cut-off switch after voltage stabilization on electric capacity, the bias voltage of current source just remains on the small capacitances two ends of its grid end respectively; Read the stage at pixel cell signal, because switch disconnects, the bias voltage of noise on pixel cell that reference current source and the transistor be attached thereto produce does not affect, thus avoids the noise introducing reference current source and transistor.Simultaneously, due to insert P cock and small capacitances be local, when the amplitude of pixel cell output signal is larger, the grid end of other row current source can't be recalcitrated by the grid source electric capacity of current source, also the bias current of other row pixel cell would not be had influence on, being expert in the highlighted place of image also can not be abnormal, thus promotes the picture quality of cmos image sensor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a mirror current source, is characterized in that, comprising: I-V converting unit, V-I converting unit, switch, electric capacity;
Described I-V converting unit first input end is connected to described reference current source output terminal, and described I-V switching cell voltage output terminal connects V-I converting unit first input end by switch, and described I-V converting unit second inputs termination first voltage;
Described electric capacity is connected across between described V-I converting unit first input end and described first voltage, and described V-I converting unit second input end is connected to described first voltage, and described V-I converting unit current output terminal is described image current source output terminal.
2. mirror current source according to claim 1, is characterized in that, described reference current source comprises band gap reference.
3. mirror current source according to claim 1, is characterized in that, described mirror current source also comprises:
Control module, is connected between described V-I converting unit current output terminal and image current source output terminal;
Described control module input end is connected to described V-I converting unit current output terminal;
Described control module control end selectivity is connected to the second voltage or tertiary voltage;
Described control module output terminal is connected to described image current source output terminal.
4. mirror current source according to claim 3, is characterized in that, described mirror current source also comprises: the second control module;
Described second control module input end is connected to described reference current source output terminal;
Described second control module output terminal is connected to described I-V converting unit input end;
The control voltage output terminal of described second control module is connected to described second voltage.
5. mirror current source according to claim 1, is characterized in that, described I-V converting unit comprises:
First NMOS tube; Described V-I unit comprises: the second NMOS tube;
The drain electrode of described first NMOS tube and grid are connected to the first input end of described I-V converting unit jointly;
The grid of described first NMOS tube is connected to the voltage output end of described I-V converting unit;
The source electrode of described first NMOS tube is connected to the second input end of described I-V converting unit;
The drain electrode of described second NMOS tube is connected to described V-I converting unit current output terminal;
The grid of described second NMOS tube is connected to described V-I converting unit first input end;
The source electrode of described second NMOS tube is connected to described V-I converting unit second input end.
6. mirror current source according to claim 3, is characterized in that, described control module comprises: the 3rd NMOS tube;
The drain electrode of described first NMOS tube and grid are connected to the first input end of described I-V converting unit jointly;
The grid of described first NMOS tube is connected to the voltage output end of described I-V converting unit;
The source electrode of described first NMOS tube is connected to the second input end of described I-V converting unit;
The drain electrode of the second NMOS tube is connected to described V-I converting unit current output terminal;
The grid of described second NMOS tube is connected to described V-I converting unit first input end;
The source electrode of described second NMOS tube is connected to described V-I converting unit second input end;
The source electrode of the 3rd NMOS tube is connected to described control module input end;
The grid of described 3rd NMOS tube is connected to described control module control end;
The drain electrode of described 3rd NMOS tube is connected to described control module output terminal.
7. the mirror current source according to claim 5 or 6, is characterized in that, described first voltage comprises: ground.
8. mirror current source according to claim 6, is characterized in that, described second voltage is higher than described tertiary voltage.
9. the mirror current source according to claim 5 or 6, is characterized in that, substitutes NMOS tube by PMOS.
10. mirror current source according to claim 9, is characterized in that, described first voltage is determined by described PMOS.
11. mirror current sources according to claim 9, is characterized in that, described second voltage is lower than described tertiary voltage.
12. 1 kinds of mirror current source arrays, is characterized in that, comprising: reference current source, I-V converting unit, N number of V-I converting unit, N number of switch, N number of electric capacity, N be more than or equal to 2 natural number;
Described I-V converting unit first input end is connected to described reference current source output terminal, described I-V switching cell voltage output terminal is connected to the n-th V-I converting unit first input end by the n-th switch, 1≤n≤N, described I-V converting unit second input end is connected to the first voltage;
Described n-th electric capacity is connected across the n-th V-I converting unit first input end and describedly connects between the first voltage, described each V-I converting unit second input end is connected to the first voltage, and described n-th V-I converting unit current output terminal connects described mirror current source array n-th output terminal.
13. mirror current source arrays according to claim 12, it is characterized in that, also comprise the N number of control module corresponding respectively to N row pixel cell, described N number of control module is connected between described N number of V-I converting unit current output terminal and image current source output terminal;
N-th control module input end is connected to the n-th V-I converting unit current output terminal, 1≤n≤N;
Described n-th control module control end respectively selectivity is connected to the second voltage or tertiary voltage;
Described n-th control module output terminal is connected to described mirror current source array n-th output terminal.
14. 1 kinds of cmos image sensor sensing circuits, is characterized in that, comprising: the mirror current source array as described in claim 12 or 13, pixel unit array, pixel cell sensing circuit;
Described mirror current source array n-th output terminal is connected to the n-th pixel cell;
Described pixel cell sensing circuit is connected with described pixel unit array.
The control method of 15. 1 kinds of cmos image sensor sensing circuits as claimed in claim 14, is characterized in that, comprising:
N-th switch disconnects, and described control module control end is connected to described tertiary voltage;
N-th switch disconnects, and described control module control end is connected to described second voltage;
N-th switch closes;
N-th switch disconnects, and carries out read operation to described pixel cell.
16. 1 kinds of amplifying circuits being applicable to cmos image sensor, are suitable for being configured at often row pixel cell, it is characterized in that, comprising: operational amplifier, the first electric capacity, the second electric capacity, amplifier switch;
In the two ends of the first electric capacity described in each, wherein one end connects described amp.in, and the other end is for connecting the described pixel cell sensing circuit output terminal of each row in the cmos image sensor sensing circuit described in claim 15;
Described operational amplifier second electric capacity two ends are connected with described amp.in, output terminal respectively;
Described operational amplifier switch ends is connected with described amp.in, output terminal respectively;
Described operational amplifier current bias input end is connected with described mirror current source row output terminal.
17. amplifying circuits according to claim 16, is characterized in that, described amplifier first electric capacity and amplifier second electric capacity are used in the PMOS made in P trap and realize.
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| CN201510082345.0A CN104679095A (en) | 2015-02-15 | 2015-02-15 | Current source, current source array, read-out circuit, control method of read-out circuit and amplification circuit |
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| CN201510082345.0A CN104679095A (en) | 2015-02-15 | 2015-02-15 | Current source, current source array, read-out circuit, control method of read-out circuit and amplification circuit |
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| CN106933295A (en) * | 2015-12-31 | 2017-07-07 | 北京同方微电子有限公司 | A kind of fast current mirror circuit |
| CN106933296A (en) * | 2015-09-30 | 2017-07-07 | 精工半导体有限公司 | Oscillating circuit |
| CN112068634A (en) * | 2019-06-11 | 2020-12-11 | 瑞昱半导体股份有限公司 | Reference voltage generating device |
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