CN104661299B - The method and system that TDD system synchronizes - Google Patents
The method and system that TDD system synchronizes Download PDFInfo
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- CN104661299B CN104661299B CN201310578705.7A CN201310578705A CN104661299B CN 104661299 B CN104661299 B CN 104661299B CN 201310578705 A CN201310578705 A CN 201310578705A CN 104661299 B CN104661299 B CN 104661299B
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- H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
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Abstract
The invention discloses the method and systems that a kind of TDD system synchronizes, and the described method comprises the following steps：Obtain the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm；The switching information is mapped in switch data block, and the switch data block is sent to the far-end unit in the TDD system；The switching information is obtained from the switch data block by demapping, the synchronism switching of uplink downlink is realized in the far-end unit.Implement the method and system that the TDD system of the present invention synchronizes, while the uplink downlink of far-end unit and proximal end unit in accurately realizing whole system keeps synchronism switching, it can be removed for generating the hardware such as control logic and the filter circuit of synchronizing signal in far-end unit, and then reduce cost.
Description
Technical field
The present invention relates to wireless communication technology field, the method and system synchronized more particularly to a kind of TDD system.
Background technology
In wireless communication technique, TDD（Time Division Duplexing, time division duplex）Synchronous communication system is such as
TD-SCDMA（Time Division-Synchronous Code Division Multiple Access, time division synchronous code division
Multiple access）、TD-LTE（Time Division Long Term Evolution, timesharing long term evolution）Equal needs design is corresponding
Synchronized algorithm generates the switching switch needed for uplink and downlink, to realize the time-division multiplexing function of system.
In traditional repeater formula TDD synchronous communication systems, entire communication system includes multiple subsystems, each subsystem
System includes a proximal end unit and multiple far-end units, and wireless signal needs to realize the amplification of signal by whole system, that is, believes
Number proximally life is prolonged in the covering of the antenna opening of unit to the antenna opening of far-end unit.In the communication process of TDD system, proximal end is single
The Logic control module of member proposes signal characteristic, is generated by specific algorithm for controlling uplink and downlink operation
The synchronous switch of situation.In the data traffic transmission period of downlink, generated switch control logic connects downlink
Logical, uplink disconnects at this time, and the antenna opening of signal proximally unit flows to the antenna opening of far-end unit, otherwise in uplink
The data traffic transmission period, signal flows to the antenna opening of proximal end unit from the antenna opening of far-end unit.
In traditional method, in order to realize that above-mentioned communication process, proximal end unit and far-end unit need independently to extract
Signal characteristic is realized synchronous and generates corresponding synchronous switch, but this mode usually along with additional hardware spending and is patrolled
Resource overhead is collected, the complexity of hardware cost and realization is significantly increased.
Invention content
Based on this, it is necessary in tdd communication systems, hardware cost is high when realizing synchronized algorithm, realizes process
The high problem of complexity provides a kind of method and system that TDD system synchronizes.
A kind of method that TDD system synchronizes, includes the following steps：
Obtain the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm；
The switching information is mapped in switch data block, and the switch data block is sent to the TDD system
In far-end unit；
The switching information is obtained from the switch data block by demapping, is realized up and down in the far-end unit
The synchronism switching of line link.
A kind of system that TDD system synchronizes, including：
First acquisition module, the switching uplink and downlink generated by synchronized algorithm for obtaining the proximal end unit in TDD system
The switching information of link；
Mapping block is transmitted for the switching information to be mapped in switch data block, and by the switch data block
To the far-end unit in the TDD system；
De-mapping module obtains the switching information for passing through demapping from the switch data block, described remote
The synchronism switching of uplink downlink is realized in end unit.
The method and system that above-mentioned TDD system synchronizes, by generating the proximal end unit in TDD system by synchronized algorithm
The switching information of switching uplink downlink be mapped in switch data block, be transmitted to far-end unit side, and pass through demapping
Mode restore the switching information, can accurately realize in each far-end unit of TDD system synchronous with proximal end unit upper
Downlink handover.Switching information is all from proximal end unit, improves synchronous consistency, and without adding life in far-end unit
The related hardwares such as logic, inspection filter circuit are generated at the synchronized algorithm and switch of the switching information, significantly reduce system
Manufacturing cost and simultaneously operating complexity.
A kind of method that TDD system synchronizes, includes the following steps：
The switch data block for being sent to the far-end unit in TDD system is obtained, the switch data block is mapped with the TDD systems
The switching information for the switching uplink downlink that proximal end unit in system is generated by synchronized algorithm；
The switching information is obtained from the switch data block by demapping, is realized up and down in the far-end unit
The synchronism switching of line link.
A kind of system that TDD system synchronizes, including：
Second acquisition module, for obtaining the switch data block for being sent to the far-end unit in TDD system, the switch data
Block is mapped with the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm；
De-mapping module obtains the switching information for passing through demapping from the switch data block, described remote
The synchronism switching of uplink downlink is realized in end unit.
The method and system that above-mentioned TDD system synchronizes, in distal end side from from proximal end unit by way of demapping
Restore the switching information in the switch data block of side, can be realized in each far-end unit of TDD system same with proximal end unit
The uplink downlink of step switches.Switching information is all from proximal end unit, therefore improves synchronous consistency, and in far-end unit
Without adding the related hardware for generating the switching information, the manufacturing cost of system and the complexity of simultaneously operating are reduced.
A kind of method that TDD system synchronizes, includes the following steps：
Obtain the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm；
The switching information is mapped in switch data block, and the switch data block is sent to the TDD system
In far-end unit.
A kind of system that TDD system synchronizes, including：
First acquisition module, the switching uplink and downlink generated by synchronized algorithm for obtaining the proximal end unit in TDD system
The switching information of link；
Mapping block is transmitted for the switching information to be mapped in switch data block, and by the switch data block
To the far-end unit in the TDD system.
The method and system that above-mentioned TDD system synchronizes, in proximal end unit side by being opened described in the generation of nearly end unit
It closes in information MAP to the switch data block, and gets forwarded to far-end unit side, to be realized in each far-end unit of TDD system
Synchronous with proximal end unit uplink downlink switching provides the switching information this source signal.Switching information is all from proximal end
Unit improves synchronous consistency, and is reduced in far-end unit without adding the related hardware for generating the switching information
The manufacturing cost of system.
Description of the drawings
Fig. 1 is the flow diagram for the method first embodiment that TDD system of the present invention synchronizes；
Fig. 2 is the flow diagram for the method second embodiment that TDD system of the present invention synchronizes；
Fig. 3 is the flow diagram for the method third embodiment that TDD system of the present invention synchronizes；
Fig. 4 is the structural schematic diagram for the system first embodiment that TDD system of the present invention synchronizes；
Fig. 5 is the structural schematic diagram for the system third embodiment that TDD system of the present invention synchronizes；
Fig. 6 is the schematic diagram of operating process of the method for TDD system synchronization of the present invention in far-end unit side；
Fig. 7 is structural schematic diagram of the system in far-end unit side of TDD system synchronization of the present invention；
Fig. 8 is the schematic diagram of operating process of the method for TDD system synchronization of the present invention in proximal end unit side；
Fig. 9 is structural schematic diagram of the system in proximal end unit side of TDD system synchronization of the present invention.
Specific implementation mode
Technical scheme of the present invention is described in detail below in conjunction with the accompanying drawings.
Referring to Fig. 1, Fig. 1 is the flow diagram for the method first embodiment that TDD system of the present invention synchronizes.
The method that the TDD system of present embodiment synchronizes includes the following steps：
Step 101, the switch for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm is obtained
Information.
Step 102, the switching information is mapped in switch data block, and the switch data block is sent to described
Far-end unit in TDD system.
Step 103, the switching information is obtained from the switch data block by demapping, in the far-end unit
Realize the synchronism switching of uplink downlink.
The switch of the switching uplink downlink generated by synchronized algorithm by the proximal end unit that will be originated from TDD system is believed
Breath is mapped to the far-end unit being sent in switch data block to be sent in TDD system, can avoid occurring in traditional approach by
Lead to the inconsistency of the indexs such as entire TDD system synchronous dynamic range in the inconsistency of detection module parameter or circuit parameter
The case where.
Demapping corresponding with mapping mode is carried out by the switch data block for being mapped with switching information that will be received, is restored
Switching information, and then synchronism switching uplink downlink is realized in each far-end unit, the synchronous calculation in each far-end unit can be removed
Method and switch generate logic and various related hardwares, particularly for analog machine, it is thus only necessary to be restored switch by light path
, completely without additional control logic and circuit overhead, the intrinsic cost of whole system is made to decline.
For step 101, the switching information preferably can be calculated by synchronized algorithm and switching logic it is close
The logic level DATA of switching switch in end unit for switching uplink downlink indicates that switch is in low electricity using number 0
Flat logic indicates that switch is in high level logic using number 1.The switching information can also be in the unit of proximal end for switching
The pulse sequence of the switching switch of uplink downlink, the pulse sequence in each period are continued by low duration and high level
Time forms.The switching information can also be this field, and other are usual for indicating in the unit of proximal end for switching uplink and downlink
The information of the switching switch of link.
For step 102, the mode of mapping includes that the switch data block directly is written, by switching information in switching information
Signature identification be written at least partly switch data block or according to technological means customary in the art by switching information with switching
Data information data in the block is corresponded to.
The switch data block preferably can be data flow based on various base band-radio frequency interface agreement, data frame or
Data packet can also be other data modes customary in the art.The base band-radio frequency interface agreement includes CPRI (The
Common Public Radio Interface) agreement, OBSAI（Open Base Station Architecture
Initiative）Agreement and TDRI agreements（Baseband extension agreement）Deng.
The mode for transmitting the switch data block includes transparent transmission, broadcast type transmission or other propagation customary in the art
Mode.
In one embodiment, the switching information is the logic level DATA for switching switch in the proximal end unit,
In, the logic level DATA can be mapped in the switch data block, it is described that the switching information is mapped to switching number
Include the following steps according to step in the block：
Step 1021, the logic level DATA and the base band data are subjected to data splicing.
Step 1022, spliced data are mapped in the switch data block.
In step 1021, the base-band data stream N-bit being transmitted is needed, by taking N=3 as an example, the low level moment is with base band
Data flow（000,010,111,101）For, become after the low level of above-mentioned data flow and switching switch is carried out data splicing
（0000,0100,1110,1010）.It is in the base-band data stream at the high level moment of switch（111,101,001,110）, carry out
Become after data splicing（1111,1011,0011,1101）, spliced base band data becomes the data flow of N+1 bit.
When carrying out data splicing in this step, for inserting the logical data of switching switch in the rearmost position of base band data,
The logical data can also be inserted to the other positions in base-band data stream in the present embodiment.
In step 1022, the spliced data flow of data is formed by the mapping based on a certain base band-radio frequency protocol
Switch data block containing switching information.
Operation in above-described embodiment, it is only necessary to be spliced by data and the mapping based on a certain base band-radio frequency protocol is formed
Switch data block containing switching information, you can the data block is sent to far-end unit, in far-end unit to carrying out data
Stripping and demapping can restore switching information, without synchronizing the synchronous switch of the complexity such as algorithm, filtering in far-end unit
Generating process, therefore can greatly simplify the process that synchronism switching uplink downlink is realized in each far-end unit.
In another embodiment, the switching information is the pulse sequence for switching switch in the proximal end unit, described
Switch data block is the radio frames based on CPRI agreements, wherein can be mapped to the pulse sequence described based on CPRI agreements
Radio frames in, it is described the switching information is mapped to switch data step in the block to include the following steps：
Step 1023, pulse period, high level lasting time and the low level of the pulse sequence of the switching switch are obtained
At least one of these three timing informations of duration.In this step, when pulse period constant holding predetermined value, it is only necessary to obtain
Take high level lasting time or low duration；When pulse period changes at random, two in three timing informations need to be obtained
It is a.
Step 1024, from the radio frames based on CPRI agreements, at least two are chosen for mapping the pulse sequence
Superframe.In this step, when pulse period constant holding predetermined value, two superframes are chosen；When pulse period changes at random, choose
Three superframes.
Step 1025, according to the high level of the first superframe and the pulse sequence at least two superframes of selection or low
The trip point of level（The switching moment）, obtain the base of the time location of a trip point for identifying the pulse sequence
Between punctual.In this step, by analyzing the first superframe（Can be any one in the superframe chosen）Sequential and described
The pulse sequence for switching switch, according to the specific trip point of mark（The starting point of high level or low level starting point）It calculates
The time value of the fiducial time.
Step 1026, any one control word domain of first superframe is written using the fiducial time as byte value
In, except described at least two superframes that at least one of three timing informations of acquisition are chosen as byte value write-in
In the arbitrary control word domain of other superframes outside one superframe.One superframe corresponds to a time value.
Operation in above-described embodiment, by by the letter of the timing information of the pulse sequence and the time location of trip point
The corresponding mode being inserted into the control word of radio frames of breath, switching information is mapped in switch data block, does not both consume base band number
According to useful bandwidth, and the recovery of switching information can be realized in far-end unit.
For step 103, the mapping process in corresponding step 102 carries out demapping.
In one embodiment, the switching information is the logic level DATA for switching switch in the proximal end unit, institute
The step of obtaining the switching information from the switch data block by demapping is stated to include the following steps：
The spliced data are parsed from the switch data block；
The logic level DATA is removed from the spliced data, obtains the base band data and described
Logic level DATA.
Information is removed in above-mentioned steps（Solution splicing）The process spliced of process and data it is completely the same.Before such as solving splicing
Data flow be：（1111,1011,0011,1101）, then solving spliced base-band data stream is（111,101,001,110）, high
Level logic is（1,1,1,1）, it is preferable that it can be by being based on a certain base band-radio frequency protocol（It is consistent with mapping process）Solution reflect
The mode penetrated parses the spliced data flow from the switch data block.
In another embodiment, the switching information is the pulse sequence for switching switch in the proximal end unit, described
Switch data block is the radio frames based on CPRI agreements, wherein can the pulse sequence be based on CPRI described in receive
Demapping goes out in the radio frames of agreement, described the step of obtaining the switching information from the switch data block by demapping
Include the following steps：
The byte value of each byte of the radio frames is detected successively, if detecting the non-zero byte of byte value, immediate record inspection
The time value of timing position of the byte value and the non-zero byte measured in the radio frames（Non-zero word where fiducial time
The trip point of the pulse sequence of the corresponding switching switch of section）.
According to the pulse of the pulse sequence of the byte value of record, the time value of record and/or the scheduled switching switch
Period restores the pulse sequence.
An above-mentioned radio frames based on CPRI agreements include 150 superframes（Hyper Frame）, each superframe includes
256 base frames (Basic Frame), base frame is the basic unit transmitted by CPRI.The length of one base frame is equal to wireless communication
Number a chip (chip) length, the transmission cycle of each base frame is 1/3.84MHz.Wherein, each CPRI bases frame includes
16 words, in 16 words, including 1 control word (Control Word) and for carrying inphase quadrature（IQ, In-phase
Quardrature）15 words of data, the control data and each manufacturer that control word is used to carry in addition to I/Q data are made by oneself
The control word information of justice.
In other embodiments, those skilled in the art can also record the fiducial time and sequential letter in advance
The byte information of the residing control word of breath from the switch data block obtains the switching information described by demapping
In step, the non-zero byte of byte value is directly detected according to the byte information of record, and then restore the time sequential pulse.
Referring to Fig. 2, Fig. 2 is the flow diagram for the method second embodiment that TDD system of the present invention synchronizes.
The main distinction for the method and the first embodiment that the TDD system of present embodiment synchronizes is, institute
It is the pulse sequence for switching switch in the proximal end unit to state switching information, and the switch data block is the nothing based on CPRI agreements
Line frame, it is described the switching information is mapped to switch data step in the block to specifically include following steps：
Step 201, the low level duration of the pulse sequence is obtained.
Step 202, it is chosen out of described radio frames and the trip point time interval minimum of the high level of the pulse sequence
Superframe, wherein the superframe of the time interval minimum is in after the high level.
Step 203, using the predetermined period of the pulse sequence subtract preset time delay value with it is described it is low level continue when
Between and minimum time away from distance values summation, obtain fiducial time, wherein the minimum time is away from for the high level and institute
State the time interval between the superframe of time interval minimum.
Step 204, the time interval is written into as byte value in the low level duration and the fiducial time
In two default control words of minimum superframe, wherein the default control word for the fiducial time to be written and the time
Time difference between superframe header away from minimum superframe is the preset time delay value.
Operating process in the above embodiment is only the specific embodiment of the present invention, and being not used in restriction, other are implemented
Mode.The pulse sequence of the switching switch can be mapped to the nothing by the present invention by other conventional techniques of this field
In line frame.
Referring to Fig. 3, Fig. 3 is the flow diagram for the method third embodiment that TDD system of the present invention synchronizes.
The main distinction for the method and the first embodiment that the TDD system of present embodiment synchronizes is,
According to the predetermined period of the time value and the pulse sequence of the byte value of record, record, after restoring the pulse sequence, into
One step includes the following steps：
Step 301, the delay inequality for obtaining the process for restoring the pulse sequence carries out sequential school to the pulse sequence
It is accurate.
Existing systematic error aforesaid operations are by carrying out switching information recovery in obtaining step 103 when, and then correct extensive
Multiple pulse sequence can greatly improve the accuracy of the pulse sequence of recovery, and it is synchronous with proximal end unit to improve far-end unit
Consistency.
Referring to Fig. 4, Fig. 1 is the structural schematic diagram for the system first embodiment that TDD system of the present invention synchronizes.
The system that the TDD system of present embodiment synchronizes includes the first acquisition module 110, the reconciliation of mapping block 120
Mapping block 130, wherein：
First acquisition module 110, above and below the switching generated by synchronized algorithm for obtaining the proximal end unit in TDD system
The switching information of line link.
Mapping block 120 is passed for the switching information to be mapped in switch data block, and by the switch data block
It send to the far-end unit in the TDD system.
De-mapping module 130 obtains the switching information, described for passing through demapping from the switch data block
The synchronism switching of uplink downlink is realized in far-end unit.
The switch of the switching uplink downlink generated by synchronized algorithm by the proximal end unit that will be originated from TDD system is believed
Breath is mapped to the far-end unit being sent in switch data block to be sent in TDD system, can avoid occurring in traditional approach by
Lead to the inconsistency of the indexs such as entire TDD system synchronous dynamic range in the inconsistency of detection module parameter or circuit parameter
The case where.
Demapping corresponding with mapping mode is carried out by the switch data block for being mapped with switching information that will be received, is restored
Switching information, and then synchronism switching uplink downlink is realized in each far-end unit, the synchronous calculation in each far-end unit can be removed
Method and switch generate logic and various related hardwares, particularly for analog machine, it is thus only necessary to be restored switch by light path
, completely without additional control logic and circuit overhead, the intrinsic cost of whole system is made to decline.
For the first acquisition module 110, the switching information can be calculated by synchronized algorithm and switching logic
The logic level DATA of switching switch in obtained proximal end unit for switching uplink downlink indicates to switch using number 0
In low-level logic, indicate that switch is in high level logic using number 1.The switching information can also be in the unit of proximal end
Pulse sequence for the switching switch for switching uplink downlink, the pulse sequence in each period is by low duration and height
Level duration forms.The switching information can also be this field, and other are usual for indicating in the unit of proximal end for cutting
Change the information of the switching switch of downlink.
For mapping block 120, the mode of mapping includes that the switch data block directly is written in switching information, will be switched
The signature identification of information be written at least partly switch data block or according to technological means customary in the art by switching information with
Switch data information data in the block is corresponded to.
The switch data block preferably can be data flow based on various base band-radio frequency interface agreement, data frame or
Data packet can also be other data modes customary in the art.The base band-radio frequency interface agreement includes CPRI (The
Common Public Radio Interface) agreement, OBSAI（Open Base Station Architecture
Initiative）Agreement and TDRI agreements（Baseband extension agreement）Deng.
The mode for transmitting the switch data block includes transparent transmission, broadcast type transmission or other propagation customary in the art
Mode.
In one embodiment, the switching information is the logic level DATA for switching switch in the proximal end unit,
In, the logic level DATA can be mapped in the switch data block, the mapping block 120 is used for logic electricity
Flat data carry out data splicing with the base band data, spliced data are mapped in the switch data block.
In a tdd system, need the base-band data stream being transmitted be N-bit when, by taking N=3 as an example, the low level moment with
Base-band data stream（000,010,111,101）For, mapping block 120 can by above-mentioned data flow with switching switch low level into
Row data are spliced, and data flow becomes after carrying out data splicing（0000,0100,1110,1010）.At high level moment of switch
Base-band data stream is（111,101,001,110）, become after carrying out data splicing（1111,1011,0011,1101）, after splicing
Base band data become the data flow of N+1 bit.When mapping block 120 carries out data splicing, patrolling for switch will be switched
It collects data to insert for the rearmost position of base band data, the logical data can also be inserted in the present embodiment in base band
The other positions of data flow.
The spliced data flow of data is also passed through and is assisted based on a certain base band-radio frequency by mapping block 120 in the present embodiment
The mapping of view forms the switch data block containing switching information.
Operation in above-described embodiment, it is only necessary to be spliced by data and the mapping based on a certain base band-radio frequency protocol is formed
Switch data block containing switching information, you can the data block is sent to far-end unit, in far-end unit to carrying out data
Stripping and demapping can restore switching information, without synchronizing the synchronous switch of the complexity such as algorithm, filtering in far-end unit
Generating process, therefore can greatly simplify the process that synchronism switching uplink downlink is realized in each far-end unit.
In another embodiment, the switching information is the pulse sequence for switching switch in the proximal end unit, described
Switch data block is the radio frames based on CPRI agreements, wherein the pulse sequence can be mapped to the base by mapping block 120
In the radio frames of CPRI agreements, the mapping block 120 is for performing the following operations：
Obtain it is described switching switch pulse sequence pulse period, high level lasting time and low duration this
At least one of three timing informations.In this step, when pulse period constant holding predetermined value, it is only necessary to obtain high level and hold
Continuous time or low duration；When pulse period changes at random, two in three timing informations need to be obtained.
From the radio frames based on CPRI agreements, at least two superframes for mapping the pulse sequence is chosen.At this
In step, when pulse period constant holding predetermined value, two superframes are chosen；When pulse period changes at random, three superframes are chosen.
According to the high level of the first superframe and the pulse sequence at least two superframes of selection or low level jump
Height（The switching moment）, obtain the fiducial time of the time location of a trip point for identifying the pulse sequence.
In this step, by analyzing the first superframe（Can be any one in the superframe chosen）Sequential and the switching switch
Pulse sequence, according to the specific trip point of mark（The starting point of high level or low level starting point）Calculate the benchmark
The time value of time.
It is written the fiducial time as byte value in any one control word domain of first superframe, by acquisition
In at least two superframes that at least one of three timing informations are chosen as byte value write-in in addition to first superframe
In the arbitrary control word domain of other superframes.One superframe corresponds to a time value.
Operation in above-described embodiment, by by the letter of the timing information of the pulse sequence and the time location of trip point
The corresponding mode being inserted into the control word of radio frames of breath, switching information is mapped in switch data block, does not both consume base band number
According to useful bandwidth, and the recovery of switching information can be realized in far-end unit.
For De-mapping module 130, the mapping process in correspondence mappings module 120 carries out demapping.
In one embodiment, the switching information is the logic level DATA for switching switch in the proximal end unit, institute
De-mapping module 130 is stated for parsing the spliced data from the switch data block, by the logic level number
It is removed according to from the spliced data, obtains the base band data and the logic level DATA.
It is removed into row information in above-mentioned De-mapping module 130（Solution splicing）Process and 120 data of mapping block splicings
Process is completely the same.Such as solving the data flow before splicing is：（1111,1011,0011,1101）, then spliced base band data is solved
Stream is（111,101,001,110）, high level logic is（1,1,1,1）, it is preferable that it can be assisted by being based on a certain base band-radio frequency
View（It is consistent with mapping process）Demapping mode, the spliced data flow is parsed from the switch data block
Come.
In another embodiment, the switching information is the pulse sequence for switching switch in the proximal end unit, described
Switch data block is the radio frames based on CPRI agreements, wherein De-mapping module 130 can map the pulse sequence from reception
Demapping in radio frames based on CPRI agreements described in, the De-mapping module 130 is for performing the following operations：
The byte value of each byte of the radio frames is detected successively, if detecting the non-zero byte of byte value, immediate record inspection
The time value of timing position of the byte value and the non-zero byte measured in the radio frames（Non-zero word where fiducial time
The trip point of the pulse sequence of the corresponding switching switch of section）.
According to the pulse of the pulse sequence of the byte value of record, the time value of record and/or the scheduled switching switch
Period restores the pulse sequence.
An above-mentioned radio frames based on CPRI agreements include 150 superframes（Hyper Frame）, each superframe includes
256 base frames (Basic Frame), base frame is the basic unit transmitted by CPRI.The length of one base frame is equal to wireless communication
Number a chip (chip) length, the transmission cycle of each base frame is 1/3.84MHz.Wherein, each CPRI bases frame includes
16 words, in 16 words, including 1 control word (Control Word) and for carrying inphase quadrature（IQ, In-phase
Quardrature）15 words of data, the control data and each manufacturer that control word is used to carry in addition to I/Q data are made by oneself
The control word information of justice.
In other embodiments, those skilled in the art can also record the fiducial time and sequential letter in advance
The byte information of the residing control word of breath, when obtaining the switching information from the switch data block by demapping, directly
It connects and the non-zero byte of byte value is detected according to the byte information of record, and then restore the time sequential pulse.
It is the second embodiment for the system that TDD system of the present invention synchronizes below.
The main distinction for the system and the first embodiment that the TDD system of second embodiment of the invention synchronizes
It is, the switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is based on CPRI
The radio frames of agreement, the mapping block 120 specifically execute following operation：
Obtain the low level duration of the pulse sequence.
The superframe with the trip point time interval minimum of the high level of the pulse sequence is chosen out of described radio frames,
In, the superframe of the time interval minimum is in after the high level.
Preset time delay value and the low level duration and minimum are subtracted using the predetermined period of the pulse sequence
The summation of the distance values of time interval obtains fiducial time, wherein the minimum time is away from for the high level and the time interval
Time interval between minimum superframe.
The super of the time interval minimum is written into as byte value in the low level duration and the fiducial time
In two default control words of frame, wherein the default control word for the fiducial time to be written and time interval minimum
Time difference between the superframe header of superframe is the preset time delay value.
Operating process in the above embodiment is only the specific embodiment of the present invention, and being not used in restriction, other are implemented
Mode.The pulse sequence of the switching switch can be mapped to the nothing by the present invention by other conventional techniques of this field
In line frame.
Referring to Fig. 5, Fig. 5 is the structural schematic diagram for the system third embodiment that TDD system of the present invention synchronizes.
The main distinction for the system and the first embodiment that the TDD system of present embodiment synchronizes is, into
One step includes correction module 140, and the correction module 140 is used to obtain the delay inequality for the process for restoring the pulse sequence, right
The pulse sequence carries out timing alignment.
Existing systematic error when aforesaid operations are by obtaining the progress switching information recovery of De-mapping module 130, and then school
The pulse sequence just restored can greatly improve the accuracy of the pulse sequence of recovery, improve far-end unit and proximal end unit is same
The consistency of step.
Referring to Fig. 6, the signal of operating process of the method that Fig. 6, which is TDD system of the present invention, to be synchronized in far-end unit side
Figure, includes the following steps：
Step 601, the switch data block for being sent to the far-end unit in TDD system is obtained, the switch data block is mapped with
The switching information for the switching uplink downlink that proximal end unit in the TDD system is generated by synchronized algorithm.
Step 602, the switching information is obtained from the switch data block by demapping, in the far-end unit
Realize the synchronism switching of uplink downlink.
Above-mentioned steps 601 correspond to the switch data block for obtaining and being sent in the step 102 described in Fig. 1, above-mentioned steps 602 and figure
Step 103 described in 1 is identical.The reality of its enforceable embodiment synchronous method of the TDD system corresponding with Fig. 1
It is consistent to apply mode.
Aforesaid operations step is carried out corresponding to mapping mode by the switch data block for being mapped with switching information that will be received
Demapping, restore switching information, and then realize synchronism switching uplink downlink in each far-end unit, it is single that each distal end can be removed
Synchronized algorithm and switch in member generate logic and various related hardwares, particularly for analog machine, it is thus only necessary to pass through light
Switch is restored on road, completely without additional control logic and circuit overhead, the intrinsic cost of whole system is made to decline.
Referring to Fig. 7, structural schematic diagram of the system that Fig. 7, which is TDD system of the present invention, to be synchronized in far-end unit side, described
The system that TDD system synchronizes includes the second acquisition module 150 and De-mapping module 130, wherein：
Second acquisition module 150, for obtaining the switch data block for being sent to the far-end unit in TDD system, the switching
Data block is mapped with the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm.
De-mapping module 130 obtains the switching information, described for passing through demapping from the switch data block
The synchronism switching of uplink downlink is realized in far-end unit.
Above-mentioned second acquisition module 150 is used to obtain the switch data block that the mapping block 120 described in Fig. 4 is sent, above-mentioned
De-mapping module 130 is identical with the De-mapping module 130 described in Fig. 1.
Demapping corresponding with mapping mode is carried out by the switch data block for being mapped with switching information that will be received, is restored
Switching information, and then synchronism switching uplink downlink is realized in each far-end unit, the synchronous calculation in each far-end unit can be removed
Method and switch generate logic and various related hardwares, particularly for analog machine, it is thus only necessary to be restored switch by light path
, completely without additional control logic and circuit overhead, the intrinsic cost of whole system is made to decline.
Referring to Fig. 8, the signal of operating process of the method that Fig. 8, which is TDD system of the present invention, to be synchronized in proximal end unit side
Figure, the system that the TDD system synchronizes include the following steps：
Step 801, the switch for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm is obtained
Information.
Step 802, the switching information is mapped in switch data block, and the switch data block is sent to described
Far-end unit in TDD system.
Above-mentioned steps 801 are identical with the step 101 described in Fig. 1, for sending cutting for step 601 acquisition described in Fig. 6
Data block is changed, above-mentioned steps 802 are identical with the step 102 described in Fig. 1.Its enforceable embodiment is corresponding with Fig. 1
The embodiment for the method that the TDD system synchronizes is consistent.Pass through synchronized algorithm by the proximal end unit that will be originated from TDD system
The switching information of the switching uplink downlink of generation is mapped to the distal end being sent in switch data block to be sent in TDD system
Unit can avoid occurring in traditional approach since the inconsistency of detection module parameter or circuit parameter leads to entire TDD system
The case where inconsistency of the indexs such as synchronous dynamic range.
Referring to Fig. 9, structural schematic diagram of the system that Fig. 9, which is TDD system of the present invention, to be synchronized in proximal end unit side, described
The system that TDD system synchronizes includes the first acquisition module 110 and mapping block 120, wherein：
First acquisition module 110, above and below the switching generated by synchronized algorithm for obtaining the proximal end unit in TDD system
The switching information of line link.
Mapping block 120 is passed for the switching information to be mapped in switch data block, and by the switch data block
It send to the far-end unit in the TDD system.
The first acquisition module 110 that above-mentioned first acquisition module 110 is used to receive described in Fig. 4 is identical, above-mentioned mapping
Module 120 is identical with the mapping block 120 described in Fig. 1, for sending cutting for the acquisition of the second acquisition module 150 in Fig. 7
Change data block.
The switch of the switching uplink downlink generated by synchronized algorithm by the proximal end unit that will be originated from TDD system is believed
Breath is mapped to the far-end unit being sent in switch data block to be sent in TDD system, can avoid occurring in traditional approach by
Lead to the inconsistency of the indexs such as entire TDD system synchronous dynamic range in the inconsistency of detection module parameter or circuit parameter
The case where.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
Cannot the limitation to the scope of the claims of the present invention therefore be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (16)
1. a kind of method that TDD system synchronizes, which is characterized in that include the following steps：
Obtain the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm；
The switching information is mapped in switch data block, and the switch data block is sent in the TDD system
Far-end unit；
The switching information is obtained from the switch data block by demapping, uplink and downlink chain is realized in the far-end unit
The synchronism switching on road；
The switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is to be assisted based on CPRI
The radio frames of view；
The TDD system is time division duplex synchronous system, and the CPRI agreements are base band-radio frequency interface agreement.
2. the method that TDD system according to claim 1 synchronizes, which is characterized in that the switching information is the proximal end
Switch the logic level DATA of switch in unit, it is described by the switching information be mapped to switch data step in the block include with
Lower step：
The logic level DATA and base band data are subjected to data splicing；
Spliced data are mapped in the switch data block.
3. the method that TDD system according to claim 2 synchronizes, which is characterized in that described to be cut from described by demapping
The step of obtaining the switching information is changed in data block to include the following steps：
The spliced data are parsed from the switch data block；
The logic level DATA is removed from the spliced data, obtains the base band data and the logic
Level data.
4. the method that TDD system according to claim 1 synchronizes, which is characterized in that described to map the switching information
Include the following steps to switch data step in the block：
Obtain the low level duration of the pulse sequence；
The superframe with the trip point time interval minimum of the high level of the pulse sequence is chosen out of described radio frames, wherein institute
The superframe for stating time interval minimum is in after the high level；
Preset time delay value and the low level duration and minimum time are subtracted using the predetermined period of the pulse sequence
Away from distance values summation, obtain fiducial time, wherein the minimum time away from for the high level and the time interval it is minimum
Superframe between time interval；
The superframe of the time interval minimum is written using the low level duration and the fiducial time as byte value
In two default control words, wherein the superframe of default control word and time interval minimum for the fiducial time to be written
Superframe header between time difference be the preset time delay value.
5. the method that TDD system according to claim 4 synchronizes, which is characterized in that described to be cut from described by demapping
The step of obtaining the switching information is changed in data block to include the following steps：
The byte value of each byte of the radio frames is detected successively, if detecting the non-zero byte of byte value, immediate record detects
Timing position in the radio frames of byte value and the non-zero byte time value；
According to the predetermined period of the time value and the pulse sequence of the byte value of record, record, restore the pulse sequence.
6. the method that TDD system according to claim 5 synchronizes, which is characterized in that the byte value according to record,
The predetermined period of the time value of record and the pulse sequence further includes following step after the step of restoring the pulse sequence
Suddenly：
The delay inequality for obtaining the process for restoring the pulse sequence carries out timing alignment to the pulse sequence.
7. the system that a kind of TDD system synchronizes, which is characterized in that including：
First acquisition module, the switching uplink downlink generated by synchronized algorithm for obtaining the proximal end unit in TDD system
Switching information；
Mapping block is sent to institute for the switching information to be mapped in switch data block, and by the switch data block
State the far-end unit in TDD system；
De-mapping module obtains the switching information for passing through demapping from the switch data block, in distal end list
The synchronism switching of uplink downlink is realized in member；
The switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is to be assisted based on CPRI
The radio frames of view；
The TDD system is time division duplex synchronous system, and the CPRI agreements are base band-radio frequency interface agreement.
8. the system that TDD system according to claim 7 synchronizes, which is characterized in that the switching information is the proximal end
Switch the logic level DATA of switch in unit, the mapping block be additionally operable to by the logic level DATA and base band data into
Row data are spliced, and spliced data are mapped in the switch data block.
9. the system that TDD system according to claim 8 synchronizes, which is characterized in that the De-mapping module is used for：
The spliced data are parsed from the switch data block；
The logic level DATA is removed from the spliced data, obtains the base band data and the logic
Level data.
10. the system that TDD system according to claim 7 synchronizes, which is characterized in that the mapping block is additionally operable to：
Obtain the low level duration of the pulse sequence；
The superframe with the trip point time interval minimum of the high level of the pulse sequence is chosen out of described radio frames, wherein institute
The superframe for stating time interval minimum is in after the high level；
Preset time delay value and the low level duration and minimum time are subtracted using the predetermined period of the pulse sequence
Away from distance values summation, obtain fiducial time, wherein the minimum time away from for the high level and the time interval it is minimum
Superframe between time interval；
The superframe of the time interval minimum is written using the low level duration and the fiducial time as byte value
In two default control words, wherein the superframe of default control word and time interval minimum for the fiducial time to be written
Superframe header between time difference be the preset time delay value.
11. the system that TDD system according to claim 10 synchronizes, which is characterized in that the De-mapping module is used for：
The byte value for detecting each byte of the radio frames successively, when detecting the non-zero byte of byte value, immediate record detection
To timing position in the radio frames of byte value and the non-zero byte time value；
According to the predetermined period of the time value and the pulse sequence of the byte value of record, record, restore the pulse sequence.
12. the system that TDD system according to claim 11 synchronizes, which is characterized in that further include correction module, for obtaining
The delay inequality for taking the process for restoring the pulse sequence carries out timing alignment to the pulse sequence.
13. a kind of method that TDD system synchronizes, which is characterized in that include the following steps：
The switch data block for being sent to the far-end unit in TDD system is obtained, the switch data block is mapped in the TDD system
Proximal end unit by synchronized algorithm generate switching uplink downlink switching information；
The switching information is obtained from the switch data block by demapping, uplink and downlink chain is realized in the far-end unit
The synchronism switching on road；
The switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is to be assisted based on CPRI
The radio frames of view；
The TDD system is time division duplex synchronous system, and the CPRI agreements are base band-radio frequency interface agreement.
14. the system that a kind of TDD system synchronizes, which is characterized in that including：
Second acquisition module, for obtaining the switch data block for being sent to the far-end unit in TDD system, the switch data block reflects
The switching information for the switching uplink downlink that the proximal end unit penetrated in TDD system is generated by synchronized algorithm；
De-mapping module obtains the switching information for passing through demapping from the switch data block, in distal end list
The synchronism switching of uplink downlink is realized in member；
The switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is to be assisted based on CPRI
The radio frames of view；
The TDD system is time division duplex synchronous system, and the CPRI agreements are base band-radio frequency interface agreement.
15. a kind of method that TDD system synchronizes, which is characterized in that include the following steps：
Obtain the switching information for the switching uplink downlink that the proximal end unit in TDD system is generated by synchronized algorithm；
The switching information is mapped in switch data block, and the switch data block is sent in the TDD system
Far-end unit；
The switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is to be assisted based on CPRI
The radio frames of view；
The TDD system is time division duplex synchronous system, and the CPRI agreements are base band-radio frequency interface agreement.
16. the system that a kind of TDD system synchronizes, which is characterized in that including：
First acquisition module, the switching uplink downlink generated by synchronized algorithm for obtaining the proximal end unit in TDD system
Switching information；
Mapping block is sent to institute for the switching information to be mapped in switch data block, and by the switch data block
State the far-end unit in TDD system；
The switching information is the pulse sequence for switching switch in the proximal end unit, and the switch data block is to be assisted based on CPRI
The radio frames of view；
The TDD system is time division duplex synchronous system, and the CPRI agreements are base band-radio frequency interface agreement.
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