CN104661299A - Synchronization method and system for TDD (Time Division Duplexing) system - Google Patents
Synchronization method and system for TDD (Time Division Duplexing) system Download PDFInfo
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Abstract
The invention discloses a synchronization method and system for a TDD (Time Division Duplexing) system. The method comprises the following steps: acquiring switching information for switching an uplink and a downlink generated by a near-end unit in the TDD system through a synchronization algorithm; mapping the switching information into a switching data block, and transmitting the switching data block to a remote unit in the TDD system; and acquiring the switching information from the switching data block through de-mapping, and implementing synchronous switching of the uplink and the downlink in the remote unit. Through implementation of the synchronization method and system for the TDD system disclosed by the invention, hardware such as a control logic and a filter circuit for generating synchronization signals in the remote unit can be removed while synchronous switching of the uplinks and downlinks of the remote unit and the near-end unit in the whole system is implemented accurately, and the cost is reduced.
Description
Technical field
The present invention relates to wireless communication technology field, particularly relate to the method and system that a kind of TDD system is synchronous.
Background technology
In wireless communication technology, TDD(Time Division Duplexing, time division duplex) synchronous communication system is as TD-SCDMA(Time Division-Synchronous Code Division Multiple Access, TD SDMA), TD-LTE(Time Division Long Term Evolution, timesharing Long Term Evolution) etc. need to design corresponding synchronized algorithm and produce up link and the diverter switch needed for down link, to realize the time-division multiplexing function of system.
In traditional repeater formula TDD synchronous communication system, whole communication system comprises multiple subsystem, each subsystem comprises a near-end unit and multiple far-end unit, wireless signal needs the amplification being realized signal by whole system, and namely the antenna opening of signal proximally unit prolongs life to the covering of the antenna opening of far-end unit.In the communication process of TDD system, the Logic control module of near-end unit proposes signal characteristic, produces the synchro switch for controlling up link and downlink operation situation through specific algorithm.In the data traffic transmission period of down link, down link is communicated with by the switch control logic produced, now up link disconnects, the antenna opening of signal proximally unit flows to the antenna opening of far-end unit, otherwise in the data traffic transmission period of up link, the antenna opening of signal distally unit flows to the antenna opening of near-end unit.
In traditional method, in order to realize above-mentioned communication process, near-end unit and far-end unit need to extract signal characteristic independently, realize synchronous and produce corresponding synchro switch, but this mode along with extra hardware spending and logical resource expense, significantly increases the complexity of hardware cost and realization usually.
Summary of the invention
Based on this, be necessary in tdd communication systems, the problem that when realizing synchronized algorithm, hardware cost is high, implementation procedure complexity is high, provides the method and system that a kind of TDD system is synchronous.
The method that TDD system is synchronous, comprises the following steps:
Obtain the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm;
Described switching information is mapped in switch data block, and by the far-end unit in described switch data block movement to described TDD system;
From described switch data block, obtain described switching information by demapping, in described far-end unit, realize the synchronism switching of uplink downlink.
The system that TDD system is synchronous, comprising:
First acquisition module, the switching information of the switching uplink downlink that the near-end unit for obtaining in TDD system is generated by synchronized algorithm;
Mapping block, for being mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system;
De-mapping module, for obtaining described switching information by demapping from described switch data block, realizes the synchronism switching of uplink downlink in described far-end unit.
The method and system that above-mentioned TDD system is synchronous, be mapped in switch data block by the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm, be sent to far-end unit side, and recover described switching information by the mode of demapping, can realize switching with the uplink downlink of near-end units synchronization in each far-end unit of accurately TDD system.Switching information is all from near-end unit, improve synchronous consistency, and without the need to setting up the synchronized algorithm and the related hardware such as switch formation logic, inspection filter circuit that generate described switching information in far-end unit, significantly reduce the manufacturing cost of system and the complexity of simultaneous operation.
The method that TDD system is synchronous, comprises the following steps:
Obtain the switch data block of the far-end unit mail in TDD system, described switch data block is mapped with the switching information of the switching uplink downlink that the near-end unit in described TDD system is generated by synchronized algorithm;
From described switch data block, obtain described switching information by demapping, in described far-end unit, realize the synchronism switching of uplink downlink.
The system that TDD system is synchronous, comprising:
Second acquisition module, for obtaining the switch data block of the far-end unit mail in TDD system, described switch data block is mapped with the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm;
De-mapping module, for obtaining described switching information by demapping from described switch data block, realizes the synchronism switching of uplink downlink in described far-end unit.
The method and system that above-mentioned TDD system is synchronous, mode in far-end side by demapping recovers described switching information from the switch data block from near-end unit side, can realize switching with the uplink downlink of near-end units synchronization in each far-end unit of TDD system.Switching information, all from near-end unit, therefore improves synchronous consistency, and without the need to setting up the related hardware generating described switching information in far-end unit, reduces the manufacturing cost of system and the complexity of simultaneous operation.
The method that TDD system is synchronous, comprises the following steps:
Obtain the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm;
Described switching information is mapped in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
The system that TDD system is synchronous, comprising:
First acquisition module, the switching information of the switching uplink downlink that the near-end unit for obtaining in TDD system is generated by synchronized algorithm;
Mapping block, for being mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
The method and system that above-mentioned TDD system is synchronous, be mapped in described switch data block in near-end unit side by the described switching information that end unit generates nearly, and pass toward far-end unit side, provide this source signal of described switching information for realizing switching with the uplink downlink of near-end units synchronization in each far-end unit of TDD system.Switching information, all from near-end unit, improves synchronous consistency, and without the need to setting up the related hardware generating described switching information in far-end unit, reduces the manufacturing cost of system.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of synchronous method first execution mode of TDD system of the present invention;
Fig. 2 is the schematic flow sheet of synchronous method second execution mode of TDD system of the present invention;
Fig. 3 is the schematic flow sheet of synchronous method the 3rd execution mode of TDD system of the present invention;
Fig. 4 is the structural representation of synchronous system first execution mode of TDD system of the present invention;
Fig. 5 is the structural representation of synchronous system the 3rd execution mode of TDD system of the present invention;
Fig. 6 is the schematic diagram of the synchronous method of TDD system of the present invention in the operating process of far-end unit side;
Fig. 7 is the synchronous structural representation of system in far-end unit side of TDD system of the present invention;
Fig. 8 is the schematic diagram of the synchronous method of TDD system of the present invention in the operating process of near-end unit side;
Fig. 9 is the synchronous structural representation of system in near-end unit side of TDD system of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in detail.
Refer to Fig. 1, Fig. 1 is the schematic flow sheet of synchronous method first execution mode of TDD system of the present invention.
The method that the described TDD system of present embodiment is synchronous comprises the following steps:
Step 101, obtains the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm.
Step 102, is mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
Step 103, obtains described switching information by demapping, realizes the synchronism switching of uplink downlink in described far-end unit from described switch data block.
Be mapped in switch data block to be transmitted the far-end unit be sent in TDD system by the switching information of the switching uplink downlink generated by synchronized algorithm by the near-end unit be derived from TDD system, can avoid occurring in traditional approach because the inconsistency of detection module parameter or circuit parameter causes the situation of the inconsistency of the indexs such as whole TDD system synchronous dynamic scope.
By the switch data block being mapped with switching information received is carried out the demapping corresponding to mapping mode, recover switching information, and then synchronism switching uplink downlink is realized in each far-end unit, synchronized algorithm in removable each far-end unit and switch formation logic and various related hardware, special in analog machine, only need by light path, switch to be recovered, do not need extra control logic and circuit overhead completely, the intrinsic cost of whole system is declined.
For step 101, described switching information can be preferably for switching the logic level DATA of the diverter switch of uplink downlink in the near-end unit calculated by synchronized algorithm and switching logic, use numeral 0 to represent that switch is in low-level logic, use numeral 1 to represent that switch is in high level logic.Described switching information also can be for switching the pulse sequence of the diverter switch of uplink downlink in near-end unit, and the pulse sequence in each cycle is made up of low duration and high level lasting time.Described switching information can also be that other are usual for representing in near-end unit for switching the information of the diverter switch of uplink downlink in this area.
For step 102, the mode of mapping comprises and directly switching information is write described switch data block, the signature identification of switching information is write switch data block at least in part or switching information carries out corresponding with the information data in switch data block by the technological means usual according to this area.
Described switch data block can be preferably based on the data flow of various base band-radio frequency interface agreement, Frame or packet, can also be usual other data modes in this area.Described base band-radio frequency interface agreement comprises CPRI (The Common Public Radio Interface) agreement, OBSAI(Open Base StationArchitecture Initiative) agreement and TDRI agreement (baseband extension agreement) etc.
The mode transmitting described switch data block comprises other usual circulation ways of transparent transmission, broadcast type transmission or this area.
In one embodiment, described switching information is the logic level DATA of diverter switch in described near-end unit, wherein, described logic level DATA can be mapped in described switch data block, described the step that described switching information is mapped in switch data block be comprised the following steps:
Step 1021, carries out data splicing by described logic level DATA and described base band data.
Step 1022, by spliced data-mapping in described switch data block.
In step 1021, need the base-band data stream N bit carrying out transmitting, for N=3, the low level moment is with base-band data stream (000,010,111,101) be example, after the low level of above-mentioned data flow and diverter switch is carried out data splicing, become (0000,0100,1110,1010).Be (111,101,001,110) in the base-band data stream in the high level moment of switch, become after carrying out data splicing (1111,1011,0011,1101), spliced base band data becomes the data flow of N+1 bit.When carrying out data splicing in this step, the logical data of diverter switch to be inserted the rearmost position at base band data, also described logical data can be inserted other positions in base-band data stream in the present embodiment.
In step 1022, by spliced for data data flow through forming the switch data block containing switching information based on the mapping of a certain base band-radio frequency protocol.
Operation in above-described embodiment, only need to be spliced by data and form the switch data block containing switching information based on the mapping of a certain base band-radio frequency protocol, described data block can be sent to far-end unit, at far-end unit to carrying out data stripping and demapping can recover switching information, without the need to carrying out the complicated synchro switch generative process such as synchronized algorithm, filtering at far-end unit, therefore can greatly be reduced at the process realizing synchronism switching uplink downlink in each far-end unit.
In another embodiment, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, wherein, described pulse sequence can be mapped in the described radio frames based on CPRI agreement, described the step that described switching information is mapped in switch data block be comprised the following steps:
Step 1023, obtains at least one in these three time sequence informations of the pulse period of the pulse sequence of described diverter switch, high level lasting time and low duration.In this step, during pulse period constant maintenance predetermined value, only need to obtain high level lasting time or low duration; During pulse period change at random, two in three time sequence informations need be obtained.
Step 1024, from the radio frames based on CPRI agreement, chooses at least two for mapping the superframe of described pulse sequence.In this step, during pulse period constant maintenance predetermined value, two superframes are chosen; During pulse period change at random, choose three superframes.
Step 1025, according to high level or the low level trip point (switching over moment) of the first superframe at least two superframes chosen and described pulse sequence, obtains the fiducial time of the time location for the trip point identifying described pulse sequence.In this step, by the pulse sequence of the sequential and described diverter switch of analyzing the first superframe (can be any one in the superframe chosen), calculate the time value of described fiducial time according to the concrete trip point (starting point of high level or low level starting point) of mark.
Step 1026, using described fiducial time as in any one control word territory of described first superframe of byte value write, at least one in three time sequence informations obtained is write in any control word territory of other superframes at least two superframes chosen except described first superframe as byte value.A corresponding time value of superframe.
Operation in above-described embodiment, by the information of the time sequence information of described pulse sequence and the time location of trip point correspondence being inserted the mode in the control word of radio frames, switching information is mapped in switch data block, both do not consumed base band data and had dedicated bandwidth, the recovery of switching information can have been realized again at far-end unit.
For step 103, the mapping process in corresponding step 102 carries out demapping.
In one embodiment, described switching information is the logic level DATA of diverter switch in described near-end unit, and the described step obtaining described switching information by demapping from described switch data block comprises the following steps:
Described spliced data are parsed from described switch data block;
Described logic level DATA is peeled off from described spliced data, obtains described base band data and described logic level DATA.
The process that the process of information stripping (separating splicing) in above-mentioned steps and data are spliced is completely the same.As separated the data flow before splicing be: (1111,1011,0011,1101), then separating spliced base-band data stream is (111,101,001,110), high level logic is (1,1,1,1), preferably, by the mode of the demapping based on a certain base band-radio frequency protocol (consistent with mapping process), described spliced data flow is parsed from described switch data block.
In another embodiment, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, wherein, described pulse sequence can be gone out based on demapping the radio frames of CPRI agreement described in receiving, the described step obtaining described switching information by demapping from described switch data block comprises the following steps:
Detect the byte value of each byte of described radio frames successively, if the byte that byte value is non-zero detected, the time value of the byte value that immediate record detects and the timing position of described non-zero byte in the described radio frames trip point of pulse sequence of the corresponding described diverter switch of non-zero byte of place (fiducial time).
According to the pulse period of the byte value recorded, the time value of record and/or the pulse sequence of predetermined described diverter switch, recover described pulse sequence.
An above-mentioned radio frames based on CPRI agreement comprises 150 superframes (Hyper Frame), and each superframe comprises 256 base frames (Basic Frame), and base frame is the elementary cell transmitted by CPRI.The length of a base frame equals the length of a chip (chip) of wireless signal, and the transmission cycle of each base frame is 1/3.84MHz.Wherein, each CPRI base frame comprises 16 words, in 16 words, comprise 1 control word (Control Word) and for carrying inphase quadrature (IQ, In-phase Quardrature) 15 words of data, control word is for carrying the self-defining control word information of control data and each manufacturer except I/Q data.
In other embodiments, those skilled in the art can also record the byte information of described fiducial time and the control word residing for described time sequence information in advance, obtain in the step of described switching information by demapping described from described switch data block, directly detect according to the byte information of record the byte that byte value is non-zero,, and then recover described time sequential pulse.
Refer to Fig. 2, Fig. 2 is the schematic flow sheet of synchronous method second execution mode of TDD system of the present invention.
The main distinction of the method that the described TDD system of present embodiment is synchronous and described first execution mode is, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, describedly the step that described switching information is mapped in switch data block is specifically comprised the following steps:
Step 201, obtains the low level duration of described pulse sequence.
Step 202, chooses the superframe minimum with the trip point time interval of the high level of described pulse sequence in described radio frames, wherein, after the minimum superframe of described time interval is in described high level.
Step 203, the predetermined period of described pulse sequence is used to deduct the summation of the distance values of preset time delay value and described low level duration and minimum time distance, obtain fiducial time, wherein, described minimum time is apart from being time interval between the minimum superframe of described high level and described time interval.
Step 204, described low level duration and described fiducial time are write in two default control words of the minimum superframe of described time interval as byte value, wherein, for the minimum superframe of the default control word and described time interval that write described fiducial time superframe header between time difference be described preset time delay value.
Operating process in above-mentioned execution mode is only a specific embodiment of the present invention, is not used in and limits other execution modes.The pulse sequence of described diverter switch is mapped in described radio frames by other conventional techniques means of this area by the present invention.
Refer to Fig. 3, Fig. 3 is the schematic flow sheet of synchronous method the 3rd execution mode of TDD system of the present invention.
The main distinction of the method that the described TDD system of present embodiment is synchronous and described first execution mode is, at the byte value according to record, the time value of record and the predetermined period of described pulse sequence, after recovering described pulse sequence, further comprising the steps:
Step 301, obtains the delay inequality of the process recovering described pulse sequence, carries out timing alignment to described pulse sequence.
The systematic error existed aforesaid operations is by carrying out switching information and recovering in obtaining step 103 time, and then correct the pulse sequence recovered, greatly can improve the accuracy of the pulse sequence of recovery, improve the consistency of far-end unit and near-end units synchronization.
Refer to Fig. 4, Fig. 1 is the structural representation of synchronous system first execution mode of TDD system of the present invention.
The system that the described TDD system of present embodiment is synchronous comprises the first acquisition module 110, mapping block 120 and De-mapping module 130, wherein:
First acquisition module 110, the switching information of the switching uplink downlink that the near-end unit for obtaining in TDD system is generated by synchronized algorithm.
Mapping block 120, for being mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
De-mapping module 130, for obtaining described switching information by demapping from described switch data block, realizes the synchronism switching of uplink downlink in described far-end unit.
Be mapped in switch data block to be transmitted the far-end unit be sent in TDD system by the switching information of the switching uplink downlink generated by synchronized algorithm by the near-end unit be derived from TDD system, can avoid occurring in traditional approach because the inconsistency of detection module parameter or circuit parameter causes the situation of the inconsistency of the indexs such as whole TDD system synchronous dynamic scope.
By the switch data block being mapped with switching information received is carried out the demapping corresponding to mapping mode, recover switching information, and then synchronism switching uplink downlink is realized in each far-end unit, synchronized algorithm in removable each far-end unit and switch formation logic and various related hardware, special in analog machine, only need by light path, switch to be recovered, do not need extra control logic and circuit overhead completely, the intrinsic cost of whole system is declined.
For the first acquisition module 110, described switching information can be preferably for switching the logic level DATA of the diverter switch of uplink downlink in the near-end unit calculated by synchronized algorithm and switching logic, use numeral 0 to represent that switch is in low-level logic, use numeral 1 to represent that switch is in high level logic.Described switching information also can be for switching the pulse sequence of the diverter switch of uplink downlink in near-end unit, and the pulse sequence in each cycle is made up of low duration and high level lasting time.Described switching information can also be that other are usual for representing in near-end unit for switching the information of the diverter switch of uplink downlink in this area.
For mapping block 120, the mode of mapping comprises and directly switching information is write described switch data block, the signature identification of switching information is write switch data block at least in part or switching information carries out corresponding with the information data in switch data block by the technological means usual according to this area.
Described switch data block can be preferably based on the data flow of various base band-radio frequency interface agreement, Frame or packet, can also be usual other data modes in this area.Described base band-radio frequency interface agreement comprises CPRI (The Common Public Radio Interface) agreement, OBSAI(Open Base StationArchitecture Initiative) agreement and TDRI agreement (baseband extension agreement) etc.
The mode transmitting described switch data block comprises other usual circulation ways of transparent transmission, broadcast type transmission or this area.
In one embodiment, described switching information is the logic level DATA of diverter switch in described near-end unit, wherein, described logic level DATA can be mapped in described switch data block, described mapping block 120 for described logic level DATA and described base band data being carried out data splicing, by spliced data-mapping in described switch data block.
In a tdd system, when the base-band data stream that needs carry out transmitting is N bit, for N=3, the low level moment is with base-band data stream (000,010,111,101) be example, the low level of above-mentioned data flow and diverter switch can be carried out data splicing by mapping block 120, after carrying out data splicing, data flow becomes (0000,0100,1110,1010).Be (111,101,001,110) in the base-band data stream in the high level moment of switch, become after carrying out data splicing (1111,1011,0011,1101), spliced base band data becomes the data flow of N+1 bit.When mapping block 120 carries out data splicing, the logical data of diverter switch to be inserted the rearmost position at base band data, also described logical data can be inserted other positions in base-band data stream in the present embodiment.
Spliced for data data flow is also formed through the mapping based on a certain base band-radio frequency protocol the switch data block containing switching information by mapping block 120 in the present embodiment.
Operation in above-described embodiment, only need to be spliced by data and form the switch data block containing switching information based on the mapping of a certain base band-radio frequency protocol, described data block can be sent to far-end unit, at far-end unit to carrying out data stripping and demapping can recover switching information, without the need to carrying out the complicated synchro switch generative process such as synchronized algorithm, filtering at far-end unit, therefore can greatly be reduced at the process realizing synchronism switching uplink downlink in each far-end unit.
In another embodiment, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, wherein, described pulse sequence can be mapped in the described radio frames based on CPRI agreement by mapping block 120, and described mapping block 120 is for performing following operation:
Obtain at least one in these three time sequence informations of the pulse period of the pulse sequence of described diverter switch, high level lasting time and low duration.In this step, during pulse period constant maintenance predetermined value, only need to obtain high level lasting time or low duration; During pulse period change at random, two in three time sequence informations need be obtained.
From the radio frames based on CPRI agreement, choose at least two for mapping the superframe of described pulse sequence.In this step, during pulse period constant maintenance predetermined value, two superframes are chosen; During pulse period change at random, choose three superframes.
According to high level or the low level trip point (switching over moment) of the first superframe at least two superframes chosen and described pulse sequence, obtain the fiducial time of the time location for the trip point identifying described pulse sequence.In this step, by the pulse sequence of the sequential and described diverter switch of analyzing the first superframe (can be any one in the superframe chosen), calculate the time value of described fiducial time according to the concrete trip point (starting point of high level or low level starting point) of mark.
Using described fiducial time as in any one control word territory of described first superframe of byte value write, at least one in three time sequence informations obtained is write in any control word territory of other superframes at least two superframes chosen except described first superframe as byte value.A corresponding time value of superframe.
Operation in above-described embodiment, by the information of the time sequence information of described pulse sequence and the time location of trip point correspondence being inserted the mode in the control word of radio frames, switching information is mapped in switch data block, both do not consumed base band data and had dedicated bandwidth, the recovery of switching information can have been realized again at far-end unit.
For De-mapping module 130, the mapping process in correspondence mappings module 120 carries out demapping.
In one embodiment, described switching information is the logic level DATA of diverter switch in described near-end unit, described De-mapping module 130 for parsing described spliced data from described switch data block, described logic level DATA is peeled off from described spliced data, obtains described base band data and described logic level DATA.
The process that the process of information stripping (separate splicing) and mapping block 120 data splice is carried out completely the same at above-mentioned De-mapping module 130.As separated the data flow before splicing be: (1111,1011,0011,1101), then separating spliced base-band data stream is (111,101,001,110), high level logic is (1,1,1,1), preferably, by the mode of the demapping based on a certain base band-radio frequency protocol (consistent with mapping process), described spliced data flow is parsed from described switch data block.
In another embodiment, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, wherein, De-mapping module 130 described pulse sequence can be mapped from described in receiving based on demapping the radio frames of CPRI agreement, described De-mapping module 130 is for performing following operation:
Detect the byte value of each byte of described radio frames successively, if the byte that byte value is non-zero detected, the time value of the byte value that immediate record detects and the timing position of described non-zero byte in the described radio frames trip point of pulse sequence of the corresponding described diverter switch of non-zero byte of place (fiducial time).
According to the pulse period of the byte value recorded, the time value of record and/or the pulse sequence of predetermined described diverter switch, recover described pulse sequence.
An above-mentioned radio frames based on CPRI agreement comprises 150 superframes (Hyper Frame), and each superframe comprises 256 base frames (Basic Frame), and base frame is the elementary cell transmitted by CPRI.The length of a base frame equals the length of a chip (chip) of wireless signal, and the transmission cycle of each base frame is 1/3.84MHz.Wherein, each CPRI base frame comprises 16 words, in 16 words, comprise 1 control word (Control Word) and for carrying inphase quadrature (IQ, In-phase Quardrature) 15 words of data, control word is for carrying the self-defining control word information of control data and each manufacturer except I/Q data.
In other embodiments, those skilled in the art can also record the byte information of described fiducial time and the control word residing for described time sequence information in advance, when obtaining described switching information by demapping from described switch data block, directly detect according to the byte information of record the byte that byte value is non-zero,, and then recover described time sequential pulse.
It is below the second execution mode of the synchronous system of TDD system of the present invention.
The main distinction of the system that the described TDD system of second embodiment of the invention is synchronous and described first execution mode is, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, and described mapping block 120 specifically performs following operation:
Obtain the low level duration of described pulse sequence.
The superframe minimum with the trip point time interval of the high level of described pulse sequence is chosen, wherein, after the minimum superframe of described time interval is in described high level in described radio frames.
The predetermined period of described pulse sequence is used to deduct the summation of the distance values of preset time delay value and described low level duration and minimum time distance, obtain fiducial time, wherein, described minimum time is apart from being time interval between the minimum superframe of described high level and described time interval.
Described low level duration and described fiducial time are write in two default control words of the minimum superframe of described time interval as byte value, wherein, for the minimum superframe of the default control word and described time interval that write described fiducial time superframe header between time difference be described preset time delay value.
Operating process in above-mentioned execution mode is only a specific embodiment of the present invention, is not used in and limits other execution modes.The pulse sequence of described diverter switch is mapped in described radio frames by other conventional techniques means of this area by the present invention.
Refer to Fig. 5, Fig. 5 is the structural representation of synchronous system the 3rd execution mode of TDD system of the present invention.
The main distinction of the system that the described TDD system of present embodiment is synchronous and described first execution mode is, comprise correction module 140 further, described correction module 140, for obtaining the delay inequality of the process recovering described pulse sequence, carries out timing alignment to described pulse sequence.
The systematic error that aforesaid operations is undertaken existing when switching information recovers by obtaining De-mapping module 130, and then correct the pulse sequence recovered, greatly can improve the accuracy of the pulse sequence of recovery, improve the consistency of far-end unit and near-end units synchronization.
Refer to Fig. 6, Fig. 6 be the synchronous method of TDD system of the present invention at the schematic diagram of the operating process of far-end unit side, comprise the following steps:
Step 601, obtain the switch data block of the far-end unit mail in TDD system, described switch data block is mapped with the switching information of the switching uplink downlink that the near-end unit in described TDD system is generated by synchronized algorithm.
Step 602, obtains described switching information by demapping, realizes the synchronism switching of uplink downlink in described far-end unit from described switch data block.
Above-mentioned steps 601 correspondence obtains the switch data block sent in the step 102 described in Fig. 1, and above-mentioned steps 602 is identical with the step 103 described in Fig. 1.The execution mode of the method that the described TDD system that its enforceable execution mode is corresponding with Fig. 1 is synchronous is consistent.
Aforesaid operations step is by carrying out the demapping corresponding to mapping mode by the switch data block being mapped with switching information received, recover switching information, and then synchronism switching uplink downlink is realized in each far-end unit, synchronized algorithm in removable each far-end unit and switch formation logic and various related hardware, special in analog machine, only need by light path, switch to be recovered, do not need extra control logic and circuit overhead completely, the intrinsic cost of whole system is declined.
Refer to Fig. 7, Fig. 7 is the synchronous structural representation of system in far-end unit side of TDD system of the present invention, and the synchronous system of described TDD system comprises the second acquisition module 150 and De-mapping module 130, wherein:
Second acquisition module 150, for obtaining the switch data block of the far-end unit mail in TDD system, described switch data block is mapped with the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm.
De-mapping module 130, for obtaining described switching information by demapping from described switch data block, realizes the synchronism switching of uplink downlink in described far-end unit.
The switch data block that above-mentioned second acquisition module 150 sends for the mapping block 120 obtained described in Fig. 4, above-mentioned De-mapping module 130 is identical with the De-mapping module 130 described in Fig. 1.
By the switch data block being mapped with switching information received is carried out the demapping corresponding to mapping mode, recover switching information, and then synchronism switching uplink downlink is realized in each far-end unit, synchronized algorithm in removable each far-end unit and switch formation logic and various related hardware, special in analog machine, only need by light path, switch to be recovered, do not need extra control logic and circuit overhead completely, the intrinsic cost of whole system is declined.
Refer to Fig. 8, Fig. 8 is the schematic diagram of the synchronous method of TDD system of the present invention in the operating process of near-end unit side, and the synchronous system of described TDD system comprises the following steps:
Step 801, obtains the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm.
Step 802, is mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
Above-mentioned steps 801 is identical with the step 101 described in Fig. 1, and for sending the switch data block that step 601 described in Fig. 6 obtains, above-mentioned steps 802 is identical with the step 102 described in Fig. 1.The execution mode of the method that the described TDD system that its enforceable execution mode is corresponding with Fig. 1 is synchronous is consistent.Be mapped in switch data block to be transmitted the far-end unit be sent in TDD system by the switching information of the switching uplink downlink generated by synchronized algorithm by the near-end unit be derived from TDD system, can avoid occurring in traditional approach because the inconsistency of detection module parameter or circuit parameter causes the situation of the inconsistency of the indexs such as whole TDD system synchronous dynamic scope.
Refer to Fig. 9, Fig. 9 is the synchronous structural representation of system in near-end unit side of TDD system of the present invention, and the synchronous system of described TDD system comprises the first acquisition module 110 and mapping block 120, wherein:
First acquisition module 110, the switching information of the switching uplink downlink that the near-end unit for obtaining in TDD system is generated by synchronized algorithm.
Mapping block 120, for being mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
Above-mentioned first acquisition module 110 is identical for the first acquisition module 110 received described in Fig. 4, and above-mentioned mapping block 120 is identical with the mapping block 120 described in Fig. 1, the switch data block that the second acquisition module 150 for sending in Fig. 7 obtains.
Be mapped in switch data block to be transmitted the far-end unit be sent in TDD system by the switching information of the switching uplink downlink generated by synchronized algorithm by the near-end unit be derived from TDD system, can avoid occurring in traditional approach because the inconsistency of detection module parameter or circuit parameter causes the situation of the inconsistency of the indexs such as whole TDD system synchronous dynamic scope.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (16)
1. the method that TDD system is synchronous, is characterized in that, comprises the following steps:
Obtain the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm;
Described switching information is mapped in switch data block, and by the far-end unit in described switch data block movement to described TDD system;
From described switch data block, obtain described switching information by demapping, in described far-end unit, realize the synchronism switching of uplink downlink.
2. the method that TDD system according to claim 1 is synchronous, is characterized in that, described switching information is the logic level DATA of diverter switch in described near-end unit, describedly the step that described switching information is mapped in switch data block is comprised the following steps:
Described logic level DATA and described base band data are carried out data splicing;
By spliced data-mapping in described switch data block.
3. the method that TDD system according to claim 2 is synchronous, is characterized in that, the described step obtaining described switching information by demapping from described switch data block comprises the following steps:
Described spliced data are parsed from described switch data block;
Described logic level DATA is peeled off from described spliced data, obtains described base band data and described logic level DATA.
4. the method that TDD system according to claim 1 is synchronous, it is characterized in that, described switching information is the pulse sequence of diverter switch in described near-end unit, described switch data block is the radio frames based on CPRI agreement, describedly the step that described switching information is mapped in switch data block is comprised the following steps:
Obtain the low level duration of described pulse sequence;
The superframe minimum with the trip point time interval of the high level of described pulse sequence is chosen, wherein, after the minimum superframe of described time interval is in described high level in described radio frames;
The predetermined period of described pulse sequence is used to deduct the summation of the distance values of preset time delay value and described low level duration and minimum time distance, obtain fiducial time, wherein, described minimum time is apart from being time interval between the minimum superframe of described high level and described time interval;
Described low level duration and described fiducial time are write in two default control words of the minimum superframe of described time interval as byte value, wherein, for the minimum superframe of the default control word and described time interval that write described fiducial time superframe header between time difference be described preset time delay value.
5. the method that TDD system according to claim 4 is synchronous, is characterized in that, the described step obtaining described switching information by demapping from described switch data block comprises the following steps:
Detect the byte value of each byte of described radio frames successively, if the byte that byte value is non-zero detected, the time value of the byte value that immediate record detects and the timing position of described non-zero byte in described radio frames;
According to the byte value recorded, the time value of record and the predetermined period of described pulse sequence, recover described pulse sequence.
6. the method that TDD system according to claim 5 is synchronous, is characterized in that, at the described byte value according to record, the time value of record and the predetermined period of described pulse sequence, after recovering the step of described pulse sequence, further comprising the steps of:
Obtain the delay inequality of the process recovering described pulse sequence, timing alignment is carried out to described pulse sequence.
7. the system that TDD system is synchronous, is characterized in that, comprising:
First acquisition module, the switching information of the switching uplink downlink that the near-end unit for obtaining in TDD system is generated by synchronized algorithm;
Mapping block, for being mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system;
De-mapping module, for obtaining described switching information by demapping from described switch data block, realizes the synchronism switching of uplink downlink in described far-end unit.
8. the system that TDD system according to claim 7 is synchronous, it is characterized in that, described switching information is the logic level DATA of diverter switch in described near-end unit, described mapping block also for described logic level DATA and described base band data are carried out data splicing, and by spliced data-mapping in described switch data block.
9. the method that TDD system according to claim 8 is synchronous, is characterized in that, described De-mapping module is used for:
Described spliced data are parsed from described switch data block;
Described logic level DATA is peeled off from described spliced data, obtains described base band data and described logic level DATA.
10. the system that TDD system according to claim 7 is synchronous, is characterized in that, described switching information is the pulse sequence of diverter switch in described near-end unit, and described switch data block is the radio frames based on CPRI agreement, described mapping block also for:
Obtain the low level duration of described pulse sequence;
The superframe minimum with the trip point time interval of the high level of described pulse sequence is chosen, wherein, after the minimum superframe of described time interval is in described high level in described radio frames;
The predetermined period of described pulse sequence is used to deduct the summation of the distance values of preset time delay value and described low level duration and minimum time distance, obtain fiducial time, wherein, described minimum time is apart from being time interval between the minimum superframe of described high level and described time interval;
Described low level duration and described fiducial time are write in two default control words of the minimum superframe of described time interval as byte value, wherein, for the minimum superframe of the default control word and described time interval that write described fiducial time superframe header between time difference be described preset time delay value.
The system that 11. TDD system according to claim 10 are synchronous, it is characterized in that, described De-mapping module is used for:
Detect the byte value of each byte of described radio frames successively, when the non-zero byte of byte value being detected, the time value of the byte value that immediate record detects and the timing position of described non-zero byte in described radio frames;
According to the byte value recorded, the time value of record and the predetermined period of described pulse sequence, recover described pulse sequence.
The system that 12. TDD system according to claim 11 are synchronous, is characterized in that, also comprise correction module, for obtaining the delay inequality of the process recovering described pulse sequence, carries out timing alignment to described pulse sequence.
The method that 13. 1 kinds of TDD system are synchronous, is characterized in that, comprise the following steps:
Obtain the switch data block of the far-end unit mail in TDD system, described switch data block is mapped with the switching information of the switching uplink downlink that the near-end unit in described TDD system is generated by synchronized algorithm;
From described switch data block, obtain described switching information by demapping, in described far-end unit, realize the synchronism switching of uplink downlink.
The system that 14. 1 kinds of TDD system are synchronous, is characterized in that, comprising:
Second acquisition module, for obtaining the switch data block of the far-end unit mail in TDD system, described switch data block is mapped with the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm;
De-mapping module, for obtaining described switching information by demapping from described switch data block, realizes the synchronism switching of uplink downlink in described far-end unit.
The method that 15. 1 kinds of TDD system are synchronous, is characterized in that, comprise the following steps:
Obtain the switching information of the switching uplink downlink that the near-end unit in TDD system is generated by synchronized algorithm;
Described switching information is mapped in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
The system that 16. 1 kinds of TDD system are synchronous, is characterized in that, comprising:
First acquisition module, the switching information of the switching uplink downlink that the near-end unit for obtaining in TDD system is generated by synchronized algorithm;
Mapping block, for being mapped to described switching information in switch data block, and by the far-end unit in described switch data block movement to described TDD system.
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