CN104614908A - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN104614908A CN104614908A CN201510054837.9A CN201510054837A CN104614908A CN 104614908 A CN104614908 A CN 104614908A CN 201510054837 A CN201510054837 A CN 201510054837A CN 104614908 A CN104614908 A CN 104614908A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
- G02F1/13392—Gaskets; Spacers; Sealing of cells spacers dispersed on the cell substrate, e.g. spherical particles, microfibres
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses an array substrate. The array substrate comprises a substrate body, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a pixel electrode layer, wherein the first metal layer, the first insulating layer, the second metal layer, the second insulating layer and the pixel electrode layer are sequentially arranged on the surface of the substrate body. The pixel electrode layer comprises a pixel electrode and a public electrode. A protrusion is arranged on the second insulating layer, located between the pixel electrode and the public electrode and used for isolating the pixel electrode from the public electrode. The problem that due to influences of particles, a short circuit is caused is effectively solved, and the product quality is improved.
Description
[technical field]
The present invention relates to display technique field, particularly a kind of array base palte and display panels.
[background technology]
At TFT-LCD (Thin Film Transistor Liquid Crystal Display, ultrathin membrane transistor liquid crystal display (TFT-LCD)) in industry, pixel can be used the electric capacity formed between different metal and shows to maintain pixel and prevent colour cast, in time using same layer metal to make electric capacity, because same layer metal is not gone up at same layer, therefore, be easy to be subject to the impact of particle (particle) and cause the generation of short circuit.
Referring to Fig. 1, is the structural representation of the array base palte that prior art provides.Described array base palte comprises a substrate 10, and the first metal layer 20, first insulation course 30, second metal level 40, second insulation course 50 be set in turn on described substrate 10 surface and pixel electrode layer 60, wherein, pixel electrode in pixel electrode layer 60 and the common electrode on relative substrate are as pixel capacitance, and the concentric line on the public electrode in pixel electrode layer 60 and described the first metal layer 20 or described second metal level 40 is as memory capacitance.Pixel electrode layer 60 is made up of ITO (Indium Tin Oxide, tin-doped indium oxide).Known, ITO has the effect of pixel capacitance and memory capacitance, time to form the object of electric capacity be to show, inconsistent by the electric charge distribution of main pixel (main pixel) and sub-pixel (sub pixel), thus play the effect of low colour cast.But this design is because ITO is positioned at same layer, between described pixel electrode in described pixel electrode layer 60 and described public electrode, there is gap, therefore particle is easy to fall in gap, thus cause electric capacity ITO together with pixel ITO short circuit, thus cause electric capacity to lose effect, finally cause display to occur abnormal, reduce the quality of product.
Therefore, be necessary to propose a kind of new technical scheme, to solve the problems of the technologies described above.
[summary of the invention]
The object of the present invention is to provide a kind of array base palte and display panels, it effectively can avoid the problem causing due to the impact of particle being short-circuited, and improves the quality of product.
For solving the problem, technical scheme of the present invention is as follows:
A kind of array base palte, described array base palte comprises:
One substrate;
One the first metal layer, described the first metal layer is arranged on described substrate surface; Described the first metal layer comprises grid and the sweep trace of thin film transistor (TFT);
One first insulation course, described first insulation course is arranged on described the first metal layer, for isolating described the first metal layer and the second metal level;
Second metal level described in one, described second metal level is arranged on described first insulation course; Described second metal level comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line;
One second insulation course, described second insulation course is arranged on described second metal level, for isolating described second metal level and pixel electrode layer;
One is protruding, and described projection is arranged on described second insulation course;
Pixel electrode layer described in one, described pixel electrode layer is arranged on described second insulation course; Described pixel electrode layer comprises pixel electrode and public electrode;
Wherein, described projection is between described pixel electrode and described public electrode, and described projection is for isolating described pixel electrode and public electrode.
Preferably, in described array base palte, the thickness of described second insulation course at corresponding described raised position place is greater than the thickness of described second insulation course of non-protruding position.
Preferably, in described array base palte, the thickness of described second metal level at corresponding described raised position place is greater than the thickness of described second metal level of non-protruding position.
Preferably, in described array base palte, described the first metal layer also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described the first metal layer is as memory capacitance.
Preferably, in described array base palte, described second metal level also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described second metal level is as memory capacitance.
A kind of display panels, the liquid crystal cell comprising array base palte, color membrane substrates and be arranged between described array base palte and color membrane substrates; Wherein,
Described array base palte comprises:
One substrate;
One the first metal layer, described the first metal layer is arranged on described substrate surface; Described the first metal layer comprises grid and the sweep trace of thin film transistor (TFT);
One first insulation course, described first insulation course is arranged on described the first metal layer, for isolating described the first metal layer and the second metal level;
Second metal level described in one, described second metal level is arranged on described first insulation course; Described second metal level comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line;
One second insulation course, described second insulation course is arranged on described second metal level, for isolating described second metal level and pixel electrode layer;
One is protruding, and described projection is arranged on described second insulation course;
Pixel electrode layer described in one, described pixel electrode layer is arranged on described second insulation course; Described pixel electrode layer comprises pixel electrode and public electrode;
Wherein, described projection is between described pixel electrode and described public electrode, and described projection is for isolating described pixel electrode and public electrode.
Preferably, in described display panels, the thickness of described second insulation course at corresponding described raised position place is greater than the thickness of described second insulation course of non-protruding position.
Preferably, in described display panels, the thickness of described second metal level at corresponding described raised position place is greater than the thickness of described second metal level of non-protruding position.
Preferably, in described display panels, described the first metal layer also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described the first metal layer is as memory capacitance.
Preferably, in described display panels, described second metal level also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described second metal level is as memory capacitance.
Hinge structure, the present invention is by being provided with projection over the second dielectric, and between the pixel electrode of described projection in pixel electrode layer and public electrode, described projection is for isolating described pixel electrode and public electrode.Even if thus make electric capacity ITO and pixel ITO be positioned at same layer, also can not be subject to the impact of Particle, avoid electric capacity ITO and pixel ITO and be short-circuited, improve the quality of product.Be similar to a wall gear between electric capacity ITO and pixel ITO, can effectively prevent ITO short circuit from occurring, the short circuit avoiding the impact due to Particle to cause occurs.The design of described projection makes Particle not easily rest on the higher position of physical features; Even if there is Particle to drop on the position of described projection, but in the process through development and etching, the position because of projection is easy to be developed liquid or etching solution etches away, and therefore will greatly reduce because the short circuit that causes of Particle.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below.
[accompanying drawing explanation]
The structural representation of the array base palte that Fig. 1 provides for prior art;
The structural representation of the array base palte that Fig. 2 provides for the embodiment of the present invention two;
The structural representation of the array base palte that Fig. 3 provides for the embodiment of the present invention three.
[embodiment]
The word " embodiment " that this instructions uses means to be used as example, example or illustration.In addition, the article " " used in this instructions and claims usually can be interpreted as meaning " one or more ", unless otherwise or from context clear guiding singulative.
In embodiments of the present invention, by being provided with projection over the second dielectric, between the pixel electrode of described projection in pixel electrode layer and public electrode, described projection is for isolating described pixel electrode and public electrode.Even if thus make electric capacity ITO and pixel ITO be positioned at same layer, also can not be subject to the impact of Particle, avoid electric capacity ITO and pixel ITO and be short-circuited, improve the quality of product.
Embodiment one
Referring to Fig. 2, is the structural representation of the array base palte that the embodiment of the present invention provides.For convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
Described array base palte comprises: substrate 100, the first metal layer 101,1 first insulation course 102,1 second metal level 103,1 second insulation course 104 and a pixel electrode layer 105.Wherein, described the first metal layer 101 is arranged at described substrate 100 on the surface; Described first insulation course 102 is arranged on described the first metal layer 101; Described second metal level 103 is arranged on described first insulation course 102; Described first insulation course 102 is for isolating described the first metal layer 101 and the second metal level 103; Described second insulation course 104 is arranged on described second metal level 103; Described pixel electrode layer 105 is arranged on described second insulation course 104; Described second insulation course 104 is for isolating described second metal level 103 and pixel electrode layer 105.
In embodiments of the present invention, at substrate 100 deposited on silicon the first metal layer 101, and then utilize gold-tinted and etch process to form the pattern of the first metal layer 101, wherein the pattern of this first metal layer 101 comprises grid and the sweep trace of thin film transistor (TFT).When the public electrode in described pixel electrode layer 105 and described the first metal layer 101 are as memory capacitance, so the pattern of this first metal layer 101 also comprises concentric line, and this concentric line and public electrode form memory capacitance.
In embodiments of the present invention, after sputtering sedimentation second metal level 103, and then utilize gold-tinted and etch process to form the pattern of the second metal level 103, wherein, the pattern of described second metal level 103 comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line.When the public electrode in described pixel electrode layer 105 and described second metal level 103 are as memory capacitance, so the pattern of this second metal level 103 also comprises concentric line, and this concentric line and public electrode form memory capacitance.
In embodiments of the present invention, after sputtering sedimentation one pixel electrode layer 105, and then utilize gold-tinted and etch process to form the pattern of described pixel electrode layer 105, wherein, the pattern of described pixel electrode layer 105 comprises pixel electrode and public electrode.
In embodiments of the present invention, described pixel electrode layer 105 adopts ITO (IndiumTin Oxide, tin-doped indium oxide) or indium-zinc oxide IZO etc. material to make; Described first insulation course 102 can adopt G-Sinx material to make; Described second insulation course 104 can adopt P-Sinx material to make.But be understandable that, be not limited to above-mentioned material, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
In embodiments of the present invention, the second insulation course 104 is provided with between protruding 106, described protruding 106 pixel electrodes in pixel electrode layer 105 and public electrode, described protruding 106 for isolating described pixel electrode and public electrode.
In embodiments of the present invention, described pixel electrode in described pixel electrode layer 105 and the common electrode on relative substrate are as pixel capacitance, and the concentric line on described public electrode and described the first metal layer 101 or described second metal level 103 is as memory capacitance; Owing to having described protruding 106 between the described pixel electrode in described pixel electrode layer 105 and described public electrode, therefore, it is possible to described pixel electrode and described public electrode are isolated.
As from the foregoing, described protruding 106 are positioned at described pixel electrode layer 105 (namely with between layer ITO), be similar to a wall gear between electric capacity ITO and pixel ITO, can effectively prevent ITO short circuit from occurring, the short circuit avoiding the impact due to Particle to cause occurs.The design of described projection makes Particle not easily rest on the higher position of physical features; Even if there is Particle to drop on the position of described projection, but in the process through development and etching, the position because of projection is easy to be developed liquid or etching solution etches away, and therefore will greatly reduce because the short circuit that causes of Particle.
Embodiment two
Referring to Fig. 2, is the structural representation of the array base palte that the embodiment of the present invention provides.For convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
Described array base palte comprises a substrate 100, and the first metal layer 101, first insulation course 102, second metal level 103, second insulation course 104 be set in turn on described substrate 100 surface and pixel electrode layer 105.Wherein, described the first metal layer 101 comprises grid and the sweep trace of thin film transistor (TFT); Described second metal level 103 comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line; Described pixel electrode layer 105 comprises pixel electrode and public electrode.Described first insulation course 102 is for isolating described the first metal layer 101 and the second metal level 103; Described second insulation course 104 is for isolating described second metal level 103 and pixel electrode layer 105.
In embodiments of the present invention, described pixel electrode in described pixel electrode layer 105 and the common electrode on relative substrate are as pixel capacitance, and the concentric line on described public electrode and described the first metal layer 101 or described second metal level 103 is as memory capacitance.Second insulation course 104 is provided with between protruding 106, described protruding 106 pixel electrodes in pixel electrode layer 105 and public electrode, described protruding 106 for isolating described pixel electrode and public electrode.
In the present embodiment two, described protruding 106 are thickened by described second metal level 103 and are formed.Namely the thickness of described second metal level 103 of corresponding described protruding 106 positions is greater than the thickness of described second metal level 103 of non-protruding position.Described second metal level 103 of this part of the interstitial site namely between the described pixel electrode of correspondence and described public electrode, photoresistance is being smeared to described second metal level 103 of this part, exposure, development, during etching operation, make the thickness of this position thicker than the thickness of other positions, so just, make the second insulation course 104 of second metal level 103 this position padded of this position, thus the height of this position exceeds clearance height, this gap is made to present projection, be similar to a wall gear between electric capacity ITO and pixel ITO, by electric capacity ITO and pixel ITO isolation, can effectively prevent ITO short circuit from occurring, the short circuit avoiding the impact due to Particle to cause occurs.
Embodiment three
Referring to Fig. 3, is the structural representation of the array base palte that the embodiment of the present invention provides.For convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.
Described array base palte comprises: substrate 100, the first metal layer 101,1 first insulation course 102,1 second metal level 103,1 second insulation course 104 and a pixel electrode layer 105.Wherein, described the first metal layer 101 is arranged at described substrate 100 on the surface; Described first insulation course 102 is arranged on described the first metal layer 101; Described second metal level 103 is arranged on described first insulation course 102; Described first insulation course 102 is for isolating described the first metal layer 101 and the second metal level 103; Described second insulation course 104 is arranged on described second metal level 103; Described pixel electrode layer 105 is arranged on described second insulation course 104; Described second insulation course 104 is for isolating described second metal level 103 and pixel electrode layer 105.
Wherein, described the first metal layer 101 comprises grid and the sweep trace of thin film transistor (TFT); Described second metal level 103 comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line; Described pixel electrode layer 105 comprises pixel electrode and public electrode.When the public electrode in described pixel electrode layer 105 and described the first metal layer 101 are as memory capacitance, so the pattern of this first metal layer 101 also comprises concentric line, and this concentric line and public electrode form memory capacitance.When the public electrode in described pixel electrode layer 105 and described second metal level 103 are as memory capacitance, so the pattern of this second metal level 103 also comprises concentric line, and this concentric line and public electrode form memory capacitance.
In embodiments of the present invention, described pixel electrode in described pixel electrode layer 105 and the common electrode on relative substrate are as pixel capacitance, and the concentric line on described public electrode and described the first metal layer 101 or described second metal level 103 is as memory capacitance.Second insulation course 104 is provided with between protruding 106, described protruding 106 pixel electrodes in pixel electrode layer 105 and public electrode, described protruding 106 for isolating described pixel electrode and public electrode.
In the present embodiment three, described protruding 106 are thickened by described second insulation course 104 and are formed.Namely the thickness of described second insulation course 104 at corresponding described raised position place is greater than the thickness of described second insulation course 104 of non-protruding position.Described second insulation course 104 of this part of the interstitial site namely between the described pixel electrode of correspondence and described public electrode, photoresistance is being smeared to described second insulation course 104 of this part, exposure, development, during etching operation, make the thickness of this position thicker than the thickness of other positions, so just, make the height of the second insulation course 104 of this position exceed clearance height, this gap is made to present projection, be similar to a wall gear between electric capacity ITO and pixel ITO, by electric capacity ITO and pixel ITO isolation, can effectively prevent ITO short circuit from occurring, the short circuit avoiding the impact due to Particle to cause occurs.The design of described projection makes Particle not easily rest on the higher position of physical features; Even if there is Particle to drop on the position of described projection, but in the process through development and etching, the position because of projection is easy to be developed liquid or etching solution etches away, and therefore will greatly reduce because the short circuit that causes of Particle.
Embodiment four
The embodiment of the present invention additionally provides a kind of display panels.For convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.The liquid crystal cell that described display panels comprises array base palte, color membrane substrates and is arranged between described array base palte and color membrane substrates.
Described array base palte comprises: substrate 100, the first metal layer 101,1 first insulation course 102,1 second metal level 103,1 second insulation course 104 and a pixel electrode layer 105.Wherein, described the first metal layer 101 is arranged at described substrate 100 on the surface; Described first insulation course 102 is arranged on described the first metal layer 101; Described second metal level 103 is arranged on described first insulation course 102; Described first insulation course 102 is for isolating described the first metal layer 101 and the second metal level 103; Described second insulation course 104 is arranged on described second metal level 103; Described pixel electrode layer 105 is arranged on described second insulation course 104; Described second insulation course 104 is for isolating described second metal level 103 and pixel electrode layer 105.
Wherein, described the first metal layer 101 comprises grid and the sweep trace of thin film transistor (TFT); Described second metal level 103 comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line; Described pixel electrode layer 105 comprises pixel electrode and public electrode.When the public electrode in described pixel electrode layer 105 and described the first metal layer 101 are as memory capacitance, so the pattern of this first metal layer 101 also comprises concentric line, and this concentric line and public electrode form memory capacitance.When the public electrode in described pixel electrode layer 105 and described second metal level 103 are as memory capacitance, so the pattern of this second metal level 103 also comprises concentric line, and this concentric line and public electrode form memory capacitance.
In embodiments of the present invention, described pixel electrode in described pixel electrode layer 105 and the common electrode on relative substrate are as pixel capacitance, and the concentric line on described public electrode and described the first metal layer 101 or described second metal level 103 is as memory capacitance.Second insulation course 104 is provided with between protruding 106, described protruding 106 pixel electrodes in pixel electrode layer 105 and public electrode, described protruding 106 for isolating described pixel electrode and public electrode.
But be understandable that, described projection can be thickened by described second insulation course and be formed; Namely the thickness of described second insulation course 104 at corresponding described raised position place is greater than the thickness of described second insulation course 104 of non-protruding position.Or described projection can be thickened by described second metal level and be formed; Namely the thickness of described second metal level 103 of corresponding described protruding 106 positions is greater than the thickness of described second metal level 103 of non-protruding position.
In sum, by being provided with projection over the second dielectric, described projection can be thickened by described second insulation course and be formed; Or described projection can be thickened by described second metal level and be formed; Between the pixel electrode of described projection in pixel electrode layer and public electrode, described projection is for isolating described pixel electrode and public electrode.Even if thus make electric capacity ITO and pixel ITO be positioned at same layer, also can not be subject to the impact of Particle, avoid electric capacity ITO and pixel ITO and be short-circuited, improve the quality of product.Be similar to a wall gear between electric capacity ITO and pixel ITO, can effectively prevent ITO short circuit from occurring, the short circuit avoiding the impact due to Particle to cause occurs.The design of described projection makes Particle not easily rest on the higher position of physical features; Even if there is Particle to drop on the position of described projection, but in the process through development and etching, the position because of projection is easy to be developed liquid or etching solution etches away, and therefore will greatly reduce because the short circuit that causes of Particle.
Although illustrate and describe the present invention relative to one or more implementation, those skilled in the art are based on to the reading of this instructions and accompanying drawing with understand and will expect equivalent variations and amendment.The present invention includes all such amendments and modification, and only limited by the scope of claims.Especially about the various functions performed by said modules, term for describing such assembly is intended to the random component (unless otherwise instructed) corresponding to the appointed function (such as it is functionally of equal value) performing described assembly, even if be not structurally equal to the open structure of the function in the exemplary implementations performing shown in this article instructions.In addition, although the special characteristic of this instructions relative in some implementations only one be disclosed, this feature can with can be such as expect and other Feature Combinations one or more of other favourable implementations for given or application-specific.And, " comprise " with regard to term, " having ", " containing " or its distortion be used in embodiment or claim with regard to, such term is intended to comprise " to comprise " similar mode to term.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is also not used to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various change and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. an array base palte, is characterized in that, described array base palte comprises:
One substrate;
One the first metal layer, described the first metal layer is arranged on described substrate surface; Described the first metal layer comprises grid and the sweep trace of thin film transistor (TFT);
One first insulation course, described first insulation course is arranged on described the first metal layer, for isolating described the first metal layer and the second metal level;
Second metal level described in one, described second metal level is arranged on described first insulation course; Described second metal level comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line;
One second insulation course, described second insulation course is arranged on described second metal level, for isolating described second metal level and pixel electrode layer;
One is protruding, and described projection is arranged on described second insulation course;
Pixel electrode layer described in one, described pixel electrode layer is arranged on described second insulation course; Described pixel electrode layer comprises pixel electrode and public electrode;
Wherein, described projection is between described pixel electrode and described public electrode, and described projection is for isolating described pixel electrode and public electrode.
2. array base palte according to claim 1, is characterized in that, the thickness of described second insulation course at corresponding described raised position place is greater than the thickness of described second insulation course of non-protruding position.
3. array base palte according to claim 1, is characterized in that, the thickness of described second metal level at corresponding described raised position place is greater than the thickness of described second metal level of non-protruding position.
4. array base palte according to claim 1, is characterized in that, described the first metal layer also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described the first metal layer is as memory capacitance.
5. array base palte according to claim 1, is characterized in that, described second metal level also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described second metal level is as memory capacitance.
6. a display panels, the liquid crystal cell comprising array base palte, color membrane substrates and be arranged between described array base palte and color membrane substrates; It is characterized in that,
Described array base palte comprises:
One substrate;
One the first metal layer, described the first metal layer is arranged on described substrate surface; Described the first metal layer comprises grid and the sweep trace of thin film transistor (TFT);
One first insulation course, described first insulation course is arranged on described the first metal layer, for isolating described the first metal layer and the second metal level;
Second metal level described in one, described second metal level is arranged on described first insulation course; Described second metal level comprises the source electrode of thin film transistor (TFT), the drain electrode of thin film transistor (TFT) and data line;
One second insulation course, described second insulation course is arranged on described second metal level, for isolating described second metal level and pixel electrode layer;
One is protruding, and described projection is arranged on described second insulation course;
Pixel electrode layer described in one, described pixel electrode layer is arranged on described second insulation course; Described pixel electrode layer comprises pixel electrode and public electrode;
Wherein, described projection is between described pixel electrode and described public electrode, and described projection is for isolating described pixel electrode and public electrode.
7. display panels according to claim 6, is characterized in that, the thickness of described second insulation course at corresponding described raised position place is greater than the thickness of described second insulation course of non-protruding position.
8. display panels according to claim 6, is characterized in that, the thickness of described second metal level at corresponding described raised position place is greater than the thickness of described second metal level of non-protruding position.
9. display panels according to claim 6, is characterized in that, described the first metal layer also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described the first metal layer is as memory capacitance.
10. display panels according to claim 6, is characterized in that, described second metal level also comprises concentric line; Described pixel electrode and the common electrode on relative substrate are as pixel capacitance, and the described concentric line on described public electrode and described second metal level is as memory capacitance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054837.9A CN104614908B (en) | 2015-02-02 | 2015-02-02 | A kind of array base palte and liquid crystal display panel |
| PCT/CN2015/072427 WO2016123800A1 (en) | 2015-02-02 | 2015-02-06 | Array substrate and liquid crystal display panel |
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| CN201510054837.9A CN104614908B (en) | 2015-02-02 | 2015-02-02 | A kind of array base palte and liquid crystal display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110718570A (en) * | 2019-09-17 | 2020-01-21 | 深圳市华星光电技术有限公司 | Display panel and display device |
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| CN106154654B (en) * | 2016-08-26 | 2019-08-13 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837910A (en) * | 2005-03-23 | 2006-09-27 | Nec液晶技术株式会社 | Active matrix liquid crystal display device |
| CN1991480A (en) * | 2005-12-29 | 2007-07-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN103278979A (en) * | 2012-09-27 | 2013-09-04 | 上海天马微电子有限公司 | Array substrate of plane type liquid crystal displayer and manufacturing method thereof |
| CN203250093U (en) * | 2013-05-31 | 2013-10-23 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal displaying device |
| US20140132865A1 (en) * | 2012-11-09 | 2014-05-15 | Japan Display Inc. | Liquid crystal display device |
| CN104007574A (en) * | 2014-06-18 | 2014-08-27 | 南京中电熊猫液晶显示科技有限公司 | Array substrate, display device and manufacturing method of display device |
-
2015
- 2015-02-02 CN CN201510054837.9A patent/CN104614908B/en active Active
- 2015-02-06 WO PCT/CN2015/072427 patent/WO2016123800A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837910A (en) * | 2005-03-23 | 2006-09-27 | Nec液晶技术株式会社 | Active matrix liquid crystal display device |
| CN1991480A (en) * | 2005-12-29 | 2007-07-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN103278979A (en) * | 2012-09-27 | 2013-09-04 | 上海天马微电子有限公司 | Array substrate of plane type liquid crystal displayer and manufacturing method thereof |
| US20140132865A1 (en) * | 2012-11-09 | 2014-05-15 | Japan Display Inc. | Liquid crystal display device |
| CN203250093U (en) * | 2013-05-31 | 2013-10-23 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal displaying device |
| CN104007574A (en) * | 2014-06-18 | 2014-08-27 | 南京中电熊猫液晶显示科技有限公司 | Array substrate, display device and manufacturing method of display device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110718570A (en) * | 2019-09-17 | 2020-01-21 | 深圳市华星光电技术有限公司 | Display panel and display device |
| WO2021051641A1 (en) * | 2019-09-17 | 2021-03-25 | Tcl华星光电技术有限公司 | Display panel and display device |
| US11215886B2 (en) | 2019-09-17 | 2022-01-04 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel and display device |
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| CN104614908B (en) | 2017-08-25 |
| WO2016123800A1 (en) | 2016-08-11 |
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