CN104604133B - 复合型半导体器件 - Google Patents
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Abstract
一种复合型半导体器件,其包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件选择满足(1)式的上述第二晶体管。其中,Coss:上述第二晶体管的输出电容,Cds:上述第一晶体管的漏极-源极间电容,Cgs:上述第一晶体管的栅极-源极间电容,Vds:电源电压,Vbr:上述第二晶体管的击穿电压。。
Description
技术领域
本发明涉及复合型半导体器件,特别涉及包括串联连接的常导通型(normally-on-type)晶体管和常截止型(normally-off-type)晶体管的复合型半导体器件。
背景技术
在现在的半导体器件中主要使用的Si(硅)类的场效应晶体管是常截止型的。常截止型场效应晶体管是,在栅极-源极间施加了正电压时导通,在栅极-源极间没有施加正电压时不导通的晶体管。
此外,因为具有高耐压、低损失、高速开关、高温动作等特征而不断被深化实用化研究的GaN(氮化镓)类、SiC(碳化硅)的场效应晶体管是常导通型的。常导通型场效应晶体管具有负的阈值电压,在栅极-源极间电压低于阈值电压时不导通,在栅极-源极间电压高于阈值电压时导通。
当在半导体器件中使用这样的常导通型场效应晶体管时,产生不能够使用现有的栅极驱动电路等的各种问题。于是,提出将常导通型的第一场效应晶体管和常截止型的第二场效应晶体管串联连接,构成常截止型的复合型半导体器件的方案。
例如,在专利文献1中公开了,作为这样的复合型半导体器件,为了防止常截止型的第二场效应晶体管的漏极-源极间电压比耐压高,第二场效应晶体管成为雪崩状态而发生破坏,而在第二场效应晶体管的漏极-源极间连接稳压二极管,将漏极-源极间电压限制为耐压以下的电压。
现有技术文献
专利文献
专利文献1:日本特开2006-324839号公报
非专利文献
非专利文献1:[Stability and performance analysis of a SiC-basedcascode switch and an alternative solution],Ralf Siemieniec,MicroelectronicsReliability,Volume 52,Issue 3,March 2012,Pages509-518.
发明内容
发明要解决的问题
但是,在上述专利文献1中,存在因为第一场效应晶体管关断时第二场效应晶体管的电荷脱逸,控制变得不稳定的问题(参照非专利文献1)。
于是,本发明的目的在于提供一种能够抑制常截止型晶体管的破坏和控制不稳定的复合型半导体器件。
用于解决问题的技术方案
为了达成上述目的,本发明的一个方式的复合型半导体器件包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:选择满足(1)式的上述第二晶体管,
其中,Coss:上述第二晶体管的输出电容,Cds:上述第一晶体管的漏极-源极间电容,Cgs:上述第一晶体管的栅极-源极间电容,Vds:电源电压,Vbr:上述第二晶体管的击穿电压。
此外,本发明的另一方式的复合型半导体器件包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:选择满足(2)式的上述第二晶体管,
其中,Coss:上述第二晶体管的输出电容,Cds:上述第一晶体管的漏极-源极间电容,Cgs:上述第一晶体管的栅极-源极间电容,Vds:电源电压,Vbr:上述第二晶体管的击穿电压。
此外,本发明的另一方式的复合型半导体器件包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:选择电源电压Vds与上述第二晶体管的击穿电压Vbr之比为10以上且满足(3)式的上述第二晶体管,
其中,Coss:上述第二晶体管的输出电容,Cds:上述第一晶体管的漏极-源极间电容。
此外,本发明的另一方式的复合型半导体器件包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:选择电源电压Vds与上述第二晶体管的击穿电压Vbr之比为10以上且满足(4)式的上述第一晶体管,
其中,Coss:上述第二晶体管的输出电容,Cds:上述第一晶体管的漏极-源极间电容。
此外,本发明的另一方式的复合型半导体器件包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:选择满足(5)式的上述第一晶体管和上述第二晶体管,
其中,Coss:上述第二晶体管的输出电容,Cds:上述第一晶体管的漏极-源极间电容,Cgs:上述第一晶体管的栅极-源极间电容,Vds:电源电压,Vm1:使上述第二晶体管截止之后,上述第一晶体管成为截止的时刻的上述第二晶体管的漏极电压,Vbr:上述第二晶体管的击穿电压。
发明效果
根据本发明的复合型半导体器件,不使用会成为控制不稳定的原因的追加器件,在关断的期间,能够将常截止型的第二晶体管的漏极电压抑制得比击穿电压低,能够抑制第二晶体管的破坏。
附图说明
图1是本发明的一实施方式的复合型半导体器件的结构图。
图2是表示本发明的一实施方式的模拟用的L负载电路的图。
图3是表示作为本发明的一实施方式的模拟结果的第二FET的漏极电压的分析波形的曲线图。
图4是表示作为本发明的一实施方式的模拟结果的第二FET的漏极电压的分析波形的曲线图。
图5是表示本发明的一实施方式的电源电压与最终的第二FET的漏极电压的实测值的关系的曲线图。
图6是表示本发明的一实施方式第二FET的漏极电压与第二FET的输出电容的测定值的关系的曲线图。
图7是表示本发明的一实施方式的第二FET的漏极电压的实测值和计算值的曲线图。
具体实施方式
以下参照附图说明本发明的一实施方式。本发明的一实施方式的复合型半导体器件的结构表示于图1。
图1所示的复合型半导体器件1包括:高耐压常导通型的第一场效应晶体管(以下称为FET)Tr1;低耐压常截止型的第二FET Tr2;第一FETTr1的栅极-漏极间电容Cgd;第一FETTr1的栅极-源极间电容Cgs;第一FETTr1的漏极-源极间电容Cds;第二FETTr2的栅极-漏极间电容Cgd2;第二FETTr2的漏极-源极间电容Cds2;栅极电阻Rg;电源端子T1;接地端子T2;和栅极端子T3。
第一FETTr1与第二FETTr2串联连接。在第一FETTr1的漏极连接被施加电源电压Vds的电源端子T1。在第二FETTr2的源极连接与接地电位连接的接地端子T2。
在第二FETTr2的栅极连接栅极端子T3。此外,在第二FETTr2的源极与接地端子T2的连接点与第一FETTr1的栅极之间***有栅极电阻Rg。另外,也可以不设置栅极电阻Rg地使第二FETTr2的源极与接地端子T2的连接点与第一FETTr1的栅极短路。
接着,说明在这样构成的复合型半导体器件1中的第一FETTr1和第二FETTr2为导通的状态下使第二FETTr2截止时的第二FETTr2的漏极电压Vm的变动。
在第一FETTr1和第二FETTr2为导通的状态下,使第二FETTr2的栅极-源极间电压从导通电压变为截止电压时,产生第二FETTr2的漏极-源极间电压,第一FETTr1的源极电压上升,在第一FETTr1的栅极-源极间电压到达负的阈值电压Vth之前,第二FETTr2的漏极电压Vm上升。将第一FETTr1的栅极-源极间电压达到阈值电压Vth时的第二FETTr2的漏极电压Vm设为Vm1,Vm1由(1)式表示。
其中,Rg:栅极电阻Rg的电阻值,Cgd:第一FETTr1的栅极-漏极间电容Cgd的电容值,Cgs:第一FETTr1的栅极-源极间电容Cgs的电容值,k:表示第二FETTr2的漏极电压上升程度的常数,t:时间。
上述(1)式中,时间t满足(2)式。
其中,Ciss=Cgd+Cgs,是第一FETTr1的输入电容。
在第二FETTr2的漏极电压Vm到达Vm1的时刻,第一FETTr1截止,产生第一FETTr1的漏极-源极间电压。另外,根据式(1)可知,在没有设置第一FETTr1的栅极电阻Rg的情况下,Rg=0,Vm1=-Vth。
接着,说明从第一FETTr1截止起的第二FETTr2的漏极电压Vm的上升。第一FETTr1截止,在第一FETTr1的漏极-源极间产生电压。此时,第二FETTr2的漏极电压Vm依据(3)式上升。
其中,Cds:第一FETTr1的漏极-源极间电容Cds的电容值,Coss:第二FETTr2的输出电容(第二FETTr2的漏极-源极间电容Cds2和第二FETTr2的栅极-漏极间电容Cgd2的合计电容值),k2:表示第一FETTr1的漏极电压上升程度的常数。
Vm在第一FETTr1的漏极电压到达电源电压Vds之前依据(3)式上升,因此在k2×t=Vds的时刻停止上升。最终在Vm达到(4)式表示的Vm2的时刻,Vm的上升停止。
此处,如上所述在第二FETTr2的漏极电压Vm到达Vm1的时刻,蓄电于第二FETTr2的漏极-源极间电容的电荷作为偏移量残留,因此最终的Vm的值由Vm1和Vm2的和表示。
此处,为了在复合型半导体器件1的关断期间第二FETTr2不会击穿,在令第二FETTr2的击穿电压为Vbr时,以满足(5)式的方式构成第一FETTr1的漏极-源极间电容Cds、栅极-源极间电容Cgs和第二FETTr2的输出电容Coss即可。另外,Vm1有时也可以忽略。
此处,(5)式能够改写成(6)式。
由此,如果选择具有满足(6)式的输出电容Coss的第二FETTr2,则能够抑制在关断期间第二FETTr2破坏。此时,测定(6)式中的第一FETTr1的漏极-源极间电容Cds和栅极-源极间电容Cgs的各电容值即可,例如能够以下述文献1中记载的方法进行测定。此外,用于得到(6)式中的Coss的第二FETTr2的漏极-源极间电容Cds2和栅极-漏极间电容Cgd2的各电容值也例如能够由下述文献1中记载的方法测定。
<文献1>
Funaki,T.;Phankong,N.;Kimoto,T.;Hikihara,T.;,"Measuring TerminalCapacitance and Its Voltage Dependency for High-Voltage Power Devices,"PowerElectronics,IEEE Transactions on,vol.24,no.6,pp.1486-1493,June2009
doi:10.1109/TPEL.2009.2016566.
此外,(5)式也能够改写为(7)式。
由此,如果选择具有满足(7)式的漏极-源极间电容Cds的第一FETTr1,则能够抑制关断期间第二FETTr2破坏。此时,(7)式中的各电容值例如能够由上述文献1记载的方法测定。
另外,在电源电压Vds与击穿电压Vbr之比为10以上时,在(6)式右边,第一项以外的项能够忽略,因此(6)式成为(8)式。由此,在该情况下,如果选择具有满足(8)式的输出电容Coss的第二FETTr2,则能够抑制关断期间第二FETTr2破坏。
进一步,(8)式改写为(9)式。由此,如果选择具有满足(9)式的漏极-源极间电容Cds的第一FETTr1,则能够抑制关断期间第二FETTr2破坏。
此外,如上所述,最终的Vm由Vm1与Vm2之和表示,因此(10)成立。
由此,在不能够忽略Vm1时,或严格考虑Vm1时,为了在关断期间抑制第二FETTr2破坏,在令第二FETTr2的击穿电压为Vbr时,以满足(11)式的方式构成第一FETTr1的漏极-源极间电容、栅极-源极间电容和第二FETTr2的输出电容即可(即,选择具有这样的电容的第一FETTr1和第二FETTr2)。
进一步,栅极电阻Rg=0时根据(1)式,(11)式能够改写为(12)式,因此选择满足(12)式的第一FETTr1和第二FETTr2即可。
如上所述,通过适当地选择第二FETTr2和/或第一FETTr1,不使用会成为控制不稳定的原因的追加器件,就能够抑制第二FETTr2的破坏。
此处,当使第二FETTr2的输出电容Coss增大时,满足(5)式或(11)式的条件明显很容易达到,但担心会由于电容增加而导致开关损失增加。但是,如果采用本实施方式的共射共基(cascode)结构,则施加于第一FETTr1的漏极-源极间的电压最小为(电源电源-第二FETTr2的击穿电压)、且最大为(电源电压-第一FETTr1的阈值电压),所以对开关损失造成大幅影响的高电压施加于第一FETTr1。由此,第二FETTr2对于开关损失几乎不造成影响。由此,能够不使开关损失变差地提高共射共基器件的可靠性。
接着,模拟进行本实施方式的验证。以图2所示的L负载电路进行模拟。第一FETTr1、第二FETTr2的各电容表示于表1的方案1。使电源电压为600V,使第一FETTr1的阈值电压为-6.5。此外,使第二FETTr2的击穿电压为20V。
[表1]
方案1 | 方案2 | |
Coss(pF) | 950 | 950 |
Cds(pF) | 50 | 25 |
Cgs(pF) | 150 | 150 |
作为模拟结果的第二FETTr2的漏极电压Vm的分析波形表示于图3。Vm最终为33V,大幅超过20V的击穿电压。根据(10)式计算,使Vm1为6.6V时,Vm=Vm1+Vm2=6.6V+50pF/(950pF+50pF+150pF)×600V=33V。
于是,以满足(11)式的方式调整Cds,20V>6.6V+Cds/(950pF+Cds+150pF)×600V,Cds<25.13pF。为了确认效果,在图1所示的方案2中使Cds=25pF而进行模拟。在图4表示作为其结果的Vm的分析波形。根据分析结果可知,Vm最终为19.5V,低于20V的击穿电压,能够达到目标。
此外,为了通过实测来验证本实施方式的有效性,在仅使第一FET的漏极-源极间电容改变的2种复合型半导体器件A、B中进行Vm的实测评价。复合型半导体器件中的各电容由上述文献1的方法测定。复合型半导体器件A、B的第一FET的漏极-源极间电容Cds表示于表2。
[表2]
Vds(V) | Cds_A(pF) | Cds_B(pF) |
100 | 30 | 37 |
200 | 23 | 31 |
300 | 22 | 29 |
如表2所示,根据电源电压Vds的不同,在相同的器件中漏极-源极间电容Cds也会发生变化。这是因为当电源电压Vds变大时,沟道的耗尽化不断发展,电容变小。此外,令第一FET的栅极-源极间电容Cgs为160pF。虽然Cgs也根据电源电压的不同发生变化,但在此处使用的器件中该变化非常小,因此令其为一定值。
此外,第二FET的输出电容Coss的情况如下所述。对于复合型半导体器件A、B在图5中表示电源电压Vds和最终Vm的实测值的关系。例如,电源电压Vds=100V时Vm为13V附近,Vds=300V时Vm为25V附近。此外,在图6中表示使Vm逐渐变化而测定出的Coss。根据图6可知,在Vm=15V附近时,Coss为330pF,在Vm=25V附近时,Coss为290pF。由此,对于Coss,使用与对应于电源电压Vds的最终的Vm值对应的值。
此外,使阈值电压为-7V。在图7中表示实测的Vm2与(4)式的计算值的Vm2的比较结果。可知实测结果与式(4)的计算值精度非常一致。
以上,对本发明的实施方式进行了说明,但在本发明的主旨的范围内,实施方式能够进行各种变更。
附图标记说明
1 复合型半导体器件
Tr1 第一场效应晶体管
Tr2 第二场效应晶体管
Rg 栅极电阻
Vds 电源电压
T1 电源端子
T2 接地端子
T3 栅极端子
Claims (5)
1.一种复合型半导体器件,其包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:
所述第一晶体管的源极与所述第二晶体管的漏极连接,所述第一晶体管的栅极与所述第二晶体管的源极经电阻连接,所述第一晶体管的漏极与电源端子连接,
选择满足(1)式的所述第二晶体管,
其中,Coss:所述第二晶体管的漏极-源极间电容和栅极-漏极间电容的合计电容值,Cds:所述第一晶体管的漏极-源极间电容,Cgs:所述第一晶体管的栅极-源极间电容,Vds:施加于所述电源端子的电源电压,Vbr:所述第二晶体管的击穿电压。
2.一种复合型半导体器件,其包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:
所述第一晶体管的源极与所述第二晶体管的漏极连接,所述第一晶体管的栅极与所述第二晶体管的源极经电阻连接,所述第一晶体管的漏极与电源端子连接,
选择满足(2)式的所述第一晶体管,
其中,Coss:所述第二晶体管的漏极-源极间电容和栅极-漏极间电容的合计电容值,Cds:所述第一晶体管的漏极-源极间电容,Cgs:所述第一晶体管的栅极-源极间电容,Vds:施加于所述电源端子的电源电压,Vbr:所述第二晶体管的击穿电压。
3.一种复合型半导体器件,其包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:
所述第一晶体管的源极与所述第二晶体管的漏极连接,所述第一晶体管的栅极与所述第二晶体管的源极经电阻连接,所述第一晶体管的漏极与电源端子连接,
选择施加于所述电源端子的电源电压Vds与所述第二晶体管的击穿电压Vbr之比为10以上且满足(3)式的所述第二晶体管,
其中,Coss:所述第二晶体管的漏极-源极间电容和栅极-漏极间电容的合计电容值,Cds:所述第一晶体管的漏极-源极间电容。
4.一种复合型半导体器件,其包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:
所述第一晶体管的源极与所述第二晶体管的漏极连接,所述第一晶体管的栅极与所述第二晶体管的源极经电阻连接,所述第一晶体管的漏极与电源端子连接,
选择施加于所述电源端子的电源电压Vds与所述第二晶体管的击穿电压Vbr之比为10以上且满足(4)式的所述第一晶体管,
其中,Coss:所述第二晶体管的漏极-源极间电容和栅极-漏极间电容的合计电容值,Cds:所述第一晶体管的漏极-源极间电容。
5.一种复合型半导体器件,其包括串联连接的常导通型的第一晶体管和常截止型的第二晶体管,该复合型半导体器件的特征在于:
所述第一晶体管的源极与所述第二晶体管的漏极连接,所述第一晶体管的栅极与所述第二晶体管的源极经电阻连接,所述第一晶体管的漏极与电源端子连接,
选择满足(5)式的所述第一晶体管和所述第二晶体管,
其中,Coss:所述第二晶体管的漏极-源极间电容和栅极-漏极间电容的合计电容值,Cds:所述第一晶体管的漏极-源极间电容,Cgs:所述第一晶体管的栅极-源极间电容,Vds:施加于所述电源端子的电源电压,Vm1:使所述第二晶体管截止之后,所述第一晶体管成为截止的时刻的所述第二晶体管的漏极电压,Vbr:所述第二晶体管的击穿电压。
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