CN104600041B - A kind of two-side radiation semiconductor package structure and its method for packing - Google Patents

A kind of two-side radiation semiconductor package structure and its method for packing Download PDF

Info

Publication number
CN104600041B
CN104600041B CN201410822723.XA CN201410822723A CN104600041B CN 104600041 B CN104600041 B CN 104600041B CN 201410822723 A CN201410822723 A CN 201410822723A CN 104600041 B CN104600041 B CN 104600041B
Authority
CN
China
Prior art keywords
chip
fin
lead frame
colloid
chip carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410822723.XA
Other languages
Chinese (zh)
Other versions
CN104600041A (en
Inventor
曹周
敖利波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Great Team Backend Foundry Dongguan Co Ltd
Original Assignee
Great Team Backend Foundry Dongguan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Great Team Backend Foundry Dongguan Co Ltd filed Critical Great Team Backend Foundry Dongguan Co Ltd
Priority to CN201410822723.XA priority Critical patent/CN104600041B/en
Publication of CN104600041A publication Critical patent/CN104600041A/en
Application granted granted Critical
Publication of CN104600041B publication Critical patent/CN104600041B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a kind of two-side radiation semiconductor package structure and its method for packing, the two-side radiation semiconductor package structure includes:It is wrapped in lead frame, the first combination material, chip, the second combination material and fin in colloid successively from bottom to up, described first is combined material with reference to material with described second includes the isometrical bead of high temperature resistance.The two-side radiation method for packing semiconductor, including prepare lead frame;Using first with reference to material on the chip carrier welding chip;The fin and the chip are welded with reference to material using second;The lead frame of the fin will be welded, be sent directly into oven cooking cycle;A glued membrane is sticked at the lead frame back side, the top surface of the bottom surface of the chip carrier and the fin leaks outside in the colloid after shaping.Described first is combined material with reference to material with described second includes the isometrical bead of high temperature resistance, the integral thickness of lead frame, chip and fin before accurate control encapsulation.

Description

A kind of two-side radiation semiconductor package structure and its method for packing
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of two-side radiation semiconductor package structure and its Method for packing.
Background technology
In semiconductor packaging, in order to ensure its thermal diffusivity, it is necessary to control the overall thickness of chip and fin before encapsulating Degree, current thickness control is difficult to ensure that its accuracy, and such as thickness is excessive, when integral molded plastic is molded, and chip can be caused to damage Bad, severe patient can crush chip, and such as thickness is excessively thin, when integral molded plastic is molded, and excessive glue can occur in surface on a heat sink Phenomenon, influences attractive in appearance and heat dispersion.
The content of the invention
, can be accurate it is an object of the invention to propose a kind of two-side radiation semiconductor package structure and its method for packing Control integral thickness.
For up to this purpose, the present invention uses following technical scheme:
In a first aspect, a kind of two-side radiation semiconductor package structure, including:
Lead frame, the lead frame includes chip carrier, interior pin and outer pin;
First combines material, and described first is located on the chip carrier with reference to material;
Chip, the chip is located at described first and combined on material;
Second combines material, and described second is located on the chip with reference to material;
Fin, the fin is located at described second and combined on material;
Colloid, the colloid cladding and the lead frame, the chip and the fin;
Described first is combined material with reference to material with described second includes the isometrical bead of high temperature resistance.
Further, the chip has relative acting surface and non-active face, and the non-active face of the chip passes through One is bonded in the upper surface of the chip carrier with reference to material, and the acting surface of the chip is bonded in the radiating by second with reference to material The lower surface of piece.
Further, it is provided with electronic building brick, the non-active face of the chip and is not provided with the acting surface of the chip Electronic building brick.
Further, the top surface of the bottom surface of the chip carrier and the fin exposes to the colloid.
Second aspect, the invention discloses a kind of two-side radiation method for packing semiconductor, including:
Prepare lead frame:The lead frame includes chip carrier, interior pin and outer pin;
Welding chip:Using first with reference to material on the chip carrier welding chip;
Chip welds fin:The fin and the chip are welded with reference to material using second;
Baking:The lead frame of the fin will be welded, be sent directly into oven cooking cycle, material is combined after baking and is solidified, is entered And semiconductor whole height is determined;
Injection molding;A glued membrane is sticked at the lead frame back side, mold-closing injection is carried out using colloid;
Described first is combined material with reference to material with described second includes the isometrical bead of high temperature resistance.
Further, the top surface of the bottom surface of the chip carrier and the fin exposes to the colloid.
A kind of two-side radiation semiconductor package structure and its method for packing that the present invention is provided, by above and below chip Surface oil carries the combination material for including the isometrical bead of high temperature resistance, carrys out accurate lead frame, chip and the radiating controlled before encapsulation The integral thickness of piece so that semiconductor will not damage chip by pressure and not result in semiconductor packages excessive glue in encapsulation process, is improved The package quality of product, further increases the integral heat sink performance of product.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the accompanying drawing used required in technology description to do one simply to introduce, it should be apparent that, drawings in the following description are this hairs Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the two-side radiation semiconductor package structure figure that the embodiment of the present invention one is provided;
Fig. 2 is the flow chart for the two-side radiation method for packing semiconductor that the embodiment of the present invention two is provided.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to attached in the embodiment of the present invention Figure, technical scheme is clearly and completely described by embodiment, it is clear that described embodiment is the present invention one Section Example, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making Go out the every other embodiment obtained under the premise of creative work, belong to the scope of protection of the invention.
Embodiment one:
Fig. 1 is the two-side radiation semiconductor package structure figure that the embodiment of the present invention one is provided.As shown in figure 1, this is two-sided Heat-radiating semiconductor encapsulating structure includes:
Lead frame 101, the lead frame includes chip carrier, interior pin and outer pin.
First combines material 102, and described first is located on the chip carrier with reference to material 102.
Chip 103, the chip 103 is located at described first and combined on material 102.
Second combines material 104, and described second is located on the chip 103 with reference to 104 materials.
Fin 105, the fin is located at described second and combined on material 104.
Colloid 106, the cladding of colloid 106 and the lead frame 101, the chip 103 and the fin 105, The top surface of the bottom surface of the chip carrier and the fin 105 exposes to the colloid;
Described first is combined material 104 with reference to material 102 with described second includes the isometrical bead of high temperature resistance.
Wherein, first is internal conducting resinl or solder(ing) paste containing the isometrical bead of high temperature resistance with reference to material 102, by for dispensing glue Mode, will be coated on the chip carrier of lead frame 101 with reference to material.
Second is internal conducting resinl or solder(ing) paste containing the isometrical bead of high temperature resistance with reference to material 104, by mode for dispensing glue, It will be coated in reference to material on chip 103.
A kind of two-side radiation semiconductor package structure provided in the embodiment of the present invention one, passes through the upper following table in chip Face is used with the combination material for including the isometrical bead of high temperature resistance, carrys out accurate lead frame, chip and the fin controlled before encapsulation Integral thickness.
Wherein, the chip 103 has relative acting surface and non-active face, and the non-active face of the chip 103 passes through First is bonded in the upper surface of the chip carrier of the lead frame 101 with reference to material 102, and the acting surface of the chip 103 passes through Two are bonded on the lower surface of the fin 105, the acting surface of the chip 103 with reference to material 104 and are provided with electronic building brick, institute State and be not provided with electronic building brick on the non-active face of chip.
Wherein, the top surface of the bottom surface of the chip carrier and the fin 105 exposes to the colloid 106.Chip carrier The top surface of bottom surface and fin 105 is not coated by colloid, can be carried out heat exchange with the external world in time, be radiated, increased The strong heat dispersion of semiconductor devices.
Embodiment two:
Fig. 2 is the flow chart for the two-side radiation method for packing semiconductor that the embodiment of the present invention two is provided.As shown in Fig. 2 The two-side radiation method for packing semiconductor includes:
Step 201, preparation lead frame, the lead frame include chip carrier, interior pin and outer pin;
Step 202, using first with reference to material on the chip carrier welding chip;
Step 203, using second the fin and the chip are welded with reference to material;
Step 204, the chip that will weld the fin, are sent directly into oven cooking cycle, and material is combined after baking and is solidified, and then Semiconductor whole height is determined;
Step 205, stick a glued membrane at the lead frame back side, carry out mold-closing injection;
Wherein, described first in step 202 and step 203 is combined material with described second with reference to material to include high temperature resistance isometrical Bead.
Wherein, first is internal conducting resinl or solder(ing) paste containing the isometrical bead of high temperature resistance with reference to material, passes through side for dispensing glue Formula, will be coated on the chip carrier of lead frame with reference to material.
Second is internal conducting resinl or solder(ing) paste containing the isometrical bead of high temperature resistance with reference to material, will by mode for dispensing glue It is coated in reference to material on chip.
A kind of its method for packing of the two-side radiation semiconductor provided in the embodiment of the present invention one, is first passed through in the upper of chip Lower surface is used with the combination material for including the isometrical bead of high temperature resistance, is come the accurate lead frame controlled before encapsulation, chip and is dissipated The integral thickness of backing, is then packaged again so that semiconductor will not damage chip by pressure and not result in partly in encapsulation process Conductor encapsulates excessive glue, improves the package quality of product, further increases the integral heat sink performance of product.
Wherein, the top surface of the bottom surface of the chip carrier and the fin exposes to the colloid.Chip carrier bottom surface and The top surface of fin is not coated by colloid, can be carried out heat exchange with the external world in time, be radiated, enhance semiconductor The heat dispersion of device.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art it is various it is obvious change, Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.

Claims (6)

1. a kind of two-side radiation semiconductor package structure, it is characterised in that including:
Lead frame, the lead frame includes chip carrier, interior pin and outer pin;
First combines material, and described first is located on the chip carrier with reference to material;
Chip, the chip is located at described first and combined on material;
Second combines material, and described second is located on the chip with reference to material;
Fin, the fin is located at described second and combined on material;
Colloid, the colloid cladding and the lead frame, the chip and the fin;
Described first is combined material with reference to material with described second includes the isometrical bead of high temperature resistance.
2. encapsulating structure according to claim 1, it is characterised in that the chip has relative acting surface and non-active Face, the non-active face of the chip passes through the first upper surface that the chip carrier is bonded in reference to material, the acting surface of the chip Pass through the second lower surface that the fin is bonded in reference to material.
3. encapsulating structure according to claim 2, it is characterised in that electronics group is provided with the acting surface of the chip Electronic building brick is not provided with part, the non-active face of the chip.
4. encapsulating structure according to claim 1, it is characterised in that the bottom surface of the chip carrier and the top of the fin Face exposes to the colloid.
5. a kind of two-side radiation method for packing semiconductor, it is characterised in that including:
Prepare lead frame:The lead frame includes chip carrier, interior pin and outer pin;
Welding chip:Using first with reference to material on the chip carrier welding chip;
Chip welds fin:The fin and the chip are welded with reference to material using second;
Baking:The lead frame of the fin will be welded, be sent directly into oven cooking cycle, material is combined after baking and is solidified, Jin Erban Conductor whole height is determined;
Injection molding:A glued membrane is sticked at the lead frame back side, mold-closing injection is carried out using colloid;
Described first is combined material with reference to material with described second includes the isometrical bead of high temperature resistance.
6. method for packing according to claim 5, it is characterised in that the bottom surface of the chip carrier and the top of the fin Face exposes to the colloid.
CN201410822723.XA 2014-12-25 2014-12-25 A kind of two-side radiation semiconductor package structure and its method for packing Active CN104600041B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410822723.XA CN104600041B (en) 2014-12-25 2014-12-25 A kind of two-side radiation semiconductor package structure and its method for packing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410822723.XA CN104600041B (en) 2014-12-25 2014-12-25 A kind of two-side radiation semiconductor package structure and its method for packing

Publications (2)

Publication Number Publication Date
CN104600041A CN104600041A (en) 2015-05-06
CN104600041B true CN104600041B (en) 2017-10-24

Family

ID=53125719

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410822723.XA Active CN104600041B (en) 2014-12-25 2014-12-25 A kind of two-side radiation semiconductor package structure and its method for packing

Country Status (1)

Country Link
CN (1) CN104600041B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105762084B (en) * 2016-04-29 2020-11-13 通富微电子股份有限公司 Packaging method and packaging device of flip chip
CN105914155A (en) * 2016-04-29 2016-08-31 南通富士通微电子股份有限公司 Flip chip and package method thereof
CN110875266A (en) * 2018-08-30 2020-03-10 广东威灵汽车部件有限公司 Connection structure of semiconductor wafer
CN114883279B (en) * 2022-07-12 2022-10-25 深圳市冠禹半导体有限公司 Packaging method of gallium nitride device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308827A (en) * 2007-05-18 2008-11-19 矽品精密工业股份有限公司 Cooling type semiconductor package
CN101752327A (en) * 2008-12-01 2010-06-23 矽品精密工业股份有限公司 Semiconductor packaging piece with heat dissipation structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102031731B1 (en) * 2012-12-18 2019-10-14 삼성전자주식회사 Semiconductor package and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308827A (en) * 2007-05-18 2008-11-19 矽品精密工业股份有限公司 Cooling type semiconductor package
CN101752327A (en) * 2008-12-01 2010-06-23 矽品精密工业股份有限公司 Semiconductor packaging piece with heat dissipation structure

Also Published As

Publication number Publication date
CN104600041A (en) 2015-05-06

Similar Documents

Publication Publication Date Title
CN104600041B (en) A kind of two-side radiation semiconductor package structure and its method for packing
CN107742630A (en) Image sensor packaging structure
CN104241218A (en) Flip chip plastic package structure with cooling structure and manufacturing method
CN105489509A (en) Optical sensing chip package method for optimizing coating process by applying metal stencil printing technology
CN103943763B (en) A kind of encapsulating structure and method of flip LED chips
CN103390564A (en) Film based IC packaging method and packaged IC device
CN107275459A (en) Potted element and its manufacture method
CN106158783B (en) Radiator fin device with anti-overflow plastic structure
CN104900612B (en) A kind of packaging body with umbilicate type cooling fin fin base stacks radiator structure and preparation method thereof
CN103022327B (en) LED encapsulation structure and preparation method thereof
CN206505948U (en) The sheet-shaped LED device and its display screen of a kind of high moisture
CN206921851U (en) The LED encapsulation structure of anti-vulcanization
CN109671834A (en) A kind of the LED chip CSP encapsulating structure and its packaging method of two-sided light out
CN207868224U (en) A kind of more glasss of LED COB display screen modules
CN207183254U (en) A kind of encapsulating structure of raising BGA product reliability
CN214477382U (en) Temperature sensor packaging structure of pressfitting of three-layer lamination
CN104051373B (en) Heat dissipation structure and manufacturing method of semiconductor package
CN104599983B (en) A kind of semiconductor devices prevents the method for packing of excessive glue
TWI359481B (en) Sensor semiconductor package and method thereof
CN103456649A (en) Method for encapsulating semiconductors
CN106952990A (en) A kind of chip-scale LED package device and its manufacture craft
US20090191669A1 (en) Method of encapsulating an electronic component
CN207183224U (en) Heat block and with its heater, compacting heating component
CN204464271U (en) Packaging body integrated circuit structure
CN206003765U (en) High density SIP encapsulating structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant