CN104599957B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, and the preparation method of the semiconductor devices comprises at least：Silicon substrate is provided, the silicon substrate includes first surface and second surface on the other side；III-V compound layer is formed on the first surface of the silicon substrate；III-V compound devices are prepared in the III-V compound layer；Technique is performed etching to the second surface of the silicon substrate, to form the groove for exposing the III-V compound layer in the silicon substrate, and the groove is located at the lower section of the III-V compound devices；The III-V compound layer injection strong electronegativity ion exposed using ion implantation technology to the channel bottom；Passivation layer is formed in the channel bottom and inwall.The semiconductor devices that technical scheme provides obtains higher breakdown voltage, realizes the production of the III-V compound devices based on silicon substrate.
Description
Technical field
The present invention relates to a kind of semiconductor technology, more particularly to a kind of semiconductor devices and preparation method thereof.
Background technology
In general, the HFET in conventional art（HEMT）As shown in figure 1, including being formed in silicon substrate
The first semiconductor layer 200, the second semiconductor layer 400, source electrode 320, drain electrode 310 and grid 330 on 100.Described the first half lead
Body layer 200 and second semiconductor layer 400 form hetero-junctions, two-dimensional electron gas be present at the heterojunction boundary.The source
Pole 310, drain electrode 320 and grid 330 are metal, and the source electrode 310, drain electrode 320 are located at the both ends of the second semiconductor layer 400,
And Ohmic contact is formed with first semiconductor layer 200, the grid 330 is located on second semiconductor layer 400, with institute
State the second semiconductor layer 400 and form Schottky contacts.When HFET works, by under control gate 330
Schottky barrier controls the concentration of the two-dimensional electron gas, so as to realizing the control to electric current.First semiconductor layer 200
It is iii v compound semiconductor layer with second semiconductor layer 400.In general, the first semiconductor layer 200 are GaN,
Second semiconductor layer 400 is AlGaN, and both form AlGaN/GaN hetero-junctions.
It is highly difficult due to directly producing iii v compound semiconductor substrate, it is currently based on iii v compound semiconductor
In the manufacture craft of electronic power components, epitaxial layer of gallium nitride is grown on substrate base by general use, then in the nitridation
The mode of electronic device is made on gallium epitaxial layer.The material of these substrate bases has Si, SiC, sapphire（Sapphire）Or GaN
（Bulk GaN, body GaN）Deng.
Wherein, because GaN growth in silicon substrate has the advantages such as large scale, low cost, especially suitable for power electronic
Device application.However, compared to SiC, sapphire（Sapphire）Or GaN（Bulk GaN, body GaN）, silicon substrate is particularly low
Resistance silicon substrate has the characteristics of resistivity is low, electric leakage is high.Therefore when epitaxial layer of gallium nitride grows on a silicon substrate, prepared thereon
HFET（HEMT）, Schottky diode（SBD）It can be leaked Deng transversal device because flowing through the longitudinal direction of silicon substrate
Electricity and can not have very high breakdown voltage.Thus, super-pressure at present（>2000V）The making side of gallium nitride power electronic device
Formula is concentrated mainly on is grown in SiC substrate or mode by GaN growth on a sapphire substrate by GaN epitaxial layer, also without will
GaN epitaxial layer growth is applied on a si substrate, limits the popularization of gallium nitride power electronic device.
In order to solve this problem, the method that U.S. HRL laboratories propose backplate, as shown in Figure 2.In this device
Silicon substrate under drift region is cut through, and overleaf cut through region deposit back metal electrode be connected to source electrode, physically every
The passage of silicon substrate electric leakage absolutely.However, the longitudinal direction electric leakage that this backplate have also been introduced from backplate to drain electrode simultaneously is logical
Road, objectively the backplate of well conducting instead of semiconductive silicon substrate, the breakdown voltage of its device substantially can not
Higher than longitudinal breakdown voltage of the common device for forming device in GaN epitaxial layer on a si substrate.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of making side of semiconductor devices
Method, for solving that III-V compound devices are not produced on to also the III-V compound layer based on silicon substrate in the prior art
The problem of middle.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of semiconductor devices, described
The preparation method of semiconductor devices comprises at least：
Silicon substrate is provided, the silicon substrate includes first surface and second surface on the other side；
III-V compound layer is formed on the first surface of the silicon substrate；
III-V compound devices are prepared in the III-V compound layer；
Technique is performed etching to the second surface of the silicon substrate, exposes described 35 to be formed in the silicon substrate
The groove of compounds of group layer, and the groove is located at the lower section of the III-V compound devices；
The III-V compound layer injection strong electronegativity exposed using ion implantation technology to the channel bottom
Ion；
Passivation layer is formed in the channel bottom and inwall.
Preferably, the groove only exposes the area where III-V compound devices described in the III-V compound layer
Domain.
Preferably, the element for ion being injected in the ion implantation technology is O or F, implantation dosage 1e18cm-3~
1e20cm-3, Implantation Energy is more than or equal to 50keV.
Preferably, it is described to include in the step of formation III-V compound layer on the first surface of the silicon substrate：
Using depositing operation GaN layer is formed on the silicon substrate；
AlGaN layer is formed in the GaN layer or formed using depositing operation in the GaN layer using depositing operation
InAIN layer.
Preferably, it is described also to include after the step of channel bottom and inwall form passivation layer：In the passivation
Highly thermally conductive property dielectric layer is formed on layer extremely to fill up the groove.
Preferably, after described the step of preparing semiconductor devices in the III-V compound layer, to the silicon
Before the step of second surface of substrate performs etching technique, in addition on the semiconductor devices formed Metal field plate step
Suddenly.
Accordingly, technical scheme additionally provides a kind of semiconductor devices, and the semiconductor devices comprises at least：
Silicon substrate, including first surface and second surface on the other side；
III-V compound layer, on the first surface of the silicon substrate, including III-V chemical combination formed therein
Sundries part；
Wherein, groove is also formed with the silicon substrate, the groove is located at the lower section of the III-V compound devices,
And the III-V compound layer is exposed, born in the top layer for the III-V compound layer that the groove exposes formed with forceful electric power
Property ion；The bottom of the groove and inwall are formed with passivation layer.
Preferably, the region of III-V compound layer where the groove only exposes the III-V compound devices.
Preferably, the step of III-V compound layer includes：
GaN layer on the silicon substrate；
AlGaN layer in the GaN layer or the InAIN layer in the GaN layer.
Preferably, the III-V compound devices are hetero junction field effect pipe and Schottky diode.
Preferably, in the trench, highly thermally conductive property dielectric layer is also formed with the passivation layer, the highly thermally conductive property is situated between
Matter layer fills up the groove.
Preferably, the depth of strong electronegativity ion implanted layer is 200nm.
As described above, the preparation method of the semiconductor devices of the present invention, has the advantages that：
The III-V compound layer is exposed by performing etching technique to the second surface of the silicon substrate, is recycled
The III-V compound layer injection strong electronegativity ion that ion implantation technology exposes to the channel bottom so that these
Ion can give the GaN back sides to introduce fixed negative electrical charge, so as to compensate the spontaneous influence intensified of gallium nitride, form a floor height electronics
The back side isolated layer of potential barrier.It so can effectively completely cut off the longitudinal direction electric leakage for flowing through the GaN back sides, so as to obtain high breakdown voltage.
Brief description of the drawings
Fig. 1 is shown as the structural representation of the HFET in conventional art.
The HFET on a silicon substrate that Fig. 2 is shown as in conventional art forms the signal of backplate
Figure.
Fig. 3 is shown as the flow chart of the preparation method of the semiconductor devices provided in technical scheme.
Fig. 4 to Figure 13 is shown as the schematic diagram of the formation field-effect transistor provided in embodiment one.
Figure 14 to Figure 23 is shown as the schematic diagram of the formation Schottky diode provided in embodiment two.
Figure 24 to Figure 28 is shown as carrying out device performance contrast to the semiconductor devices provided in technical scheme
Simulation schematic diagram.
Component label instructions
100 silicon substrates
200 first semiconductor layers
201 two-dimensional electron gas
310 drain electrodes
320 source electrodes
330 grids
400 second semiconductor layers
11 AlGaN layers
12 GaN layers
13 silicon substrates
14 source electrodes
15 drain electrodes
16 gate dielectric layers
17 gate electrode layers
18 first passivation layers
19 Metal field plates
20 strong electronegativity sheaths
21 second passivation layers
22 highly thermally conductive property insulating barriers
24 negative electrodes
27 positive electrodes
S10~S70 steps
Embodiment
For convenience of description, first the vocabulary that this specification is related to is annotated.In this specification, relative words contain
Justice is defined by annotating herein.
Iii v compound semiconductor：The semiconductor for the compound being combined into for group iii elements and group-v element.As Ga,
In, Al etc. belong to group iii elements；As, N etc. belong to group-v element.For example GaN, AlN, InN, GaAs, AlAs etc. belong to three or five
Compound semiconductor.
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 3.It should be noted that the diagram provided in the present embodiment only illustrates the present invention's in a schematic way
Basic conception, the component relevant with the present invention is only shown in schema then rather than according to component count during actual implement, shape
And size is drawn, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout
Kenel may also be increasingly complex.
The preparation method of the semiconductor devices provided in the present embodiment comprises at least：
First, step S10 is performed：Silicon substrate is provided, the silicon substrate includes first surface and the second table on the other side
Face；
Next, perform step S20：III-V compound layer is formed on the first surface of the silicon substrate；
Next, perform step S30：III-V compound devices are prepared in the III-V compound layer；
Next, perform step S40：Technique is performed etching to the second surface of the silicon substrate, with the silicon substrate
It is middle to form the groove for exposing the III-V compound layer, and the groove is located under the III-V compound devices
Side；
Next, perform step S50：The III-V exposed using ion implantation technology to the channel bottom
Compound layer injects strong electronegativity ion；
Next, perform step S60：Passivation layer is formed in the channel bottom and inwall.
Next, perform step S70：Highly thermally conductive property dielectric layer is formed on the passivation layer extremely to fill up the groove.
Wherein, after channel bottom injects strong electronegativity ion, the lower surface of III-V compound layer can be given to introduce admittedly
Fixed negative electrical charge, so as to compensate the spontaneous influence intensified of gallium nitride, the back side isolated layer of a floor height electronic barrier is formed, effectively
The longitudinal direction electric leakage of III-V compound layer is flowed through in isolation, so as to the semiconductor devices provided in technical scheme obtain compared with
High breakdown voltage, realize the production of the III-V compound devices based on silicon substrate.
Accordingly, technical scheme additionally provides the semiconductor devices that above-mentioned preparation method is formed, described partly to lead
Body device comprises at least：
Silicon substrate, including first surface and second surface on the other side；III-V compound layer, positioned at the silicon substrate
First surface on, including III-V compound devices formed therein；Wherein, groove is also formed with the silicon substrate,
The groove is located at the lower section of the III-V compound devices, and exposes the III-V compound layer, and the groove is sudden and violent
Formed with strong electronegativity ion in the top layer of the III-V compound layer exposed；The bottom of the groove and inwall are formed with passivation
Layer.
Specifically, elaborate the situation of technical scheme provided by the invention below with two embodiments.
Embodiment one
In the present embodiment, to form the field-effect transistor of III-V compound in the III-V compound layer
（HEMT）Exemplified by.
First, with reference to shown in Fig. 3, with reference to figure 4, there is provided silicon substrate 13, the surface of silicon substrate 13 is formed with III-V
Compound layer.
The silicon substrate 13 includes being located at first surface and corresponding second surface.The first surface is upper table
Face.
The III-V compound layer forms the first surface in the silicon substrate 13.In the present embodiment, the III-V
Compound layer includes AlGaN layer 11 and GaN layer 12, and both form AlGaN/GaN hetero-junctions.Those skilled in the art can understand
, AlGaN/GaN hetero-junctions is the current most important and most basic material system for making HEMT.Wherein, due to III-V
Compound has larger piezoelectric modulus（AlN and GaN piezoelectric modulus is 8.9 and 8.5）, meanwhile, the crystalline substance between AlN and GaN
Lattice mismatch is 2.5%, and big piezoelectric modulus and lattice mismatch cause have a very strong piezoelectricity to intensify between GaN and AlGaN layer
Effect.On the other hand, III-V compound has low symmetrical crystal structure, and this make it that also there is very strong in AlGaN layer
Spontaneous intensify effect.It is spontaneous to intensify effect and piezoelectricity intensifies effect and is mutually reinforcing, this cause in AlGaN layer intensifying it is strong
Degree can reach the MV/cm orders of magnitude.Further, since conduction band discontinuity big at AlGaN/GaN heterostructure interfaces, there is provided one
Very deep SQW and the very 2DEG of high concentration, it is higher by an order of magnitude than traditional AlGaAs/GaAs systems.
In other embodiments, the III-V compound layer can also be other III-V compounds and III-V
The combination of compound layer.Such as the InAIN layer in GaN layer and GaN layer.
The generation type of the III-V compound layer is deposition.
Next, with reference to shown in Fig. 3, with reference to figure 5, formed using etching technics in the AlGaN layer 11 and GaN layer 12
Opening.The source electrode and the position of drain electrode that the position of the opening is the HEMT.
In the present embodiment, the etching technics includes, and forms photoresist layer in the AlGaN layer 11, shows through overexposure
Shadow, the photoetching offset plate figure of source electrode and drain electrode is formed on the photoresist layer, then utilize the photoresist with source electrode and drain electrode
The photoresist of figure is as mask, using Cl2/ Ar carries out dry etching as etching gas, progress inductively coupled plasma,
Opening is formed in the AlGaN layer 11 and GaN layer 12.
Next, with reference to shown in Fig. 3, with reference to figure 6, metal is formed in said opening, to be formed Europe with the GaN layer 12
Nurse contacts, and forms source electrode 14 and the drain electrode 15 of the HEMT.Wherein, the metal be generally the metals such as Ti, Al, Ni, Au or
Metal composites.
Next, with reference to shown in Fig. 3, with reference to figure 7, institute is formed in the GaN layer 12 between the source electrode 14 and drain electrode 15
State HEMT grid.The grid includes gate dielectric layer 16 and gate electrode layer 17.The grid and GaN layer 12 form schottky junctions
Touch.The material of the gate electrode layer 17 is metal or the metal composites such as Ti, Au, Pd, Ni, Cr or Pt.Gate dielectric layer 16 can
For Al2O3, HfO2, SiN etc..
Next, with reference to shown in Fig. 3, with reference to figure 8, first is formed in the AlGaN layer 11 and the gate electrode layer 17
Passivation layer 18, the material of first passivation layer 18 is silica, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be heavy
Product or backflow.First passivation layer 18 exposes the source electrode 14 and drain electrode 15.First passivation layer 18 act as protecting
AlGaN layer surface, reduce surface defect electric charge.
Next, with reference to shown in Fig. 3, with reference to figure 9, the Metal field plate 19 of the HEMT is formed.The Metal field plate 19 wraps
Include and drawn from the surface of source electrode 14, is covered in across grid on the first passivation layer 18 between grid and drain electrode 15.The metal field
Plate 19 can between smooth grid leak Electric Field Distribution effect, improve device stability and resistance to pressure energy with reference to first passivation layer 18
Power.Metal field plate material can be metal or the metal composites such as Ti, Al, Ni or Au.With the Metal field plate principle in silicon device
Similar, source bias can be incorporated into above passivation layer by the Metal field plate, with the conducting channel below smooth passivation layer
Electric Field Distribution, to improve the pressure-resistant of device.
Next, with reference to shown in Fig. 3, with reference to figure 10, technique is performed etching to the silicon substrate 12, with the silicon substrate
The groove for exposing the III-V compound layer is formed in 12, and the groove is located at region between source electrode 14 and drain electrode 15
Underface, size are no more than the source electrode 14 and drain electrode and 15 are advisable to cover region between source electrode 14 and drain electrode 15.
If region is staggered between the groove and source electrode 14 and drain electrode 15 or area is too small, it can weaken in the present embodiment and carry
The voltage endurance capability final HEMT of confession, if if the groove, which crosses conference, influences chip mechanical strength.Position is with device effective district
The positive back side in domain is defined, and cuts through backing material and exposes GaN epitaxial layer.Etching technics can use dry or wet etch silicon to serve as a contrast
Bottom.
Next, with reference to shown in Fig. 3, with reference to figure 11, the institute exposed using ion implantation technology to the channel bottom
III-V compound layer ion implanting is stated, forms strong electronegativity sheath 20；
The element that ion is injected in the ion implantation technology is O or F, implantation dosage 1e18cm-3~1e20cm-3, note
Enter energy and be more than or equal to 50keV.
These fluorine or oxonium ion can give the GaN back sides to introduce fixed negative electrical charge, so as to compensate the spontaneous shadows intensified of GaN
Ring, form the back side isolated layer of a floor height electronic barrier.It so can effectively completely cut off the longitudinal direction electric leakage for flowing through the GaN back sides, so as to obtain
Obtain high breakdown voltage.
Next, with reference to shown in Fig. 3, with reference to figure 12, the second passivation layer 21 is formed in the channel bottom and inwall.It is described
The material of second passivation layer 21 is silica, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be deposition or backflow.
Next, with reference to shown in Fig. 3, with reference to figure 13, highly thermally conductive property dielectric layer is formed on the passivation layer to by described in
Groove fills up, to improve the radiating effect of device.The highly thermally conductive property insulating barrier 22 is beryllium oxide.
Accordingly, the present embodiment also includes the semiconductor devices that above-mentioned technical process is formed（It is named as in this specification
BIHEMT）, comprise at least：
Silicon substrate 13, including first surface and second surface on the other side；
III-V compound layer 12, on the first surface of the silicon substrate 13, including hetero-junctions formed therein
FET（HEMT）；Wherein, the III-V compound layer 12 includes：GaN layer on the silicon substrate 13；Positioned at institute
State the AlGaN layer in GaN layer or the InAIN layer in the GaN layer.
Wherein, groove is also formed with the silicon substrate 13, the groove is located at the lower section of the HEMT, and exposes institute
III-V compound layer 12 is stated, formed with strong electronegativity ion in the top layer for the III-V compound layer 12 that the groove exposes
Layer 20；The bottom of the groove and inwall are formed with passivation layer 21.The depth of the strong electronegativity ion implanted layer 20 is
200nm.The BIHEMT also includes forming the source electrode 14 in the HEMT in the AlGaN layer 11 and GaN layer 12 and drain electrode 15.
Wherein, the groove only exposes the region of the III-V compound layer where the HEMT.Specifically, the groove
The underface in region, size are not surpassed with covering region between source electrode 14 and drain electrode 15 between source electrode 14 and drain electrode 15
Crossing the source electrode 14 and drain electrode 15 is advisable.If region is staggered between the groove and source electrode 14 and drain electrode 15 or area is too small,
The final voltage endurance capabilities of the BIHEMT provided in the present embodiment can be weakened, if if the groove, which crosses conference, influences chip machinery by force
Degree.Position cuts through backing material and exposes GaN epitaxial layer to be defined at the positive back side in device effective coverage.In the trench,
Highly thermally conductive property dielectric layer 22 is also formed with the passivation layer, the highly thermally conductive property dielectric layer 22 fills up the groove.The height
Thermal conductance insulating barrier 22 is beryllium oxide.
Embodiment two
In the present embodiment, to form Schottky diode in the III-V compound layer（SBD）Exemplified by.
First, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 14, there is provided silicon substrate 13, shape on the silicon substrate 13
Into there is III-V compound layer.The III-V compound layer forms the first surface in the silicon substrate 13.In the present embodiment,
The III-V compound layer includes AlGaN layer 11 and GaN layer 12, in other embodiments, the III-V compound layer
It can also be the combination of other III-V compounds and III-V compound layer.Such as the InAlN in GaN layer and upper GaN layer
Layer.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 15, using etching technics in the AlGaN layer 11
It is open with being formed in GaN layer 12.The position of the opening is the electrode of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 16, forms metal in said opening, with institute
State GaN layer 12 and form Ohmic contact, form the negative electrode 24 of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 17, in one end away from the negative electrode 24
Metal is formed in GaN layer 12, to be formed Schottky contacts with the GaN layer 12, forms the positive electrode 27 of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 18, forms the first passivation in the GaN layer 12
Layer 18.The both ends of first passivation layer 18 also partly cover the negative electrode 24 and positive electrode 27 of the SBD.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 19, is not covered in first passivation layer 18
SBD negative electrode 24 and the Metal field plate 19 that negative electrode 24 is formed in the GaN layer of negative electrode 24, and it is blunt described first
The Metal field plate 19 of positive electrode 27 is formed on the SBD positive electrodes 27 and the GaN layer of close positive electrode 27 that change layer 18 does not cover.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 20, work is being performed etching to the silicon substrate 12
Skill, to form the groove for exposing the III-V compound layer in the silicon substrate 12, and the groove is located at negative electrode
The underface in region between 24 and positive electrode 27, size are no more than with covering region between negative electrode 24 and positive electrode 27
The negative electrode 24 and positive electrode 27 are advisable.
Similar embodiment one, if region is staggered between the groove and negative electrode 24 and positive electrode 27 or area is too small,
The final voltage endurance capabilities of the SBD provided in the present embodiment can be weakened, if if the groove, which crosses conference, influences chip mechanical strength.Position
Put to be defined at the positive back side in device effective coverage, cut through backing material and expose GaN epitaxial layer.Etching technics can use dry
Method or wet etching silicon substrate.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 21, is utilizing ion implantation technology to the groove
The III-V compound layer injection strong electronegativity ion that bottom-exposed goes out；
The element that ion is injected in the ion implantation technology is O or F, implantation dosage 1e18cm-3~1e20cm-3, note
Enter energy and be more than or equal to 50keV.
These fluorine or oxonium ion can give the GaN back sides to introduce fixed negative electrical charge, so as to compensate the spontaneous shadows intensified of GaN
Ring, form the back side isolated layer of a floor height electronic barrier.It so can effectively completely cut off the longitudinal direction electric leakage for flowing through the GaN back sides, so as to obtain
Obtain high breakdown voltage.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 22, second is formed in the channel bottom and inwall
Passivation layer 21.The material of second passivation layer 21 is silica, boron-phosphorosilicate glass, silicon nitride etc..Generation type can be heavy
Product or backflow.
Next, similar embodiment one, with reference to shown in Fig. 3, with reference to figure 23, forms highly thermally conductive property on the passivation layer and is situated between
Matter layer is to the groove is filled up, to improve the radiating effect of device.The highly thermally conductive property insulating barrier 22 is beryllium oxide.
Accordingly, with continued reference to shown in Figure 23, the present embodiment also includes the semiconductor devices that above-mentioned technical process is formed（This
BISBD is named as in specification）, comprise at least：
Silicon substrate 13, including first surface and second surface on the other side；
III-V compound layer 12, on the first surface of the silicon substrate 13, including Schottky formed therein
Diode（SBD）；Wherein, the III-V compound layer 12 includes：GaN layer on the silicon substrate 13；Positioned at described
AlGaN layer in GaN layer or the InAIN layer in the GaN layer.The Schottky diode also includes being formed described
The positive electrode 27 and negative electrode 24 of the SBD in AlGaN layer 11 and GaN layer 12.
Wherein, groove is also formed with the silicon substrate 13, the groove is located at the lower section of the SBD, and exposes institute
III-V compound layer 12 is stated, formed with strong electronegativity ion in the top layer for the III-V compound layer 12 that the groove exposes
Layer 20；The bottom of the groove and inwall are formed with passivation layer 21.The depth of the strong electronegativity ion implanted layer 20 is
200nm。
Wherein, the underface in groove region between negative electrode 24 and positive electrode 27, size is to cover negative electrode
Region between 24 and positive electrode 27, but be no more than the negative electrode 24 and positive electrode 27 and be advisable.Similar embodiment one, the ditch
If region is staggered between groove and negative electrode 24 and positive electrode 27 or area is too small, the BISBD provided in the present embodiment can be weakened
Final voltage endurance capability, if if the groove, which crosses conference, influences chip mechanical strength.Position is with the positive back side in device effective coverage
It is defined, cuts through backing material and expose GaN epitaxial layer.
In the trench, highly thermally conductive property dielectric layer 22, the highly thermally conductive property dielectric layer are also formed with the passivation layer
22 fill up the groove.The highly thermally conductive property insulating barrier 22 is beryllium oxide.
In addition, inventor in order to verify BIHEMT and BISBD device performance, uses Synopsys Sentaurus
TCAD softwares are to back-etching but are not injected into the device of strong electronegativity ion and BIHEMT/BISBD has carried out comparative simulation, specifically
Situation is as follows：
1. model structure
Each layer composition：
The material of passivation layer is SiN, thickness 200nm；
GaN layer includes GaN cap layers and GaN buffer layers, and the thickness of GaN cap layers is 4nm；GaN buffer layers
Thickness is 3 μm.
AlGaN layer thickness is 20nm；
At the back side of GaN buffer layers, BIHEMT/BISBD has 200nm strong electronegativity ion implanted layer.
2. analog result
Figure 24 show the shut-off leakage current characteristic for carrying out back-etching and injecting strong electronegativity ion BISBD（Off-state
I-V）Schematic diagram, in figure, abscissa is that diode both positive and negative polarity biases VA, unit kV；Ordinate is diode current IA, unit
For A/mm.Including the BISDB of following several different situations：Channel length is 10 μm, simulates obtained device breakdown voltage
For 1.4kV；Channel length is 20 μm, and simulation obtained device breakdown voltage is 4.1kV；Channel length is 30 μm, simulation gained device
Part breakdown voltage is 7.1kV；Channel length is 40 μm, and simulation obtained device breakdown voltage is 9.9kV；Channel length is 50 μm,
It is 12.8kV to simulate obtained device breakdown voltage.
Figure 25 show the shut-off leakage current characteristic for carrying out back-etching and injecting strong electronegativity ion BIHEMT（Off-
state I-V）Schematic diagram.Including the BIHEMT of following several different situations：Channel length is 10 μm, simulation gained device
Part breakdown voltage is 1.4kV；Channel length is 20 μm, and simulation obtained device breakdown voltage is 4.2kV；Channel length is 30 μm,
It is 7.1kV to simulate obtained device breakdown voltage；Channel length is 40 μm, and simulation obtained device breakdown voltage is 9.9kV；Raceway groove is grown
Spend for 50 μm, simulation obtained device breakdown voltage is 12.8kV.
It is visible in Figure 24 and Figure 25, carried out back-etching and strong electronegativity ion implanting isolation after, BISBD and
BIHEMT breakdown voltage increases with the growth of channel length, is not limited by GaN-on-Si chips longitudinal direction breakdown voltage（Its
In, chip longitudinal direction breakdown voltage is limited by GaN buffer thickness degree, is herein 3 μm）.When channel length is 50 microns, its
Breakdown voltage can be more than 10,000 volts.
After Figure 26 show progress back-etching, inject strong electronegativity ion and be not injected into strong electronegativity ion BISBD's
Turn off leakage current characteristic（Off-state I-V）Comparison figure.Including the BISDB of following several different situations：Raceway groove is grown
Spend for 10 μm, be not injected into strong electronegativity ion implanting, simulation obtained device breakdown voltage is 800V；Channel length is 10 μm, note
Enter strong electronegativity ion, simulation obtained device breakdown voltage is 1.4kV；Channel length is 50 μm, is not injected into strong electronegativity ion
Injection, simulation obtained device breakdown voltage are what 800V is；Channel length is 50 μm, injects strong electronegativity ion, simulates institute
It is 12.8kV to obtain device electric breakdown strength.
After Figure 27 show progress back-etching, inject strong electronegativity ion and be not injected into strong electronegativity ion BIHEMT's
Turn off leakage current characteristic（Off-state I-V）Comparison figure.Including the BISDB of following several different situations：Raceway groove is grown
Spend for 10 μm, be not injected into strong electronegativity ion implanting, simulation obtained device breakdown voltage is 800V；Channel length is 10 μm, note
Enter strong electronegativity ion, simulation obtained device breakdown voltage is 1.4kV；Channel length is 50 μm, is not injected into strong electronegativity ion
Injection, simulation obtained device breakdown voltage is 800V；Channel length is 50 μm, injects strong electronegativity ion, simulates obtained device
Breakdown voltage is 12.8kV.
It is visible in Figure 26 and Figure 27, if simply having carried out back-etching without doing the isolation of strong electronegativity ion implanting, no matter
It is the influence that the breakdown voltage of SBD or HEMT device all can longitudinally be punctured by GaN-on-Si chips, no matter how raceway groove increases
Long, its breakdown voltage is all limited in 800V or so.
After Figure 28 is carries out back-etching, injection strong electronegativity ion and the GaN hetero-junctions for being not injected into strong electronegativity ion
Conduction band diagram.On GaN-on-Si epitaxial structures, after back-etching is finished so as to expose GaN buffer layers, because
Exclusive spontaneous of gallium nitride material intensifies characteristic, its can be produced at the GaN buffer layers back side it is positive intensify electric charge, so as to drag down
The conduction band at the GaN back sides, form a back channel.So when device works, this back channel can help to flow through longitudinal electric leakage, shape
Into the effect similar to low-resistance silicon substrate.So back-etching is simply finished, even silicon substrate is eliminated, but because nitridation
Gallium spontaneous the reason for intensifying, still can not completely cut off to fall longitudinal electric leakage, and device electric breakdown strength is not helped.
But ought overleaf it inject after strong electronegativity ion, these ions can give the GaN back sides to introduce fixed negative electrical charge, from
And compensate the spontaneous influence intensified of gallium nitride, form the back side isolated layer of a floor height electronic barrier.It so can effectively completely cut off stream
The longitudinal direction electric leakage at the GaN back sides is crossed, so as to obtain high breakdown voltage.
In summary, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that the preparation method of the semiconductor devices comprises at least：
Silicon substrate is provided, the silicon substrate includes first surface and second surface on the other side；
III-V compound layer is formed on the first surface of the silicon substrate：Using depositing operation on the silicon substrate
Form GaN layer；AlGaN layer is formed in the GaN layer or formed using depositing operation in the GaN layer using depositing operation
InAIN layer；
III-V compound devices are prepared in the III-V compound layer；
Technique is performed etching to the second surface of the silicon substrate, exposes the GaN layer to be formed in the silicon substrate
Groove, and the groove is located at the lower section of the III-V compound devices；
The GaN layer exposed using ion implantation technology to the channel bottom injects strong electronegativity ion, with described
The GaN back sides introduce fixed negative electrical charge, so as to compensate the spontaneous influence intensified of GaN layer, form the back of the body of a floor height electronic barrier
Face separation layer；
Passivation layer is formed in the channel bottom and inwall.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that：The groove only exposes described three
Region described in five compounds of group layers where III-V compound devices.
3. the preparation method of semiconductor devices according to claim 1, it is characterised in that：Noted in the ion implantation technology
The element for entering ion is O or F, implantation dosage 1e18cm-3~1e20cm-3, Implantation Energy is more than or equal to 50keV.
4. the preparation method of semiconductor devices according to claim 1, it is characterised in that：In the channel bottom and inwall
Also include after the step of forming passivation layer：Highly thermally conductive property dielectric layer is formed on the passivation layer to fill up the groove.
5. the preparation method of semiconductor devices according to claim 1, it is characterised in that：In the III-V compound layer
In after the step of preparing semiconductor devices, before the step of performing etching technique to the second surface of the silicon substrate, also
It is included on the semiconductor devices the step of forming Metal field plate.
6. a kind of semiconductor devices, it is characterised in that the semiconductor devices comprises at least：
Silicon substrate, including first surface and second surface on the other side；
III-V compound layer, on the first surface of the silicon substrate, including III-V chemical combination sundries formed therein
Part；The III-V compound layer includes：GaN layer on the silicon substrate；AlGaN layer in the GaN layer or
InAIN layer in the GaN layer；
Wherein, groove is also formed with the silicon substrate, the groove is located at the lower section of the III-V compound devices, and cruelly
Expose the GaN layer, formed with strong electronegativity ion in the bottom skin for the GaN layer that the groove exposes；
The bottom of the groove and inwall are formed with passivation layer.
7. semiconductor devices according to claim 6, it is characterised in that：The groove only exposes the III-V compound
The region of III-V compound layer where device.
8. semiconductor devices according to claim 6, it is characterised in that：The III-V compound devices are heterojunction field
Effect pipe and Schottky diode.
9. semiconductor devices according to claim 6, it is characterised in that：In the trench, shape is gone back on the passivation layer
Into there is highly thermally conductive property dielectric layer, the highly thermally conductive property dielectric layer fills up the groove.
10. semiconductor devices according to claim 6, it is characterised in that：The depth of strong electronegativity ion implanted layer is
200nm。
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| DE10160604A1 (en) * | 2001-12-10 | 2003-06-26 | Infineon Technologies Ag | Production of a cooling recess in a semiconductor product comprises preparing a semiconductor substrate, forming a mask on the rear side of the substrate, wet chemical etching the rear side, removing the mask |
| CN101336482A (en) * | 2005-11-29 | 2008-12-31 | 香港科技大学 | Low density drain hemts |
| CN102401840A (en) * | 2011-11-14 | 2012-04-04 | 中北大学 | Si based HEMT embedded micro accelerator and production method thereof |
| CN102856369A (en) * | 2012-09-03 | 2013-01-02 | 南京邮电大学 | Suspended HEMT (high electron mobility transistor) device based on silicon substrate nitride and preparation method of suspended HEMT device |
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| DE10160604A1 (en) * | 2001-12-10 | 2003-06-26 | Infineon Technologies Ag | Production of a cooling recess in a semiconductor product comprises preparing a semiconductor substrate, forming a mask on the rear side of the substrate, wet chemical etching the rear side, removing the mask |
| CN101336482A (en) * | 2005-11-29 | 2008-12-31 | 香港科技大学 | Low density drain hemts |
| CN102401840A (en) * | 2011-11-14 | 2012-04-04 | 中北大学 | Si based HEMT embedded micro accelerator and production method thereof |
| CN102856369A (en) * | 2012-09-03 | 2013-01-02 | 南京邮电大学 | Suspended HEMT (high electron mobility transistor) device based on silicon substrate nitride and preparation method of suspended HEMT device |
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