CN104579623B - System and method during a kind of secondary equipment in power system network pair - Google Patents
System and method during a kind of secondary equipment in power system network pair Download PDFInfo
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- CN104579623B CN104579623B CN201410811331.3A CN201410811331A CN104579623B CN 104579623 B CN104579623 B CN 104579623B CN 201410811331 A CN201410811331 A CN 201410811331A CN 104579623 B CN104579623 B CN 104579623B
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Abstract
The invention discloses system and method during a kind of secondary equipment in power system network pair, it is characterised in that including CPU, FPGA, physical layer network card chip PHY, constant-temperature crystal oscillator OCXO；The CPU is connected with FPGA by PCIE buses；The FPGA is included by the FPGA Ethernet MAC controller MAC realized and hardware timestamping detection and generation module and phase-locked loop PLL；Inputted during by network pair, filtering packets and synchronization accuracy when improving message pair, hardware timestamping is added to message using FPGA, synchronization during network pair, the setting means exported during network pair, the present invention, can be under conditions of hardware configuration not be changed, when realizing the high-accuracy network pair of multichannel using relatively low cost using FPGA as core；Simultaneously by PLL phase-locked loops and capping in MII layers of hardware timestamping technology, precision when can also greatly improve network pair；Scalability is strong.
Description
Technical field
The present invention relates to system and method during a kind of secondary equipment in power system network pair, belong to power automation technology neck
Domain.
Background technology
In intelligent substation, when during synchronous pair of secondary device using starting from during pulsed logic pair to digitalized network pair
Transition, this is the necessity of intelligent substation total digitalization.Due to combining unit, PMU (phasor measurement lists in intelligent substation
Member) etc. secondary device for pair when precision and stability requirement it is very high, remaining secondary device is in order to improve sampling precision and side
Just crash analysis, to pair when required precision also can more and more higher.Therefore become that power system is secondary to be set during high-accuracy network pair
A standby basic function.
Mainly by external ready-made chip technology when realizing network pair in secondary equipment in power system at present, such as
DP83640；Such chip is physical chip, precision when can reach basic network pair, but chip is easily by temperature, electromagnetism
The external factor such as environment, network are disturbed and need making sheet again using such chip, and cost is too high, and scalability is poor, separate port
It is few, break the hardware environment of the original stabilization of ring.
Clockwork in secondary equipment of intelligent converting station is as originating end during network pair, and remaining secondary device is used as net
Receiving terminal during network pair, there is different application demands.Most secondary devices need to access two separate networks,
To receive signal during two road networks pair, then signal when secondary device must be correctly isolated and handle this two-way pair.And clock is set
It is standby then need to a large amount of separate networks send pair when signal, then the separate port quantity that clock apparatus can be exported must be significantly
Increase.
Best master clock algorithm is specify that in IEEE1588 specifications, the multichannel IEEE1588 that the algorithm can come from reception
Selected in message wherein all the way, the initiation source on Bing Jianggai roads is used as master clock source.There is notice message in IEEE1588 messages, lead to
Knowing inside message has precision field, time source field, precedence field and port information field.Best master clock algorithm can be first
Judge the precision field of each road message, precision field represents that message initiates the time service precision of source in itself, algorithm prioritizing selection precision
Highest initiates source；If precision is the same, then compares time source field, in China, Big Dipper source is prior to GPS sources；If time source one
Sample, then compare precedence field, and it refers to initiation source in the priority of whole system, the high initiation source of algorithms selection priority；
If above all, can be compared according to port information, because port information each initiates that source is different, algorithm can be according to port
Digital size sequential selection initiates source.
The content of the invention
To solve deficiency of the prior art, when the present invention provides a kind of secondary equipment in power system network pair system and its
Setting means, chip cost is high when solving pair, the separate port limited amount of secondary device input and output the problem of.
In order to realize above-mentioned target, the present invention is adopted the following technical scheme that：During a kind of secondary equipment in power system network pair
System, including CPU, FPGA, physical layer network card chip PHY, constant-temperature crystal oscillator OCXO；The CPU and FPGA is connected by PCIE buses
Connect；The FPGA includes detecting by the FPGA Ethernet MAC controller MAC realized and hardware timestamping and generation mould
Block and phase-locked loop PLL；The PHY is connected with MAC by GMII MII；The OCXO is connected with PLL, is FPGA
Clock signal is provided；The phase-locked loop PLL is used to eliminate distortion and delay that OCXO exports clock waveform；The hardware timeout
At the time of stamp detection and generation module enter the MII layers between MAC layer and PHY layer for capturing IEEE1588 messages.
System during a kind of foregoing secondary equipment in power system network pair, it is characterized in that：The MAC includes 8 transmission MAC
With 2 reception MAC；
System during a kind of foregoing secondary equipment in power system network pair, it is characterized in that：The OCXO frequencies are 20MHz,
The FPGA is by OCXO frequencies frequency multiplication to 100MHz so that hardware timestamping minimum resolution is improved to 10ns by 50ns.
System during a kind of foregoing secondary equipment in power system network pair, it is characterized in that：The CPU, which is used, to be not less than
The POWERPC frameworks of 266MHz dominant frequency or the CPU of ARM frameworks.
System during a kind of foregoing secondary equipment in power system network pair, it is characterized in that：The FPGA logic cell quantity
No less than 24000.
The setting means of system during based on a kind of any of the above-described secondary equipment in power system network pair, it is characterised in that：Bag
Include step：
1) inputted during network pair：IEEE1588 messages in outside two separate network passages pass sequentially through PHY layer and MII
Layer enters two of FPGA reception MAC, whether this two-way message is judged by CPU best master clock algorithm, if it is not, then FPGA
CPU is sent to by receiving MAC by the characteristic information of IEEE1588 messages, and CPU uses it by best master clock algorithms selection
In in a passage message initiation source as master clock, and inform that FPGA only receives the IEEE1588 messages in this passage；
2) filtering packets and synchronization accuracy when improving message pair：If IEEE1588 messages pass through best master clock algorithm
Calculating, then FPGA judge that the message in selected passage is that IEEE1588 messages are still the related report that secondary device needs to receive
Text；If association message, then selection is received, and otherwise abandons the message；Meanwhile, distort when the appearance of OCXO output waveforms or
When producing delay, FPGA exports clock signal as input clock signal to keep whole by the use of internal phase-locked loop PLL itself
Stable clock signal, until OCXO output signals recover stable；PLL power circuits use special insulating power supply circuit, make PLL's
Power supply is separated with bus power source；
3) hardware timestamping is added to message using FPGA：FPGA is detected by hardware timestamping and generation module is captured
At the time of IEEE1588 messages enter the MII layers between MAC layer and PHY layer, the timestamp at this moment is recorded；FPGA will
Obtained hardware timestamping is added to behind IEEE1588 messages, and by message by PCIE bus transfers to CPU；
4) synchronization during network pair：CPU is to step 3) transmission IEEE1588 messages using IEEE1588 standard techniques progress
Postpone calculations of offset and clock frequency amendment so that the internal clock frequencies of whole secondary device and IEEE1588 initiate source when
Clock Frequency Synchronization；After secondary device synchronization, CPU is built new IEEE1588 messages on the basis of itself clock frequency and sent again
To FPGA；
5) exported during network pair：FPGA simultaneously to eight send MAC output above-mentioned steps obtain pair when sync message, this
A little messages pass sequentially through MII layers again and PHY layer enters independent network channel.
A kind of foregoing secondary equipment in power system network setting means, it is characterized in that：Step 1) described in message characteristic
Information refers to precision field, time source field, precedence field and port information field in IEEE1588 messages.
A kind of foregoing secondary equipment in power system network setting means, it is characterized in that：Step 1) described in it is optimal main when
Clock algorithm is the characteristic information that CPU obtains two-way IEEE1588 messages, and according to priority orders comparative feature information one by one, directly
To wherein message all the way is chosen, the initiation source of Bing Jiangzhe roads message is used as master clock.
A kind of foregoing secondary equipment in power system network setting means, it is characterized in that：The association message sets to be secondary
The message that standby normal operation needs, including GOOSE message, SV messages.
The beneficial effect that the present invention is reached：The present invention can not change the condition of hardware configuration using FPGA as core
Under, when realizing the high-accuracy network pair of multichannel using relatively low cost；Simultaneously by PLL phase-locked loops and capping in MII
The hardware timestamping technology of layer, precision when can also greatly improve network pair；Present invention input separate port number can be defeated up to 2
Going out separate port number can be up to 8, and cost is low, scalability is strong, can be widely applied to the secondary of comprehensive automation system of transformer substation
Equipment.
Brief description of the drawings
System construction drawing when Fig. 1 is secondary equipment in power system network pair；
Fig. 2 is secondary equipment in power system network setting means flow chart.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
As shown in figure 1, system during a kind of secondary equipment in power system network pair, including CPU, FPGA, physical layer network interface card core
Piece PHY, constant-temperature crystal oscillator OCXO；The CPU is connected with FPGA by PCIE buses；The FPGA include by FPGA realization with
Too net MAC controller MAC and hardware timestamping detection and generation module and phase-locked loop PLL；The MAC includes 8 hairs
Send MAC and 2 reception MAC；The PHY is connected with MAC by GMII MII；The OCXO is connected with PLL, is
FPGA provides clock signal；The phase-locked loop PLL is used to eliminate distortion and delay that OCXO exports clock waveform；The hardware
, will at the time of timestamp is detected and generation module enters the MII layers between MAC layer and PHY layer for capturing IEEE1588 messages
The timestamp at this moment is recorded.
Outside constant-temperature crystal oscillator OCXO frequencies are 20MHz, and FPGA is by OCXO frequencies frequency multiplication to 100MHz so that hardware timestamping
Minimum resolution is improved to 10ns by 50ns, and then improves the synchronization accuracy of whole system.
CPU is using the POWERPC frameworks for being not less than 266MHz dominant frequency or the CPU of ARM frameworks.
FPGA logic cell quantity is no less than 24000, to ensure the structure of ten MAC inside FPGA.
As shown in Fig. 2 during based on a kind of above-mentioned secondary equipment in power system network pair system setting means, step bag
Include：
1) inputted during network pair：IEEE1588 messages in outside two separate network passages pass sequentially through PHY layer and MII
Layer enters two of FPGA reception MAC, whether this two-way message is judged by CPU best master clock algorithm, if it is not, then FPGA
CPU is sent to by receiving MAC by the characteristic information of IEEE1588 messages, and CPU uses it by best master clock algorithms selection
In in a passage message initiation source as master clock, and inform that FPGA only receives the IEEE1588 messages in this passage；
The message characteristic information refers to precision field, time source field, precedence field and port information in IEEE1588 messages
Field；
The best master clock algorithm is the characteristic information that CPU obtains two-way IEEE1588 messages, and according to characteristic information
Inside field priority orders comparative feature information one by one, until choosing wherein message, the initiation source of Bing Jiangzhe roads message all the way
It is used as master clock.
2) filtering packets and synchronization accuracy when improving message pair：If passing through the calculating of best master clock algorithm,
FPGA judges that the message in selected passage is that IEEE1588 messages are still the association message that secondary device needs to receive, such as
GOOSE message or SV messages；If association message, then selection is received, and otherwise abandons the message；Meanwhile, using in FPGA
Portion phase-locked loop PLL eliminates the distortion and delay of above-mentioned OCXO output waveforms, this be due to PLL when work, when PLL is defeated
Go out signal clock frequency and OCXO input to PLL clock frequency it is equal when, PLL output signal voltage is inputed to OCXO
PLL applied signal voltages keep fixed phase difference value, while PLL can also serve as the output signal of itself in alternative input letter
Number；When above-mentioned OCXO signal output waveforms occur distorting and postponed, voltage-phase difference starts significantly to change, and PLL will make
With itself output signal as input signal to keep whole stable clock signal, until above-mentioned OCXO output signals recover steady
It is fixed；Because bus power source is vulnerable to external disturbance, PLL power circuits use special insulating power supply circuit, make PLL power supply with it is total
Line power supply is separated, and increases reliability.
3) hardware timestamping is added to message using FPGA：FPGA is detected by hardware timestamping and generation module is captured
At the time of IEEE1588 messages enter the MII layers between MAC layer and PHY layer, the timestamp at this moment is recorded；FPGA will
Obtained hardware timestamping is added to behind IEEE1588 messages, and message is transferred into CPU by PCIE；
4) synchronization during network pair：CPU is to step 3) transmission IEEE1588 messages using IEEE1588 standard techniques progress
Postpone calculations of offset and clock frequency amendment so that the internal clock frequencies of whole secondary device and IEEE1588 initiate source when
Clock Frequency Synchronization；After secondary device synchronization, CPU is built new IEEE1588 messages on the basis of itself clock frequency and sent again
To FPGA；
5) exported during network pair：FPGA simultaneously to eight send MAC output above-mentioned steps obtain pair when sync message, this
A little messages pass sequentially through MII layers again and PHY layer enters independent network channel.
IEEE1588 standard gauges are scheduled in the realization of the Ethernet of IEEE1588 standards, the time mark point of clock sync message
Should be corresponding with primary forward position in the first character section after start of frame delimiter (SFD), which dictates that the synchronous essence of clock
Degree depends primarily on the precision of timestamp.The present invention is by the way of FPGA hardware capping timestamp, by timestamp capping in MAC
MII layers between layer and PHY layer, this mode can avoid the larger time jitter in protocol stack top, eliminate in message transmissions
Network delay, so as to obtain higher synchronization accuracy.Export, lead to when realizing eight road IEEE1588 networks pair using monolithic FPGA
The frequency crossed between FPGA control passages is consistent, and ensures there is independent transmission MAC per road port so that network output mouth
Isolate each other.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and deformed
Also it should be regarded as protection scope of the present invention.
Claims (9)
1. system during a kind of secondary equipment in power system network pair, including CPU, FPGA, physical layer network card chip PHY, constant temperature are brilliant
Shake OCXO；The CPU is connected with FPGA by PCIE buses；The FPGA includes the Ethernet media interviews realized by FPGA
Controller MAC and hardware timestamping detection and generation module and phase-locked loop PLL；The PHY and MAC passes through GMII
MII connections；The OCXO is connected with PLL, and clock signal is provided for FPGA；The phase-locked loop PLL is used to eliminate OCXO outputs
The distortion and delay of clock waveform；The hardware timestamping detection and generation module enter MAC for capturing IEEE1588 messages
Layer PHY layer between MII layers at the time of.
2. system during a kind of secondary equipment in power system network pair according to claim 1, it is characterized in that：The MAC bags
Include 8 and send MAC and 2 reception MAC.
3. system during a kind of secondary equipment in power system network pair according to claim 1, it is characterized in that：The OCXO frequencies
Rate is 20MHz, and the FPGA is by OCXO frequencies frequency multiplication to 100MHz so that hardware timestamping minimum resolution by 50ns improve to
10ns。
4. system during a kind of secondary equipment in power system network pair according to claim 1, it is characterized in that：The CPU is adopted
With the POWERPC frameworks or the CPU of ARM frameworks for being not less than 266MHz dominant frequency.
5. system during a kind of secondary equipment in power system network pair according to claim 1, it is characterized in that：The FPGA is patrolled
Collect element number and be no less than 24000.
6. the setting means of system during based on a kind of secondary equipment in power system network pair described in any of the above-described claim, its
It is characterised by：Including step：
1) inputted during network pair：IEEE1588 messages in outside two separate network passages pass sequentially through PHY layer and MII layers are entered
Enter two of FPGA reception MAC, whether this two-way message is judged by CPU best master clock algorithm, if it is not, then FPGA passes through
Receive MAC and send the characteristic information of IEEE1588 messages to CPU, CPU uses wherein one by best master clock algorithms selection
The initiation source of message is as master clock in individual passage, and informs that FPGA only receives the IEEE1588 messages in this passage；
2) filtering packets and synchronization accuracy when improving message pair：If IEEE1588 messages pass through the meter of best master clock algorithm
Calculate, then FPGA judges that the message in selected passage is that IEEE1588 messages are still the association message that secondary device needs to receive；
If association message, then selection is received, and otherwise abandons the message；Meanwhile, when distorting occur in OCXO output waveforms or produce
During delay, FPGA exports clock signal as input clock signal to keep whole clock by the use of internal phase-locked loop PLL itself
Signal stabilization, until OCXO output signals recover stable；PLL power circuits use special insulating power supply circuit, make PLL power supply
Separated with bus power source；
3) hardware timestamping is added to message using FPGA：FPGA is detected by hardware timestamping and generation module is captured
At the time of IEEE1588 messages enter the MII layers between MAC layer and PHY layer, the timestamp at this moment is recorded；FPGA will
Obtained hardware timestamping is added to behind IEEE1588 messages, and by message by PCIE bus transfers to CPU；
4) synchronization during network pair：CPU is to step 3) transmission IEEE1588 messages postponed using IEEE1588 standard techniques
Calculations of offset and clock frequency amendment so that the internal clock frequencies of whole secondary device initiate the clock frequency in source with IEEE1588
Rate is synchronous；After secondary device synchronization, CPU is built new IEEE1588 messages on the basis of itself clock frequency and is sent to again
FPGA；
5) exported during network pair：FPGA simultaneously to eight send MAC output above-mentioned steps obtain pair when sync message, these report
Text passes sequentially through MII layers again and PHY layer enters independent network channel.
7. the setting means of system during a kind of secondary equipment in power system network pair according to claim 6, it is characterized in that：
Step 1) described in message characteristic information refer to precision field in IEEE1588 messages, time source field, precedence field and
Port information field.
8. the setting means of system during a kind of secondary equipment in power system network pair according to claim 6, it is characterized in that：
Step 1) described in best master clock algorithm be characteristic information that CPU obtains two-way IEEE1588 messages, it is and suitable according to priority
Sequence comparative feature information one by one, until choosing wherein message all the way, the initiation source of Bing Jiangzhe roads message is used as master clock.
9. the setting means of system during a kind of secondary equipment in power system network pair according to claim 6, it is characterized in that：
The association message normally runs the message of needs, including GOOSE message, SV messages for secondary device.
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901844B (en) * | 2015-05-13 | 2019-01-22 | 国家计算机网络与信息安全管理中心 | High Precision Time Stamps acquisition methods, device and network interface card based on PCIE |
| CN105391509B (en) * | 2015-11-27 | 2018-09-18 | 积成电子股份有限公司 | Network interface split-second precision scaling method based on FPGA |
| CN106201970B (en) * | 2016-06-22 | 2020-09-29 | 广东电网有限责任公司电力科学研究院 | Information acquisition device and method |
| CN108181798A (en) * | 2017-11-28 | 2018-06-19 | 东莞理工学院 | A kind of electric grid secondary apparatus self-adaptation setting means |
| CN109581856B (en) * | 2018-12-13 | 2020-09-29 | 国电南瑞科技股份有限公司 | Time synchronization and time keeping method based on high-performance crystal oscillator frequency calibration |
| CN111147177B (en) * | 2019-12-16 | 2022-04-05 | 国家电网有限公司大数据中心 | Mobile network time service method and system for smart power grid |
| CN112994824B (en) * | 2021-03-03 | 2023-03-21 | 山东山大电力技术股份有限公司 | Time synchronization method, device and system for IRIG-B code non-delay transmission |
| CN114861425B (en) * | 2022-04-25 | 2023-02-28 | 南方电网科学研究院有限责任公司 | Data communication time calculation method and system for power grid simulation and central processing unit |
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