CN104575425A - 扫描驱动电路及其与非门逻辑运算电路 - Google Patents
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Abstract
本发明公开了一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其与非门逻辑运算电路,包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器,以及多个晶体管,利用NTFT与反相器的结合替代原有的PMOS元件的功能,实现类似原来的CMOS?NAND运算电路的特性,从而解决了IGZO?TFT单型器件逻辑运算电路的设计问题,更适合大型的数字集成电路集成在液晶显示器。
Description
技术领域
本发明涉及液晶显示技术领域,特别是涉及一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其与非门逻辑运算电路。
背景技术
对于大规模集成电路而言,逻辑运算电路最基本的三个器件就是反相器(Inverter)、与非门(NAND)、或非门(NOR),而通常这三种器件都是采用CMOS FET做成,也就是电路中有PMOS和NMOS两种器件。
在氧化物半导体器件中,IGZO已经成为了下一代显示器关注的焦点,而氧化半导体由于特殊的材料结构决定了其具备较好的NTFT特性。但是,在薄膜晶体管TFT中也有NTFT和PTFT两种器件,但是一般只有LTPS制程才能获得性能较好的PTFT器件,因此如何利用单型的器件(PTFT或NTFT)制作出Inverter、NAND或NOR也成为一个亟待解决的问题。
发明内容
本发明主要解决的技术问题是提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其与非门逻辑运算电路,能够利用单型的器件(PTFT或NTFT)制作出NAND。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种与非门逻辑运算电路,所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器,以及第九晶体管(T9),栅极电性连接于所述第一反相器的输出端,漏极电性连接于恒压高电位(DCH),源极电性连接于所述逻辑运算电路的输出端(Vout);第十晶体管(T10),栅极电性连接于所述第二反相器的输出端,漏极电性连接于所述恒压高电位(DCH),源极电性连接于所述逻辑运算电路的输出端(Vout);第十一晶体管(T11),栅极电性连接于所述逻辑运算电路的第一输入端(A),漏极电性连接于所述逻辑运算电路的输出端(Vout);第十二晶体管(T12),栅极电性连接于所述逻辑运算电路的第二输入端(B),漏极电性连接于所述第一十一晶体管(T11)的源极,源极电性连接于恒压低电位(DCL)。
其中,所述第一反相器与所述第二反相器相同,均包括:第一晶体管(T1),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);第二晶体管(T2),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);第三晶体管(T3),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);第四晶体管(T4),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);第五晶体管(T5),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第三节点(M);第六晶体管(T6),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第三节点(M),源极连接于恒压低电位(DCL);第七晶体管(T7),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);第八晶体管(T8),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
其中,所述第一反相器和所述第二反相器通过所述恒压低电位(DCL)以及所述第一负电位(VSS1)接收电路控制信号。
其中,所述第一反相器与所述第二反相器相同,均包括:第二十一晶体管(T21),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);第二十二晶体管(T22),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);第二十三晶体管(T23),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);第二十四晶体管(T24),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);第二十五晶体管(T25),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);第二十六晶体管(T26),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
其中,所述第一反相器和所述第二反相器通过所述恒压高电位(DCH)以及所述恒压低电位(DCL)接收电路控制信号。
其中,所述第一反相器包括:第一晶体管(T1),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);第二晶体管(T2),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);第三晶体管(T3),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);第四晶体管(T4),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);第五晶体管(T5),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第三节点(M);第六晶体管(T6),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第三节点(M),源极连接于恒压低电位(DCL);第七晶体管(T7),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);第八晶体管(T8),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL);所述第二反相器包括:第二十一晶体管(T21),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);第二十二晶体管(T22),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);第二十三晶体管(T23),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);第二十四晶体管(T24),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);第二十五晶体管(T25),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);第二十六晶体管(T26),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
其中,所述第一反相器通过所述恒压低电位(DCL)以及所述第一负电位(VSS1)接收电路控制信号,所述第二反相器通过所述恒压高电位(DCH)以及所述恒压低电位(DCL)接收电路控制信号。
其中,所述第一负电位(VSS1)、第二负电位(VSS2)与恒压低电位(DCL)的关系为:恒压低电位(DCL)<第二负电位(VSS2)<第一负电位(VSS1)。
其中,所述与非门逻辑运算电路通过所述恒压高电位(DCH)以及所述恒压低电位(DCL)接收电路控制信号。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路,所述电路包括与非门逻辑运算电路。
本发明的有益效果是:本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其与非门逻辑运算电路,包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器,以及多个晶体管,利用NTFT与反相器的结合替代原有的PMOS元件的功能,实现类似原来的CMOS NAND运算电路的特性,从而解决了IGZO TFT单型器件逻辑运算电路的设计问题,更适合大型的数字集成电路集成在液晶显示器。
附图说明
图1为本发明实施方式中的与非门逻辑运算电路的电路图;
图2为本发明实施方式中的与非门逻辑运算电路中的第一反相器的电路图;
图3为本发明实施方式中的与非门逻辑运算电路中的第二反相器的电路图。
具体实施方式
下面结合附图和实施方式对本发明进行详细说明。
请参阅图1,为本发明实施方式中的与非门逻辑运算电路的电路图。其中,该与非门逻辑运算电路20为应用于用于氧化物半导体薄膜晶体管的扫描驱动电路的逻辑运算电路。
该电路10包括第一反相器100、第二反相器200,其中,该第一反相器100和第二反相器200均为应用于GOA电路下拉维持电路中反相器。
进一步地,该第一反相器100和第二反相器200均为应用于GOA电路下拉维持电路中的主反相器部分。
该电路10还包括:
第九晶体管(T9),栅极电性连接于该第一反相器的输出端,漏极电性连接于恒压高电位(DCH),源极电性连接于该逻辑运算电路的输出端(Vout)。
第十晶体管(T10),栅极电性连接于该第二反相器的输出端,漏极电性连接于该恒压高电位(DCH),源极电性连接于该逻辑运算电路的输出端(Vout)。
第十一晶体管(T11),栅极电性连接于该逻辑运算电路的第一输入端(A),漏极电性连接于该逻辑运算电路的输出端(Vout)。
第十二晶体管(T12),栅极电性连接于该逻辑运算电路的第二输入端(B),漏极电性连接于该第一十一晶体管(T11)的源极,源极电性连接于恒压低电位(DCL)。
其中,该与非门逻辑运算电路通过该恒压高电位(DCH)以及该恒压低电位(DCL)接收电路控制信号。
请同时参阅图2,为本发明一实施方式中的与非门逻辑运算电路中的反相器的电路图。该反相器的组成及连接关系如下:
第一晶体管(T1),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S)。
第二晶体管(T2),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1)。
第三晶体管(T3),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于该反相器的输出端(Vout)。
第四晶体管(T4),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于该反相器的输出端(Vout),源极电性连接第二节点(K)。
第五晶体管(T5),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第三节点(M)。
第六晶体管(T6),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于第三节点(M),源极连接于恒压低电位(DCL)。
第七晶体管(T7),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K)。
第八晶体管(T8),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
其中,该反相器通过该恒压低电位(DCL)以及该第一负电位(VSS1)接收电路控制信号。
第一负电位(VSS1)、第二负电位(VSS2)与恒压低电位(DCL)的关系为:恒压低电位(DCL)<第二负电位(VSS2)<第一负电位(VSS1)。
请参阅图3,为本发明另一实施方式中的与非门逻辑运算电路中的反相器的电路图。该反相器的组成及连接关系如下:
第二十一晶体管(T21),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S)。
第二十二晶体管(T22),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1)。
第二十三晶体管(T23),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于该反相器的输出端(Vout)。
第二十四晶体管(T24),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于该反相器的输出端(Vout),源极电性连接第二节点(K)。
第二十五晶体管(T25),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K)。
第二十六晶体管(T26),栅极电性连接于该反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
其中,该反相器通过该恒压高电位(DCH)以及该恒压低电位(DCL)接收电路控制信号。
第一负电位(VSS1)、第二负电位(VSS2)与恒压低电位(DCL)的关系为:恒压低电位(DCL)<第二负电位(VSS2)<第一负电位(VSS1)。
在本实施方式中,该电路10包括的第一反相器和第二反相器均为如图2所示的反相器。
在另一实施方式中,该电路10包括的第一反相器和第二反相器均为如图3所示的反相器。
再一实施方式中,该电路10包括的第一反相器为如图2所示的反相器,第二反相器均为如图3所示的反相器。
本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路及其与非门逻辑运算电路,包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器,以及多个晶体管,利用NTFT与反相器的结合替代原有的PMOS元件的功能,实现类似原来的CMOS NAND运算电路的特性,从而解决了IGZO TFT单型器件逻辑运算电路的设计问题,更适合大型的数字集成电路集成在液晶显示器。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (10)
1.一种与非门逻辑运算电路,其特征在于,所述电路包括应用于GOA电路下拉维持电路中的第一反相器和第二反相器,以及
第九晶体管(T9),栅极电性连接于所述第一反相器的输出端,漏极电性连接于恒压高电位(DCH),源极电性连接于所述逻辑运算电路的输出端(Vout);
第十晶体管(T10),栅极电性连接于所述第二反相器的输出端,漏极电性连接于所述恒压高电位(DCH),源极电性连接于所述逻辑运算电路的输出端(Vout);
第十一晶体管(T11),栅极电性连接于所述逻辑运算电路的第一输入端(A),漏极电性连接于所述逻辑运算电路的输出端(Vout);
第十二晶体管(T12),栅极电性连接于所述逻辑运算电路的第二输入端(B),漏极电性连接于所述第一十一晶体管(T11)的源极,源极电性连接于恒压低电位(DCL)。
2.根据权利要求1所述的与非门逻辑运算电路,其特征在于,所述第一反相器与所述第二反相器相同,均包括:
第一晶体管(T1),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);
第二晶体管(T2),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);
第三晶体管(T3),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);
第四晶体管(T4),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);
第五晶体管(T5),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第三节点(M);
第六晶体管(T6),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第三节点(M),源极连接于恒压低电位(DCL);
第七晶体管(T7),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);
第八晶体管(T8),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
3.根据权利要求2所述的与非门逻辑运算电路,其特征在于,所述第一反相器和所述第二反相器通过所述恒压低电位(DCL)以及所述第一负电位(VSS1)接收电路控制信号。
4.根据权利要求1所述的与非门逻辑运算电路,其特征在于,所述第一反相器与所述第二反相器相同,均包括:
第二十一晶体管(T21),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);
第二十二晶体管(T22),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);
第二十三晶体管(T23),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);
第二十四晶体管(T24),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);
第二十五晶体管(T25),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);
第二十六晶体管(T26),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
5.根据权利要求4所述的与非门逻辑运算电路,其特征在于,所述第一反相器和所述第二反相器通过所述恒压高电位(DCH)以及所述恒压低电位(DCL)接收电路控制信号。
6.根据权利要求1所述的与非门逻辑运算电路,其特征在于,所述第一反相器包括:
第一晶体管(T1),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);
第二晶体管(T2),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);
第三晶体管(T3),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);
第四晶体管(T4),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);
第五晶体管(T5),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第三节点(M);
第六晶体管(T6),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第三节点(M),源极连接于恒压低电位(DCL);
第七晶体管(T7),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);
第八晶体管(T8),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL);
所述第二反相器包括:
第二十一晶体管(T21),栅极与漏极均电性连接于恒压高电位(DCH),源极电性连接于第一节点(S);
第二十二晶体管(T22),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第一节点(S),源极电性连接于第一负电位(VSS1);
第二十三晶体管(T23),栅极电性连接于第一节点(S),漏极电性连接于恒压高电位(DCH),源极电性连接于所述反相器的输出端(Vout);
第二十四晶体管(T24),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于所述反相器的输出端(Vout),源极电性连接第二节点(K);
第二十五晶体管(T25),栅极电性连接于第三节点(M),漏极电性连接于恒压高电位(DCH),源极电性连接于第二节点(K);
第二十六晶体管(T26),栅极电性连接于所述反相器的输入端(Vin),漏极电性连接于第二节点(K),源极连接于恒压低电位(DCL)。
7.根据权利要求6所述的与非门逻辑运算电路,其特征在于,所述第一反相器通过所述恒压低电位(DCL)以及所述第一负电位(VSS1)接收电路控制信号,所述第二反相器通过所述恒压高电位(DCH)以及所述恒压低电位(DCL)接收电路控制信号。
8.根据权利要求1至7任一项所述的与非门逻辑运算电路,其特征在于,所述第一负电位(VSS1)、第二负电位(VSS2)与恒压低电位(DCL)的关系为:恒压低电位(DCL)<第二负电位(VSS2)<第一负电位(VSS1)。
9.根据权利要求1所述的与非门逻辑运算电路,其特征在于,所述与非门逻辑运算电路通过所述恒压高电位(DCH)以及所述恒压低电位(DCL)接收电路控制信号。
10.一种用于氧化物半导体薄膜晶体管的扫描驱动电路,其特征在于,所述电路包括如权利要求1至9任意一项所述的与非门逻辑运算电路。
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- 2015-01-28 RU RU2017128297A patent/RU2648614C1/ru active
- 2015-01-28 WO PCT/CN2015/071705 patent/WO2016109994A1/zh active Application Filing
- 2015-01-28 DE DE112015005530.4T patent/DE112015005530T5/de active Pending
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Also Published As
Publication number | Publication date |
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KR101894199B1 (ko) | 2018-10-04 |
JP2018509020A (ja) | 2018-03-29 |
US20170229081A1 (en) | 2017-08-10 |
WO2016109994A1 (zh) | 2016-07-14 |
GB2549862B (en) | 2021-07-14 |
GB201708791D0 (en) | 2017-07-19 |
KR20170103904A (ko) | 2017-09-13 |
JP6637506B2 (ja) | 2020-01-29 |
GB2549862A (en) | 2017-11-01 |
DE112015005530T5 (de) | 2017-09-21 |
CN104575425B (zh) | 2017-04-12 |
RU2648614C1 (ru) | 2018-03-26 |
US9786692B2 (en) | 2017-10-10 |
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