Summary of the invention
The technical problem to be solved in the present invention provides a kind of watchdog reset circuit and repositioning method, to guarantee the operate as normal of watchdog circuit during the programming device upgrading.
In order to solve the problems of the technologies described above, the invention provides a kind of watchdog reset circuit, comprise the CPU that is connected in series, watchdog module, programming device, comprise that also at least one has the element of clocking capability, described element and described programming device are arranged in parallel, the output reset signal is to the reset signal port of described watchdog module, described element receives the bus signals of CPU, when upgrading, described programming device picks up counting, if CPU crashes in the timing time, then described element at timing time then to watchdog module output reset signal, restarts CPU by described watchdog module to CPU output power-on reset signal.
Further, after described programming device and described reset signal with element of clocking capability are passed through the logical and module, output to the reset signal port of watchdog module.
Further, the reset signal port at described watchdog module is provided with a manual switch.
Further, described timing time with element of clocking capability is the update time of the programming device of expectation.
Further, described element with clocking capability is programmable logic device (PLD) or the processor with clocking capability.
Further, when adopting the programmable logic device (PLD) conduct to have the clocking capability element, described programmable logic device (PLD) adopts one of following device: the electrically programmable logical device is that EPLD, CPLD are that CPLD, field programmable gate array are FPGA; When adopting the processor conduct to have the clocking capability element, described processor adopting digital signal processor DSP.
In order to solve the problems of the technologies described above, the present invention also provides a kind of watchdog reset method, when CPU judges that programming device need be upgraded, the element that notice has clocking capability picks up counting, and the upgrading programming device, if CPU crashes before described element timing arrives, then described element is when timing arrives, to watchdog module output reset signal, watchdog module restarts CPU to CPU output power-on reset signal.
Further, described timing time with element of clocking capability is the update time of the programming device of expectation.
Further, described element with clocking capability is programmable logic device (PLD) or the processor with clocking capability.
Further, when adopting the programmable logic device (PLD) conduct to have the clocking capability element, described programmable logic device (PLD) adopts one of following device: the electrically programmable logical device is that EPLD, CPLD are that CPLD, field programmable gate array are FPGA; When adopting the processor conduct to have the clocking capability element, described processor adopting digital signal processor DSP.
The inventive method is applicable to most digital communication veneers.Adopt circuit of the present invention and method, can guarantee watchdog circuit operate as normal during the programming device upgrading, watchdog circuit is more flexible, and the reset function of system is more reliable.The logical and module is finished the logical and function of two programming device output signals among the present invention, thereby makes two programming devices can finish the cpu function that resets.Dirigibility of the present invention is that the logical and module can be discrete logical AND gate, also can be the chip pin logic line with.Dirigibility of the present invention is that also programming device two also can be other devices such as signal processor, as long as CPU can visit and have clocking capability.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
As shown in Figure 1, the present invention is for realizing that watchdog circuit during the programming device upgrading is still in the watchdog reset circuit of operate as normal, be provided with plural programming device, newly-increased programming device two is to serve as interim house dog during programming device one upgraded version, be the another one house dog, therefore also watchdog circuit provided by the invention can be considered as a kind of many watchdog reset circuits.Fig. 1 has shown the situation that two programming devices are arranged, and many watchdog circuits comprise with lower module:
The CPU processor is connected with programming device by bus, and receives the power-on reset signal (Power_Reset) that watchdog circuit sends;
Programming device one is used to cooperate watchdog chip to realize the veneer watchdog function, plays the effect of expansion time-delay;
Watchdog chip, its house dog input end (WDI) links to each other with programming device one with house dog output terminal (WDO), when having level in the regular hour, the WDI pin do not change, WDO can export a negative pulse, when hand-reset signal (Manu_Reset) when negative pulse occurring, the reset pulse (Powreset signal) that watchdog chip will produce certain width outputs to CPU;
Except using special watchdog chip, other modules that can realize watchdog function all can.
Programming device two when programming device one upgrading, is provided with timing, and at timing then, the output negative pulse triggers cpu reset by watchdog chip to Manu_Reset;
Timing can be set as required, is generally the update time of the programming device of expectation.Except adopting programming device (as electrically programmable logical device EPLD, complex programmable logic device (CPLD), on-site programmable gate array FPGA etc.), also can adopt processor to realize, as digital signal processor DSP, in a word, as long as there is the element of clocking capability all can realize.
Logical and module log1, the reset signal of reception programming device one and programming device two is through behind the logic and operation, to watchdog chip output Manu_Reset.
Utilize circuit of the present invention, many watchdog reset circuits of in the TD-SCDMA system, realizing, as shown in Figure 2.In the present embodiment, watchdog chip adopts 706; Programming device has been selected EPLD (CPLD) and FPGA (field programmable gate array) for use, and wherein EPLD is as cooperate the programmable logic device (PLD) one that realizes watchdog function with watchdog chip; In addition, between the input of the output of logical AND gate and watchdog chip, increased a manual reset switch Switch, sent hand-reset signal (Manu_Reset) to watchdog chip, with convenient when the practical application, hand-reset CPU.The signal that watchdog chip receives EPLD and/or FPGA sends power-on reset signal to CPU, perhaps by the reset switch hand-reset.
Fig. 3 is the process flow diagram that the present invention realizes many watchdog resets, may further comprise the steps:
Step 310, CPU normally move, the watchdog circuit operate as normal;
Step 320, CPU are judged programming device one according to programming device one current version whether the needs upgrading are loaded, if jump to step 330, otherwise return step 310;
Whether CPU can be set to regularly detect programming device one needs upgrading.
Step 330, CPU notice programming device two opening timing functions, programming device two timing begin;
The version of step 340, CPU upgrading programming device one;
If step 350 CPU in programming device two timings crashes, forward step 370 to, otherwise jump to step 360;
Step 360, CPU notice programming device two programming devices one version load successfully, and the timeing closing device returns step 310;
Step 370, programming device two timings arrive, and to watchdog chip output reset signal, watchdog chip is received the hand-reset signal, then to CPU output reset signal;
Step 380, CPU restart;
Step 390, CPU start successfully.
After CPU notice programming device two programming devices one load successfully in step 360, and in the step 390, after CPU started successfully, CPU can continue to use programming device one as watchdog circuit, and subsequent treatment and the present invention are irrelevant.
For the timer of programming device two, when cpu reset, can close the timer of programming device two by reset signal, if CPU does not reset, then can after the success of CPU loading programmable device one redaction, close this timer, this prescribing method has a variety of.
In the TD-SCDMA system, adopt flow process that said method realizes many house dogs as shown in Figure 4, programming device has been selected EPLD and FPGA for use, and the timer timing was an example with 5 seconds, and step is as follows:
Step 410, CPU normally move, the watchdog circuit operate as normal;
Step 420, judge EPLD whether need the upgrading, if jump to step 430, otherwise be transferred to step 410;
Step 430, CPU notice FPGA opening timing function, countdown begins for 5 seconds;
Step 440, CPU upgrading EPLD version;
If step 450 is the success of CPU upgrading EPLD version in timing, execution in step 460 jumps to step 470 if CPU crashes;
Step 460, CPU notice FPGA programming device one EPLD version load successfully, and clocking capability is closed, and returns step 410;
Step 470, FPGA5 timing in second end, output cpu reset pulse signal;
Step 480, CPU restart;
Step 490, CPU start successfully, return step 410;
Though describe embodiments of the invention in detail in conjunction with the above-mentioned application of diagrammatic sketch, but this is not a practical application unique method of the present invention, for those skilled in the art, still can modify and do not change the spirit and scope of the invention above-mentioned embodiment.