CN104538352A

CN104538352A - Array substrate, manufacturing method thereof and display device

Info

Publication number: CN104538352A
Application number: CN201410852998.8A
Authority: CN
Inventors: 刘翔
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2014-12-31
Filing date: 2014-12-31
Publication date: 2015-04-22

Abstract

The invention discloses an array substrate, a manufacturing method of the array substrate and a display device. The array substrate comprises a first thin film transistor and a second thin film transistor. The first thin film transistor and the second thin film transistor are formed above an underlayer substrate. The first thin film transistor is a polycrystalline silicon thin film transistor. The second thin film transistor is a metallic oxide thin film transistor or an amorphous silicon thin film transistor. The first thin film transistor is located on the peripheral region of the array substrate, and the second thin film transistor is located on the display region of the array substrate. By means of the technical scheme, the problem that the polycrystalline silicon thin film transistor cannot be applied to production of large display panels with the ram being over 6 G is solved, the limit of the excimer laser crystallization process bottleneck is broken through thoroughly, and the array substrate, the manufacturing method and the display device have very high application value.

Description

Array base palte and manufacture method, display unit

Technical field

The present invention relates to Display Technique field, particularly array base palte and manufacture method, display unit.

Background technology

Along with the size of display floater constantly increases, the frequency of drive circuit constantly improves, and the integrated level of the neighboring area of display floater also can correspondingly improve, and existing amorphous silicon film transistor electron mobility is difficult to meet job requirement.For this reason, the amorphous silicon film transistor in display floater is replaced with the more much higher polycrystal silicon film transistor of electron mobility by production firm.

Prior art is when preparing polysilicon layer, following three kinds of technology are often adopted to be prepared: solid phase crystallization (Solid Phase Crystallization, be called for short SPC), metal-induced lateral crystallization (Metal-Induced Lateral Crystallization, be called for short MILC) and quasi-molecule laser annealing (Excimer Laser Anneal is called for short Excimer-Laser Crystallization).Wherein, quasi-molecule laser annealing technique is being utilized to prepare in the process of polysilicon, because melting crystal process is very short, very little to the thermal shock of substrate, the inexpensive glass even feature such as plastic of non-refractory can be used, thus receive the favor of vast panel production firm.

But, add man-hour at the large scale display floater carrying out more than 6G, be subject to the restriction of laser pulse wide cut, the homogeneity of the polysilicon layer prepared can be made poor, thus directly had influence on the homogeneity of thin-film transistor, and then have influence on the picture display of display floater.Therefore, polycrystalline SiTFT is no longer suitable for the production of the large scale display floater of more than 6G.

Summary of the invention

The invention provides a kind of array base palte and manufacture method, display unit, effectively can solve the problem that polycrystalline SiTFT cannot be applied to the production of the large scale display floater of more than 6G.

For achieving the above object, the invention provides a kind of manufacture method of array base palte, comprising:

The first film transistor and the second thin-film transistor is formed above underlay substrate, described the first film transistor is polycrystalline SiTFT, described second thin-film transistor is metal oxide thin-film transistor or amorphous silicon film transistor, described the first film transistor is positioned at the neighboring area of described array base palte, and described second thin-film transistor is positioned at the viewing area of described array base palte.

Alternatively, described second thin-film transistor is metal oxide thin-film transistor, described the first film transistor comprises: polysilicon semiconductor layer, and described second thin-film transistor comprises: metal-oxide semiconductor layer, and the material of described metal oxide semiconductor layer is amorphous metal oxide;

The described step forming the first film transistor and the second thin-film transistor above described underlay substrate specifically comprises:

At disposed thereon one deck amorphous silicon membrane of described underlay substrate;

Patterning processes is carried out to described amorphous silicon membrane, forms amorphous silicon figure with the fringe region at described array base palte;

Carry out crystallization processes process to described amorphous silicon figure, to make described amorphous silicon graphics for polysilicon graphics, described polysilicon graphics forms described polysilicon semiconductor layer;

Described first insulating barrier is formed above described polysilicon semiconductor layer and described underlay substrate;

At disposed thereon one deck amorphous metal oxide film of described first insulating barrier;

Carry out patterning processes to described amorphous metal oxide film, to form amorphous metal oxide figure in the viewing area of described array base palte, described amorphous metal oxide figure forms described metal-oxide semiconductor layer.

Alternatively, described second thin-film transistor is metal oxide thin-film transistor, described the first film transistor comprises: polysilicon semiconductor layer, and described second thin-film transistor comprises: metal-oxide semiconductor layer, and the material of described metal oxide semiconductor layer is crystalline metal-oxide;

Described first insulating barrier is formed above described amorphous silicon figure and described underlay substrate;

Patterning processes is carried out to described amorphous metal oxide film, to form amorphous metal oxide figure in the viewing area of described array base palte;

Crystallization processes process is carried out to described amorphous silicon figure and described amorphous metal oxide figure, to make described amorphous silicon graphics for polysilicon graphics, described amorphous metal oxide graphics is crystalline metal-oxide figure, described polysilicon graphics forms described polysilicon semiconductor layer, and described crystalline metal-oxide figure forms described metal oxide semiconductor layer.

Alternatively, described the first film transistor also comprises: first grid, the first source electrode and the first drain electrode, and described second thin-film transistor also comprises: second grid, the second source electrode and the second drain electrode;

Also comprise after forming the step of metal oxide semiconductor layer:

The second insulating barrier is formed above described metal oxide semiconductor layer and described first insulating barrier;

Above described second insulating barrier, form first grid and second grid, described first grid is positioned at the neighboring area of described array base palte, and described second grid is positioned at the viewing area of described array base palte;

The 3rd insulating barrier is formed above described first grid, described second grid and described second insulating barrier;

On described first insulating barrier, described second insulating barrier and described 3rd insulating barrier, the region of corresponding described polysilicon semiconductor layer forms the first via hole, and the region of corresponding described metal oxide semiconductor layer forms the second via hole on described second insulating barrier and described 3rd insulating barrier;

The first source electrode, the first drain electrode, the second source electrode and the second drain electrode is formed above described 3rd insulating barrier, described first source electrode is connected with described polysilicon semiconductor layer by described first via hole with described first drain electrode, and described second source electrode is connected with described metal oxide semiconductor layer by described second via hole with described second drain electrode;

The 4th insulating barrier is formed above described first source electrode, described first drain electrode, described second source electrode, described second drain electrode and described 3rd insulating barrier, on described 4th insulating barrier, the region of corresponding described first drain electrode is formed with the 3rd via hole, and on described 4th insulating barrier, the region of corresponding described second drain electrode is formed with the 4th via hole;

Above described 4th insulating barrier, form the first pixel electrode and the second pixel electrode, described first pixel electrode is drained by described 3rd via hole and described first and is connected, and described second pixel electrode is drained by described 4th via hole and described second and is connected.

Alternatively, described second thin-film transistor is amorphous silicon film transistor, and described the first film transistor comprises: polysilicon semiconductor layer, and described second thin-film transistor comprises: amorphous silicon semiconductor layer;

Carry out patterning processes to described amorphous silicon material, all to form amorphous silicon figure at the fringe region of described array base palte and viewing area, the amorphous silicon figure being positioned at the viewing area of described underlay substrate forms amorphous silicon semiconductor layer;

Crystallization processes process is carried out to the amorphous silicon figure of the neighboring area being positioned at described underlay substrate, to make the amorphous silicon graphics of the neighboring area being positioned at described underlay substrate for polysilicon graphics, the polysilicon graphics being positioned at the neighboring area of described underlay substrate forms described polysilicon semiconductor layer.

Also comprise after forming the step of polysilicon semiconductor layer:

Pentasyllabic quatrain edge layer is formed above described amorphous silicon semiconductor layer, described polysilicon semiconductor layer and described underlay substrate;

Above described pentasyllabic quatrain edge layer, form first grid and second grid, described first grid is positioned at the neighboring area of described array base palte, and described second grid is positioned at the viewing area of described array base palte;

The 6th insulating barrier is formed above described first grid, described second grid and described pentasyllabic quatrain edge layer;

In described pentasyllabic quatrain edge layer and described 6th insulating barrier, the region of corresponding described polysilicon semiconductor layer forms the 5th via hole, and the region of corresponding described amorphous silicon semiconductor layer forms the 6th via hole in described pentasyllabic quatrain edge layer and the 6th insulating barrier;

The first source electrode, the first drain electrode, the second source electrode and the second drain electrode is formed above described 6th insulating barrier, described first source electrode is connected with described polysilicon semiconductor layer by described 5th via hole with described first drain electrode, and described second source electrode is connected with described amorphous silicon semiconductor layer by described 6th via hole with described second drain electrode;

Four-line poem with seven characters to a line edge layer is formed above described first source electrode, described first drain electrode, described second source electrode, described second drain electrode and described 6th insulating barrier, in described four-line poem with seven characters to a line edge layer, the region of corresponding described first drain electrode is formed with the 7th via hole, and in described four-line poem with seven characters to a line edge layer, the region of corresponding described second drain electrode is formed with the 8th via hole;

Above described four-line poem with seven characters to a line edge layer, form the first pixel electrode and the second pixel electrode, described first pixel electrode is drained by described 7th via hole and described first and is connected, and described second pixel electrode is drained by described 8th via hole and described second and is connected.

Alternatively, described crystallization processes process comprises: solid phase crystallization process, laser crystallization technique or thermal anneal process.

For achieving the above object, the present invention also provides a kind of array base palte, comprise: the first film transistor and the second thin-film transistor, described the first film transistor and described second thin-film transistor are formed at the top of underlay substrate, described the first film transistor is polycrystalline SiTFT, described second thin-film transistor is metal oxide thin-film transistor or amorphous silicon film transistor, described the first film transistor is positioned at the neighboring area of described array base palte, and described second thin-film transistor is positioned at the viewing area of described array base palte.

Alternatively, described second thin-film transistor is metal oxide thin-film transistor, and described array base palte specifically comprises:

Polysilicon semiconductor layer, described polysilicon semiconductor layer is formed at the top of described underlay substrate, and described polysilicon semiconductor layer is positioned at the neighboring area of described array base palte;

First insulating barrier, described first insulating barrier is formed at the top of described polysilicon semiconductor layer and described underlay substrate;

Metal oxide semiconductor layer, described metal oxide semiconductor layer is formed at the top of described first insulating barrier, and described metal oxide semiconductor layer is positioned at the viewing area of described array base palte;

Second insulating barrier, described second insulating barrier is formed at the top of described first insulating barrier and described metal oxide semiconductor layer;

First grid and second grid, described first grid and described second grid are formed at the top of described second insulating barrier, and first grid is positioned at the neighboring area of described array base palte, and described second grid is positioned at the viewing area of described array base palte;

3rd insulating barrier, described 3rd insulating barrier is formed at the top of described first grid, described second grid and described second insulating barrier, on described first insulating barrier, described second insulating barrier and described 3rd insulating barrier, the region of corresponding described polysilicon semiconductor layer is formed with the first via hole, and on described second insulating barrier and described 3rd insulating barrier, the region of corresponding described metal oxide semiconductor layer is formed with the second via hole;

First source electrode, the first drain electrode, the second source electrode and the second drain electrode, described first source electrode, described first drain electrode, described second source electrode and described second drain electrode are formed at the top of described 3rd insulating barrier, described first source electrode is connected with described polysilicon semiconductor layer by described first via hole with described first drain electrode, and described second source electrode is connected with described metal oxide semiconductor layer by described second via hole with described second drain electrode;

4th insulating barrier, described 4th insulating barrier is formed at described first source electrode, described first drain electrode, described second source electrode, described second drain electrode and the top of described 3rd insulating barrier, on described 4th insulating barrier, the region of corresponding described first drain electrode is formed with the 3rd via hole, and on described 4th insulating barrier, the region of corresponding described second drain electrode is formed with the 4th via hole

First pixel electrode and the second pixel electrode, described first pixel electrode and described second pixel electrode are formed at the top of described 4th insulating barrier, described first pixel electrode is drained by described 3rd via hole and described first and is connected, and described second pixel electrode is drained by described 4th via hole and described second and is connected.

Alternatively, the material of described metal oxide semiconductor layer is crystalline metal-oxide.

Alternatively, described second thin-film transistor is amorphous silicon film transistor, and described array base palte specifically comprises:

Polysilicon semiconductor layer, described polysilicon semiconductor layer is formed at the top of described underlay substrate, and described polysilicon semiconductor layer is positioned at the neighboring area of array base palte;

Amorphous silicon semiconductor layer, described amorphous silicon semiconductor layer is formed at the top of described underlay substrate, and described amorphous silicon semiconductor layer is positioned at the viewing area of array base palte;

Pentasyllabic quatrain edge layer, described pentasyllabic quatrain edge layer is formed at the top of described amorphous silicon semiconductor layer, described polysilicon semiconductor layer and described underlay substrate;

First grid and second grid, described first grid and described second grid are formed at the top of described pentasyllabic quatrain edge layer, and described first grid is positioned at the neighboring area of described array base palte, and described second grid is positioned at the viewing area of described array base palte;

6th insulating barrier, described 6th insulating barrier is formed at the top of described first grid, described second grid and described pentasyllabic quatrain edge layer, on described pentasyllabic quatrain edge layer and described 6th insulating barrier, the region of corresponding described polysilicon semiconductor layer is formed with the 5th via hole, and on described pentasyllabic quatrain edge layer and the 6th insulating barrier, the region of corresponding described amorphous silicon semiconductor layer is formed with the 6th via hole;

First source electrode, the first drain electrode, the second source electrode and the second drain electrode, described first source electrode, described first drain electrode, described second source electrode and described second drain electrode are formed at the top of described 6th insulating barrier, described first source electrode is connected with described polysilicon semiconductor layer by described 5th via hole with described first drain electrode, and described second source electrode is connected with described amorphous silicon semiconductor layer by described 6th via hole with described second drain electrode;

Four-line poem with seven characters to a line edge layer, described four-line poem with seven characters to a line edge layer is formed at described first source electrode, described first drain electrode, described second source electrode, described second drain electrode and the top of described 6th insulating barrier, in described four-line poem with seven characters to a line edge layer, the region of corresponding described first drain electrode is formed with the 7th via hole, and in described four-line poem with seven characters to a line edge layer, the region of corresponding described second drain electrode is formed with the 8th via hole;

First pixel electrode and the second pixel electrode, described first pixel electrode and described second pixel electrode are formed at the top of described four-line poem with seven characters to a line edge layer, described first pixel electrode is drained by described 7th via hole and described first and is connected, and described second pixel electrode is drained by described 8th via hole and described second and is connected.

For achieving the above object, the present invention also provides a kind of display unit, comprising: array base palte, and described array base palte adopts above-mentioned array base palte.

The present invention has following beneficial effect:

The embodiment of the present invention two provides a kind of array base palte and manufacture method, display unit, wherein, this array base palte comprises: the first film transistor and the second thin-film transistor, the first film transistor and the second thin-film transistor are formed at the top of underlay substrate, the first film transistor is polycrystalline SiTFT, second thin-film transistor is metal-oxide film crystal silicon pipe or amorphous silicon film transistor, the first film transistor is positioned at the neighboring area of array base palte, and the second thin-film transistor is positioned at the viewing area of array base palte.Technical scheme of the present invention effectively can solve the problem that polycrystalline SiTFT cannot be applied to the production of the large scale display floater of more than 6G, thoroughly breaks through the restriction of Excimer-Laser Crystallization technique bottleneck, has very high using value.

Accompanying drawing explanation

The schematic cross-section of the array base palte that Fig. 1 provides for the embodiment of the present invention one;

Fig. 2 is the flow chart of the manufacture method of array base palte shown in Fig. 1;

Fig. 3 a is the schematic diagram forming amorphous silicon figure above underlay substrate;

Fig. 3 b is the schematic diagram forming the first insulating barrier above amorphous silicon figure and underlay substrate;

Fig. 3 c carries out the schematic diagram after crystallization processes to amorphous silicon figure and amorphous metal oxide figure;

Fig. 3 d is the schematic diagram forming the second insulating barrier above metal oxide semiconductor layer and the first insulating barrier;

Fig. 3 e is the schematic diagram forming first grid and second grid above the second insulating barrier;

Fig. 3 f is the schematic diagram forming the 3rd insulating barrier above first grid, second grid and the second insulating barrier;

Fig. 3 g is the schematic diagram forming the first via hole and the second via hole on each insulating barrier;

Fig. 3 h forms the first source electrode, the first drain electrode, the second source electrode and the second schematic diagram drained above the 3rd insulating barrier;

Fig. 3 i is the schematic diagram forming the 4th insulating barrier above the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the 3rd insulating barrier;

The schematic cross-section of the array base palte that Fig. 4 provides for the embodiment of the present invention one;

Fig. 5 is the flow chart of the manufacture method of array base palte shown in Fig. 4;

Fig. 6 a is the schematic diagram forming amorphous silicon semiconductor layer and polysilicon semiconductor layer above underlay substrate;

Fig. 6 b is the schematic diagram forming pentasyllabic quatrain edge layer above amorphous silicon semiconductor layer, polysilicon semiconductor layer and underlay substrate;

Fig. 6 c is the schematic diagram forming first grid and second grid above pentasyllabic quatrain edge layer;

Fig. 6 d is the schematic diagram forming the 6th insulating barrier above first grid, second grid and pentasyllabic quatrain edge layer;

Fig. 6 e is the schematic diagram forming the 5th via hole and the 6th via hole on pentasyllabic quatrain edge layer, the 6th insulating barrier;

Fig. 6 f forms the first source electrode, the first drain electrode, the second source electrode and the second schematic diagram drained above the 6th insulating barrier;

Fig. 6 g is the schematic diagram forming four-line poem with seven characters to a line edge layer above the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the 6th insulating barrier.

Embodiment

For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with accompanying drawing, a kind of array base palte provided by the invention and manufacture method thereof, display unit are described in detail.

Embodiment one

The schematic cross-section of the array base palte that Fig. 1 provides for the embodiment of the present invention one, as shown in Figure 1, this array base palte comprises: the first film transistor A and the second thin-film transistor B, the first film transistor A and the second thin-film transistor B is formed at the top of underlay substrate 1, the first film transistor A is polycrystalline SiTFT, second thin-film transistor B is metal oxide thin-film transistor, the first film transistor A is positioned at the neighboring area of array base palte, and the second thin-film transistor is positioned at the viewing area B of array base palte.

In the present embodiment, on the one hand, by relatively much higher for electron mobility polycrystal silicon film transistor, (electron mobility is at 30cm ²about/Vs) be arranged on the neighboring area of array base palte, the neighboring area of large scale display floater can be met to the high request of the electron mobility of components and parts.On the other hand, because this polycrystalline SiTFT is only arranged on the neighboring area of array base palte, and the size of this neighboring area is less, therefore carrying out in the process of crystallization to amorphous silicon, existing Excimer-Laser Crystallization technique can meet uniformity requirements fully.In addition, in the viewing area of large scale display floater, hand over low to the requirement for driving pixel cell to carry out the electron mobility of the thin-film transistor of pixel display, (electron mobility is at 10cm for metal oxide thin-film transistor ²/ Vs) electron mobility be enough to the driving requirement meeting pixel cell.Technical scheme of the present invention, can solve the problem that polycrystalline SiTFT cannot be applied to the production of the large scale display floater of more than 6G effectively, thoroughly breaks through the restriction of Excimer-Laser Crystallization technique bottleneck, has very high using value.

In the present embodiment, this array base palte specifically comprises: polysilicon semiconductor layer 2, first insulating barrier 3, metal oxide semiconductor layer 4, second insulating barrier 5, first grid 6, second grid 7, the 3rd insulating barrier 8, first source electrode 11, first drain electrode 12, second source electrode 13, second drain electrode the 14, the 4th insulating barrier 16, first pixel electrode 18 and the second pixel electrode 19.Wherein, polysilicon semiconductor layer 2 is formed at the top of underlay substrate 1, and polysilicon semiconductor layer 2 is positioned at the neighboring area of array base palte; First insulating barrier 3 is formed at the top of polysilicon semiconductor layer 2 and underlay substrate 1; Metal oxide semiconductor layer 4 is formed at the top of the first insulating barrier 3, and metal oxide semiconductor layer 4 is positioned at the viewing area of array base palte; Second insulating barrier 5 is formed at the top of the first insulating barrier 3 and metal oxide semiconductor layer 4; First grid 6 and second grid 7 are formed at the top of the second insulating barrier, and first grid 6 is positioned at the neighboring area of array base palte, and second grid 7 is positioned at the viewing area of array base palte; 3rd insulating barrier 8 is formed at the top of first grid 6, second grid 7 and the second insulating barrier 5, the region that on first insulating barrier 3, second insulating barrier 5 and the 3rd insulating barrier 8, the region of corresponding polysilicon semiconductor layer 2 is formed with corresponding metal oxide semiconductor layer 4 on the first via hole 9, second insulating barrier 5 and the 3rd insulating barrier 8 is formed with the second via hole 10; First source electrode 11, first drain electrode 12, second source electrode 13 and the second drain electrode 14 are formed at the top of the 3rd insulating barrier, first source electrode 11 and first is leaked 12 poles and is connected with polysilicon semiconductor layer 2 by the first via hole 9, and the second source electrode 13 is connected with metal oxide semiconductor layer 4 by the second via hole 10 with the second drain electrode 14; 4th insulating barrier 15 is formed at the top of the first source electrode 11, first drain electrode 12, second source electrode 13, second drain electrode 14 and the 3rd insulating barrier 8, the region that on 4th insulating barrier 15, the region of corresponding first drain electrode 12 is formed with corresponding second drain electrode 14 on the 3rd via hole the 16, four insulating barrier 15 is formed with the 4th via hole 17; First pixel electrode 18 and the second pixel electrode 19 are formed at the top of the 4th insulating barrier 15, and the first pixel electrode 18 is drained by the 3rd via hole 16 and first and 12 to be connected, and the second pixel electrode 19 passes through the 4th via hole 17 and second and drains and 14 to be connected.

It should be noted that, polysilicon semiconductor layer 2 in the present embodiment, first grid 6, first source electrode 11 and the first drain electrode 12 form polycrystalline SiTFT, metal oxide semiconductor layer 4, second grid 8, second source electrode 13 and the second drain electrode 14 form metal oxide thin-film transistor, and each insulating barrier is to coordinate the needs of the course of processing to arrange accordingly.

In addition, in the present embodiment, the material of metal oxide semiconductor layer 4 is specifically as follows amorphous metal oxide semiconductor or crystalline metal-oxide semiconductor.

The embodiment of the present invention one additionally provides a kind of manufacture method preparing array base palte, and this manufacture method comprises:

Step S1: form the first film transistor and the second thin-film transistor above underlay substrate, the first film transistor is polycrystalline SiTFT, second thin-film transistor is metal oxide thin-film transistor, the first film transistor is positioned at the neighboring area of array base palte, and the second thin-film transistor is positioned at the viewing area of array base palte.

The array base palte shown in Fig. 1 can be prepared by step S1.Below in conjunction with accompanying drawing being described in detail with the concrete manufacture process to the array base palte shown in Fig. 1.In addition, in following content, for the material of the metal oxide semiconductor layer 4 in metal oxide thin-film transistor for crystalline metal-oxide is described.

Fig. 2 is the flow chart of the manufacture method of array base palte shown in Fig. 1, and as shown in Figure 2, step S1 specifically comprises:

Step 101: at disposed thereon one deck amorphous silicon membrane of underlay substrate.

Step 102: carry out patterning processes to amorphous silicon membrane, forms amorphous silicon figure with the fringe region at array base palte.

Fig. 3 a is the schematic diagram forming amorphous silicon figure above underlay substrate, as shown in Figure 3 a, in step 101 and step 102, first, deposits one deck amorphous silicon material by chemical gaseous phase depositing process on underlay substrate 1; Then, patterning processes is carried out to amorphous silicon membrane, form amorphous silicon figure 28 with the fringe region at array base palte.

Step 103: form the first insulating barrier above amorphous silicon figure and underlay substrate.

Fig. 3 b is the schematic diagram forming the first insulating barrier above amorphous silicon figure and underlay substrate, as shown in Figure 3 b, by disposed thereon one deck first insulating material of chemical gaseous phase depositing process at amorphous silicon figure 28 and underlay substrate 1, to form the first insulating barrier 3, this first insulating material can select oxide, nitride or oxynitrides.

Step 104: at disposed thereon one deck amorphous metal oxide film of the first insulating barrier.

Step 105: carry out patterning processes to amorphous metal oxide film, to form amorphous metal oxide figure in the viewing area of array base palte.

Step 106: carry out crystallization processes process to amorphous silicon figure and amorphous metal oxide figure, to make amorphous silicon graphics for polysilicon graphics, amorphous metal oxide graphics is crystalline metal-oxide figure.

Fig. 3 c carries out the schematic diagram after crystallization processes to amorphous silicon figure and amorphous metal oxide figure, as shown in Figure 3 c, in step 104 ~ step 106, first, by the method for sputtering or thermal evaporation at disposed thereon one deck amorphous metal oxide material of the first insulating barrier 3; Then, carry out patterning processes to form amorphous metal oxide figure to this amorphous metal oxide material, this amorphous metal oxide semiconductor figure is positioned at the viewing area of array base palte; Finally, crystallization processes process is carried out to current whole substrate, polysilicon graphics is converted into make the amorphous silicon figure 28 in substrate, amorphous metal oxide graphics is crystalline metal-oxide figure, wherein polysilicon graphics forms polysilicon semiconductor layer 2, and crystalline metal-oxide figure forms metal oxide semiconductor layer 4.

Alternatively, this crystallization processes process can be: solid phase crystallization process, laser crystallization technique or thermal anneal process.

It should be noted that, the metal oxide semiconductor layer 4 be made up of crystalline metal-oxide has stronger stability and corrosion resistance, thus effectively can avoid the impact on metal oxide semiconductor layer in follow-up technique.

In addition, in the present embodiment, the crystallization processes prepared in polysilicon semiconductor layer 2 process and the crystallization processes prepared in metal oxide semiconductor layer 4 process are completed with in an operation, thus effectively can reduce production procedure, shorten the production cycle, and then promote product line efficiency.

Step 107: form the second insulating barrier above metal oxide semiconductor layer and the first insulating barrier.

Fig. 3 d is the schematic diagram forming the second insulating barrier above metal oxide semiconductor layer and the first insulating barrier, as shown in Figure 3 d, by disposed thereon one deck second insulating material of chemical gaseous phase depositing process at metal oxide semiconductor layer 4 and the first insulating barrier 3, to form the second insulating barrier 5.Wherein, this second insulating material can select oxide, nitride or oxynitrides.

Step 108: form first grid and second grid above the second insulating barrier, first grid is positioned at the neighboring area of array base palte, and second grid is positioned at the viewing area of array base palte.

Fig. 3 e is the schematic diagram forming first grid and second grid above the second insulating barrier, as shown in Figure 3 e, first, by the method for sputtering or thermal evaporation at disposed thereon one deck grid metal material of the second insulating barrier 5; Then, a patterning processes is carried out to form first grid 6 and second grid 7 to grid metal material.Wherein, first grid 6 is positioned at the neighboring area of array base palte, and second grid 7 is positioned at the viewing area of array base palte.

Step 109: form the 3rd insulating barrier above first grid, second grid and the second insulating barrier.

Fig. 3 f is the schematic diagram forming the 3rd insulating barrier above first grid, second grid and the second insulating barrier, as illustrated in figure 3f, by disposed thereon one deck three insulating material of chemical gaseous phase depositing process at first grid 6, second grid 7 and the second insulating barrier 5, to form the 3rd insulating barrier 8.Wherein, the 3rd insulating material can select oxide, nitride or oxynitrides.

Step 110: the region of corresponding polysilicon semiconductor layer forms the first via hole on the first insulating barrier, the second insulating barrier and the 3rd insulating barrier, and the region of corresponding metal oxide semiconductor layer forms the second via hole on the second insulating barrier and the 3rd insulating barrier.

Fig. 3 g is the schematic diagram forming the first via hole and the second via hole on each insulating barrier, as shown in figure 3g, form the first via hole 9 by a patterning processes with the region of corresponding polysilicon semiconductor layer 2 on the first insulating barrier 3, second insulating barrier 5 and the 3rd insulating barrier 8, on the second insulating barrier 6 and the 3rd insulating barrier 8, the region of corresponding metal oxide semiconductor layer 4 forms the second via hole 10 simultaneously.

Step 111: form the first source electrode, the first drain electrode, the second source electrode and the second drain electrode above the 3rd insulating barrier, first source electrode is connected with polysilicon semiconductor layer by the first via hole with the first drain electrode, and the second source electrode is connected with metal oxide semiconductor layer by the second via hole with the second drain electrode.

Fig. 3 h is the schematic diagram forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode above the 3rd insulating barrier, as illustrated in figure 3h, first, by the method for sputtering or thermal evaporation at disposed thereon one deck source and drain metal material of the 3rd insulating barrier 8; Then, a patterning processes is carried out to form the first source electrode 11, first drain electrode 12, second source electrode 13 and the second drain electrode 14 to source and drain metal material.Wherein the first source electrode 11 is connected with polysilicon semiconductor layer 2 by the first via hole 9 with the first drain electrode 12, and the second source electrode 13 is connected with metal oxide semiconductor layer 4 by the second via hole 10 with the second drain electrode 14.

Step 112: form the 4th insulating barrier above the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the 3rd insulating barrier, on 4th insulating barrier, the region of corresponding first drain electrode is formed with the 3rd via hole, and on the 4th insulating barrier, the region of corresponding second drain electrode is formed with the 4th via hole.

Fig. 3 i is the schematic diagram forming the 4th insulating barrier above the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the 3rd insulating barrier, as shown in figure 3i, first, to be drained 14 and the 3rd disposed thereon one deck the 4th insulating material of insulating barrier 8 at the first source electrode 11, first 12, second source electrode 13, second that drains by chemical gaseous phase depositing process; Then a patterning processes is carried out to the 4th insulating material, the 3rd via hole 16 is formed with the region of the first drain electrode 12 corresponding on the 4th insulating material, the region of corresponding second drain electrode 14 forms the 4th via hole 17, and the 4th remaining insulating material is to form the 4th insulating barrier 15.Wherein, the 4th insulating material can select oxide, nitride or oxynitrides.

Step 113: form the first pixel electrode and the second pixel electrode above the 4th insulating barrier, the first pixel electrode is drained by the 3rd via hole and first and is connected, and the second pixel electrode is drained by the 4th via hole and second and is connected.

See Fig. 1, first, the disposed thereon layer of transparent electric conducting material of the 4th insulating barrier 15 is deposited on by sputtering or the method for thermal evaporation; Then, a patterning processes is carried out to form the first pixel electrode 18 and the second pixel electrode 19 to transparent conductive material.Wherein, the first pixel electrode 18 is drained by the 3rd via hole 16 and first and 12 to be connected, and the second pixel 19 electrode passes through the 4th via hole 17 and second and drains and 14 to be connected, and alternatively, this transparent conductive material is tin indium oxide (Formula I TO).Flow process terminates.

It should be noted that, when the material of the metal oxide semiconductor layer 4 in metal oxide thin-film transistor is amorphous metal oxide, carry out crystallization processes process to amorphous silicon figure to perform before the step (step 104) of deposition one deck amorphous metal oxide with the step (step 106) forming polysilicon graphics, to prevent amorphous metal oxide to be converted into polysilicon oxide, its detailed process is not described in detail herein.

In addition, the patterning processes in the application includes the processing steps such as photoresist coating, exposure, development, etching, photoresist lift off.

The embodiment of the present invention one provides a kind of array base palte and manufacture method thereof, wherein, this array base palte comprises: the first film transistor and the second thin-film transistor, the first film transistor and the second thin-film transistor are formed at the top of underlay substrate, the first film transistor is polycrystalline SiTFT, second thin-film transistor is metal oxide thin-film transistor, and the first film transistor is positioned at the neighboring area of array base palte, and the second thin-film transistor is positioned at the viewing area of array base palte.Technical scheme of the present invention effectively can solve the problem that polycrystalline SiTFT cannot be applied to the production of the large scale display floater of more than 6G, thoroughly breaks through the restriction of Excimer-Laser Crystallization technique bottleneck, has very high using value.

Embodiment two

The schematic cross-section of the array base palte that Fig. 4 provides for the embodiment of the present invention one, as shown in Figure 4, this array base palte comprises: the first film transistor C and the second thin-film transistor D, the first film transistor C and the second thin-film transistor D is formed at the top of underlay substrate 1, the first film transistor C is polycrystalline SiTFT, second thin-film transistor D is amorphous silicon film transistor, the first film transistor C is positioned at the neighboring area of array base palte, and the second thin-film transistor D is positioned at the viewing area of array base palte.

In the present embodiment, on the one hand, relatively much higher for electron mobility polycrystal silicon film transistor is arranged on the neighboring area of array base palte, the neighboring area of large scale display floater can be met to the high request of the electron mobility of components and parts.On the other hand, because this polycrystalline SiTFT is only arranged on the neighboring area of array base palte, and the size of this neighboring area is less, therefore carrying out in the process of crystallization to amorphous silicon, existing Excimer-Laser Crystallization technique can meet uniformity requirements fully.In addition, in the viewing area of large scale display floater, tell somebody what one's real intentions are to the requirement for driving pixel cell to carry out the electron mobility of the thin-film transistor of pixel display, (electron mobility is at 0.5cm for amorphous silicon film transistor ²about/Vs) electron mobility be enough to the driving requirement meeting pixel cell.Technical scheme of the present invention, can solve the problem that polycrystalline SiTFT cannot be applied to the production of the large scale display floater of more than 6G effectively, thoroughly breaks through the restriction of Excimer-Laser Crystallization technique bottleneck, has very high using value.

In the present embodiment, this array base palte specifically comprises: polysilicon semiconductor layer 2, amorphous silicon semiconductor layer 20, pentasyllabic quatrain edge layer 21, first grid 6, second grid 7, the 6th insulating barrier 22, first source electrode 11, first drain electrode 12, second source electrode 13, second drain electrode 14, four-line poem with seven characters to a line edge layer 25, first pixel electrode 18 and the second pixel electrode 19.Wherein, polysilicon semiconductor layer 2 is formed at the top of underlay substrate 1, and polysilicon semiconductor layer 2 is positioned at the neighboring area of array base palte; Amorphous silicon semiconductor layer 20 is formed at the top of underlay substrate 1, and amorphous silicon semiconductor layer 20 is positioned at the viewing area of array base palte; Pentasyllabic quatrain edge layer 21 is formed at the top of amorphous silicon semiconductor layer 20, polysilicon semiconductor layer 2 and underlay substrate 1; First grid 6 and second grid 7 are formed at the top of pentasyllabic quatrain edge layer 21, and first grid 6 is positioned at the neighboring area of array base palte, and second grid 7 is positioned at the viewing area of array base palte; 6th insulating barrier 22 is formed at the top of first grid 6, second grid 7 and pentasyllabic quatrain edge layer 21, the region that on pentasyllabic quatrain edge layer 21 and the 6th insulating barrier 22, the region of corresponding polysilicon semiconductor layer 2 is formed with corresponding amorphous silicon semiconductor layer 20 on the 5th via hole 23, the pentasyllabic quatrain edge layer 21 and the 6th insulating barrier 22 is formed with the 6th via hole 24; First source electrode 11, first drain electrode 12, second source electrode 13 and the second drain electrode 14 are formed at the top of the 6th insulating barrier 22, first source electrode 11 is connected with polysilicon semiconductor layer 2 by the 5th via hole 23 with the first drain electrode 12, and the second source electrode 13 is connected with amorphous silicon semiconductor layer 20 by the 6th via hole 24 with the second drain electrode 14; Four-line poem with seven characters to a line edge layer 25 is formed at the top of the first source electrode 11, first drain electrode 12, second source electrode 13, second drain electrode 14 and the 6th insulating barrier 22, the region that in four-line poem with seven characters to a line edge layer 25, the region of corresponding first drain electrode 12 is formed with corresponding second drain electrode 14 in the 7th via hole 26, the four-line poem with seven characters to a line edge layer 25 is formed with the 8th via hole 27; First pixel electrode 18 and the second pixel electrode 19 are formed at the top of four-line poem with seven characters to a line edge layer 25, and the first pixel electrode 18 is drained by the 7th via hole 26 and first and 12 to be connected, and the second pixel electrode 19 passes through the 8th via hole 27 and second and drains and 14 to be connected.

It should be noted that, polysilicon semiconductor layer 2 in the present embodiment, first grid 6, first source electrode 11 and the first drain electrode 12 form polycrystalline SiTFT, amorphous silicon semiconductor layer 20, second grid 7, second source electrode 13 and the second drain electrode 14 form amorphous silicon film transistor, and each insulating barrier is to coordinate the needs of the course of processing to arrange accordingly.

The embodiment of the present invention two additionally provides a kind of manufacture method preparing array base palte, and this manufacture method comprises:

Step S2: form the first film transistor and the second thin-film transistor above underlay substrate 1, the first film transistor is polycrystalline SiTFT, second thin-film transistor is amorphous silicon film transistor, the first film transistor is positioned at the neighboring area of array base palte, and the second thin-film transistor is positioned at the viewing area of array base palte.

The array base palte shown in Fig. 4 can be prepared by step S2.Below in conjunction with accompanying drawing being described in detail with the concrete manufacture process to the array base palte shown in Fig. 4.

Fig. 5 is the flow chart of the manufacture method of array base palte shown in Fig. 4, and as shown in Figure 5, step S2 specifically comprises:

Step 201: form amorphous silicon semiconductor layer and polysilicon semiconductor layer above underlay substrate, amorphous silicon semiconductor layer is positioned at the viewing area of array base palte, and polysilicon semiconductor layer is positioned at the neighboring area of array base palte.

Fig. 6 a is the schematic diagram forming amorphous silicon semiconductor layer and polysilicon semiconductor layer above underlay substrate, and as shown in Figure 6 a, step 201 specifically comprises:

Step 2011: at disposed thereon one deck amorphous silicon material of underlay substrate.

Step 2012: carry out patterning processes to amorphous silicon material, all to form amorphous silicon figure at the fringe region of array base palte and viewing area, the amorphous silicon figure being positioned at the viewing area of underlay substrate forms amorphous silicon semiconductor layer.

Step 2013: crystallization processes process is carried out to the amorphous silicon figure of the neighboring area being positioned at underlay substrate, to make the amorphous silicon graphics of the neighboring area being positioned at underlay substrate for polysilicon graphics, the polysilicon graphics being positioned at the neighboring area of underlay substrate forms polysilicon semiconductor layer.

In the present embodiment, amorphous silicon semiconductor layer and polysilicon semiconductor layer synchronously formed and effectively can reduce production procedure, shorten the production cycle, promote and produce line efficiency.

Step 202: form pentasyllabic quatrain edge layer above amorphous silicon semiconductor layer, polysilicon semiconductor layer and underlay substrate.

Fig. 6 b is the schematic diagram forming pentasyllabic quatrain edge layer above amorphous silicon semiconductor layer, polysilicon semiconductor layer and underlay substrate, as shown in Figure 6 b, by disposed thereon one deck the 5th insulating material of chemical gaseous phase depositing process amorphous silicon semiconductor layer 20, polysilicon semiconductor layer 2 and underlay substrate 1, to form pentasyllabic quatrain edge layer 21, the 5th insulating material can select oxide, nitride or oxynitrides.

Step 203: form first grid and second grid above pentasyllabic quatrain edge layer, first grid is positioned at the neighboring area of array base palte, and second grid is positioned at the viewing area of array base palte.

Fig. 6 c is the schematic diagram forming first grid and second grid 7 above pentasyllabic quatrain edge layer 21, as fig. 6 c, first, by the method for sputtering or thermal evaporation at disposed thereon one deck grid metal material of pentasyllabic quatrain edge layer 21; Then, a patterning processes is carried out to form first grid 6 and second grid 7 to grid metal material.Wherein, first grid 6 is positioned at the neighboring area of array base palte, and second grid 7 is positioned at the viewing area of array base palte.

Step 204: form the 6th insulating barrier above first grid, second grid and pentasyllabic quatrain edge layer.

Fig. 6 d is the schematic diagram forming the 6th insulating barrier above first grid, second grid and pentasyllabic quatrain edge layer, as shown in fig 6d, by disposed thereon one deck six insulating material of chemical gaseous phase depositing process in first grid 6, second grid 7 and pentasyllabic quatrain edge layer 21, to form the 6th insulating barrier 22.Wherein, the 6th insulating material can select oxide, nitride or oxynitrides.

Step 205: the region of corresponding polysilicon semiconductor layer forms the 5th via hole in pentasyllabic quatrain edge layer and the 6th insulating barrier, and the region of corresponding amorphous silicon semiconductor layer forms the 6th via hole in pentasyllabic quatrain edge layer and the 6th insulating barrier.

Fig. 6 e is the schematic diagram forming the 5th via hole and the 6th via hole on pentasyllabic quatrain edge layer, the 6th insulating barrier, as shown in figure 3g, form the 5th via hole 23 by a patterning processes with the region of corresponding polysilicon semiconductor layer 2 in pentasyllabic quatrain edge layer 21 and the 6th insulating barrier 22, in pentasyllabic quatrain edge layer 21 and the 6th insulating barrier 22, the region of corresponding amorphous silicon semiconductor layer 20 forms the 6th via hole 24 simultaneously.

Step 206: form the first source electrode, the first drain electrode, the second source electrode and the second drain electrode above the 6th insulating barrier, first source electrode is connected with polysilicon semiconductor layer by the 5th via hole with the first drain electrode, and the second source electrode is connected with amorphous silicon semiconductor layer by the 6th via hole with the second drain electrode.

Fig. 6 f is the schematic diagram forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode above the 6th insulating barrier, as shown in Figure 6 f, first, by the method for sputtering or thermal evaporation at disposed thereon one deck source and drain metal material of the 6th insulating barrier 22; Then, a patterning processes is carried out to form the first source electrode 11, first drain electrode 12, second source electrode 13 and the second drain electrode 14 to source and drain metal material.Wherein the first source electrode 11 is connected with polysilicon semiconductor layer 2 by the 5th via hole 23 with the first drain electrode 12, and the second source electrode 13 is connected with amorphous silicon semiconductor layer 20 by the 6th via hole 24 with the second drain electrode 14.

Step 207: form four-line poem with seven characters to a line edge layer above the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the 6th insulating barrier, in four-line poem with seven characters to a line edge layer, the region of corresponding first drain electrode is formed with the 7th via hole, and in four-line poem with seven characters to a line edge layer, the region of corresponding second drain electrode is formed with the 8th via hole.

Fig. 6 g is the schematic diagram forming four-line poem with seven characters to a line edge layer above the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the 6th insulating barrier, as shown in figure 6g, first, to be drained 14 and the 3rd disposed thereon one deck the 7th insulating material of insulating barrier at the first source electrode 11, first 12, second source electrode 13, second that drains by chemical gaseous phase depositing process; Then, a patterning processes is carried out to the 7th insulating material, form the 7th via hole 26 with the region of the first drain electrode 12 corresponding on the 7th insulating material, the region of corresponding second drain electrode 14 forms the 8th via hole 27, and the 7th remaining insulating material is to form four-line poem with seven characters to a line edge layer 25.Wherein, the 7th insulating material can select oxide, nitride or oxynitrides.

Step 208: form the first pixel electrode and the second pixel electrode above four-line poem with seven characters to a line edge layer, the first pixel electrode is drained by the 7th via hole and first and is connected, and the second pixel electrode is drained by the 8th via hole and second and is connected.

See Fig. 4, first, the disposed thereon layer of transparent electric conducting material of four-line poem with seven characters to a line edge layer 25 is deposited on by sputtering or the method for thermal evaporation; Then, a patterning processes is carried out to form the first pixel electrode 18 and the second pixel electrode 19 to transparent conductive material.Wherein, the first pixel electrode 18 is drained by the 7th via hole 26 and first and 12 to be connected, and the second pixel electrode 19 passes through the 8th via hole 27 and second and drains and 14 to be connected.Flow process terminates.

The embodiment of the present invention two provides a kind of array base palte and manufacture method thereof, wherein, this array base palte comprises: the first film transistor and the second thin-film transistor, the first film transistor and the second thin-film transistor are formed at the top of underlay substrate, the first film transistor is polycrystalline SiTFT, second thin-film transistor is amorphous silicon film transistor, and the first film transistor is positioned at the neighboring area of array base palte, and the second thin-film transistor is positioned at the viewing area of array base palte.Technical scheme of the present invention effectively can solve the problem that polycrystalline SiTFT cannot be applied to the production of the large scale display floater of more than 6G, thoroughly breaks through the restriction of Excimer-Laser Crystallization technique bottleneck, has very high using value.

Embodiment three

The embodiment of the present invention three provides a kind of display unit, this display unit comprises array base palte, the array base palte that this array base palte adopts above-described embodiment one or embodiment two to provide, particular content see the description in above-described embodiment one and embodiment two, can repeat no more herein.

Display unit in the present embodiment can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.

The display unit provided due to the present embodiment three comprises the array base palte in above-described embodiment one or embodiment two, and therefore the present embodiment possesses above-described embodiment one or the Advantageous Effects described in embodiment two.

Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.

Claims

1. a manufacture method for array base palte, is characterized in that, comprising:

2. the manufacture method of array base palte according to claim 1, it is characterized in that, described second thin-film transistor is metal oxide thin-film transistor, described the first film transistor comprises: polysilicon semiconductor layer, described second thin-film transistor comprises: metal-oxide semiconductor layer, and the material of described metal oxide semiconductor layer is amorphous metal oxide;

3. the manufacture method of array base palte according to claim 1, it is characterized in that, described second thin-film transistor is metal oxide thin-film transistor, described the first film transistor comprises: polysilicon semiconductor layer, described second thin-film transistor comprises: metal-oxide semiconductor layer, and the material of described metal oxide semiconductor layer is crystalline metal-oxide;

4. according to the manufacture method of the array base palte described in Claims 2 or 3, it is characterized in that, described the first film transistor also comprises: first grid, the first source electrode and the first drain electrode, and described second thin-film transistor also comprises: second grid, the second source electrode and the second drain electrode;

Also comprise after forming the step of metal oxide semiconductor layer:

5. the manufacture method of array base palte according to claim 1, it is characterized in that, described second thin-film transistor is amorphous silicon film transistor, and described the first film transistor comprises: polysilicon semiconductor layer, and described second thin-film transistor comprises: amorphous silicon semiconductor layer;

6. the manufacture method of array base palte according to claim 5, it is characterized in that, described the first film transistor also comprises: first grid, the first source electrode and the first drain electrode, and described second thin-film transistor also comprises: second grid, the second source electrode and the second drain electrode;

Also comprise after forming the step of polysilicon semiconductor layer:

7. the manufacture method of the array base palte according to claim 2,3 or 5, is characterized in that, described crystallization processes process comprises: solid phase crystallization process, laser crystallization technique or thermal anneal process.

8. an array base palte, it is characterized in that, comprise: the first film transistor and the second thin-film transistor, described the first film transistor and described second thin-film transistor are formed at the top of underlay substrate, described the first film transistor is polycrystalline SiTFT, described second thin-film transistor is metal oxide thin-film transistor or amorphous silicon film transistor, described the first film transistor is positioned at the neighboring area of described array base palte, and described second thin-film transistor is positioned at the viewing area of described array base palte.

9. array base palte according to claim 8, is characterized in that, described second thin-film transistor is metal oxide thin-film transistor, and described array base palte specifically comprises:

10. array base palte according to claim 8 or claim 9, it is characterized in that, the material of described metal oxide semiconductor layer is crystalline metal-oxide.

11. array base paltes according to claim 8, is characterized in that, described second thin-film transistor is amorphous silicon film transistor, and described array base palte specifically comprises:

12. 1 kinds of display unit, is characterized in that, comprising: as the array base palte as described in arbitrary in the claims 8-11.